RV_TIMER Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	38.143m	337.590ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.600s	74.511us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.620s	55.772us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.600s	1.699ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	120.305us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.740s	32.805us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.620s	55.772us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	120.305us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	57.346m	93.457ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.140m	701.561ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	37.267m	8.965s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	37.267m	8.965s	50	50	100.00
V2	stress	rv_timer_stress_all	1.755h	2.367s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.620s	16.181us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.960s	138.551us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.960s	138.551us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.600s	74.511us	5	5	100.00
		rv_timer_csr_rw	0.620s	55.772us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	120.305us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	128.457us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.600s	74.511us	5	5	100.00
		rv_timer_csr_rw	0.620s	55.772us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	120.305us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	128.457us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	0.920s	83.911us	5	5	100.00
		rv_timer_tl_intg_err	1.480s	219.557us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.480s	219.557us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	33.031m	328.032ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			618	620	99.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.59	99.36	98.73	100.00	--	100.00	100.00	99.43

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test rv_timer_disabled has 1 failures.

    • 43.rv_timer_disabled.90916084088982025075746341929806687584148728876431432369582221136445568100666
      Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test rv_timer_random has 1 failures.

    • 178.rv_timer_random.54769339800498177820791181749361331332683242233736931947251048191336932521263
      Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/178.rv_timer_random/latest/run.log

        Job ID: smart:385f6a2e-0e49-4569-ad95-4583a99a2ce7
      

Past Results

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