RV_TIMER Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 40.758m 232.762ms 199 200 99.50
V1 csr_hw_reset rv_timer_csr_hw_reset 0.600s 76.456us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.640s 14.767us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.700s 416.414us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.790s 435.981us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.380s 32.857us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.640s 14.767us 20 20 100.00
rv_timer_csr_aliasing 0.790s 435.981us 5 5 100.00
V1 TOTAL 254 255 99.61
V2 random_reset rv_timer_random_reset 15.521m 188.928ms 50 50 100.00
V2 disabled rv_timer_disabled 5.971m 859.911ms 47 50 94.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 31.382m 6.995s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 31.382m 6.995s 50 50 100.00
V2 stress rv_timer_stress_all 1.607h 1.081s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.610s 15.639us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.300s 171.265us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.300s 171.265us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.600s 76.456us 5 5 100.00
rv_timer_csr_rw 0.640s 14.767us 20 20 100.00
rv_timer_csr_aliasing 0.790s 435.981us 5 5 100.00
rv_timer_same_csr_outstanding 0.830s 128.317us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.600s 76.456us 5 5 100.00
rv_timer_csr_rw 0.640s 14.767us 20 20 100.00
rv_timer_csr_aliasing 0.790s 435.981us 5 5 100.00
rv_timer_same_csr_outstanding 0.830s 128.317us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err rv_timer_sec_cm 0.850s 260.226us 5 5 100.00
rv_timer_tl_intg_err 1.470s 134.953us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.470s 134.953us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 27.647m 138.192ms 11 50 22.00
V3 TOTAL 11 50 22.00
TOTAL 577 620 93.06

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 7 7 6 85.71
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.59 99.36 98.73 100.00 -- 100.00 100.00 99.43

Failure Buckets

Past Results