RV_TIMER Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	59.282m	642.259ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.580s	29.234us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.630s	13.913us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.680s	2.530ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.850s	39.931us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.630s	121.872us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.630s	13.913us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	39.931us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	27.301m	149.999ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.857m	990.214ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	20.617m	1.966s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	20.617m	1.966s	50	50	100.00
V2	stress	rv_timer_stress_all	1.263h	735.927ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.620s	42.210us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.960s	278.653us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.960s	278.653us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.580s	29.234us	5	5	100.00
		rv_timer_csr_rw	0.630s	13.913us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	39.931us	5	5	100.00
		rv_timer_same_csr_outstanding	0.820s	22.662us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.580s	29.234us	5	5	100.00
		rv_timer_csr_rw	0.630s	13.913us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	39.931us	5	5	100.00
		rv_timer_same_csr_outstanding	0.820s	22.662us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.950s	102.728us	5	5	100.00
		rv_timer_tl_intg_err	1.480s	723.988us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.480s	723.988us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	21.404m	466.906ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			582	620	93.87

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.59	99.36	98.73	100.00	--	100.00	100.00	99.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test rv_timer_stress_all_with_rand_reset has 34 failures.
  - 0.rv_timer_stress_all_with_rand_reset.16680556998492482492858305950375390821963282838348323090149187348933804938606
    Line 276, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11697620343 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11697620343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.24623107638492722493188555468528006339193913320546009597655918685994676086730
    Line 310, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 152584151281 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 152584151281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_disabled has 2 failures.
  - 6.rv_timer_disabled.59327594878348733551156288482893847076684948907111277347268310822752376949601
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.rv_timer_disabled.81416683255994113823920999963092275141094664673717126734552649357664189025316
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:752) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 1.rv_timer_stress_all_with_rand_reset.27626815075999975953907068855473194060295569936320665941633466566436888972905
    Line 482, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34697704213 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 34697704213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 47.rv_timer_random.14075666980715828025547147090677000557029821800379611866371719774632801401069
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_random/latest/run.log
```
  Job ID: smart:46a3f65f-af52-4872-9f02-48bf7da38245
```

RV_TIMER Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f92a5ee77b`