RV_TIMER Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 43.564m 98.676ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.610s 24.874us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.610s 55.972us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.650s 973.217us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.830s 128.396us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.580s 152.058us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.610s 55.972us 20 20 100.00
rv_timer_csr_aliasing 0.830s 128.396us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 28.953m 298.142ms 50 50 100.00
V2 disabled rv_timer_disabled 6.200m 868.666ms 47 50 94.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 19.292m 696.846ms 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 19.292m 696.846ms 50 50 100.00
V2 stress rv_timer_stress_all 46.862m 2.413s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.660s 40.142us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 2.890s 60.521us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 2.890s 60.521us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.610s 24.874us 5 5 100.00
rv_timer_csr_rw 0.610s 55.972us 20 20 100.00
rv_timer_csr_aliasing 0.830s 128.396us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 147.090us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.610s 24.874us 5 5 100.00
rv_timer_csr_rw 0.610s 55.972us 20 20 100.00
rv_timer_csr_aliasing 0.830s 128.396us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 147.090us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err rv_timer_sec_cm 0.910s 164.576us 5 5 100.00
rv_timer_tl_intg_err 1.420s 440.931us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.420s 440.931us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 21.032m 101.192ms 13 50 26.00
V3 TOTAL 13 50 26.00
TOTAL 580 620 93.55

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.57 99.36 98.73 100.00 -- 100.00 100.00 99.32

Failure Buckets

Past Results