RV_TIMER Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	56.381m	1.004s	198	200	99.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.610s	19.354us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.620s	20.341us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.320s	829.903us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.730s	47.912us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.570s	41.511us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.620s	20.341us	20	20	100.00
		rv_timer_csr_aliasing	0.730s	47.912us	5	5	100.00
V1		TOTAL			253	255	99.22
V2	random_reset	rv_timer_random_reset	20.363m	79.504ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.856m	641.619ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	24.098m	3.205s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	24.098m	3.205s	50	50	100.00
V2	stress	rv_timer_stress_all	50.101m	1.326s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.630s	21.487us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.090s	229.850us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.090s	229.850us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.610s	19.354us	5	5	100.00
		rv_timer_csr_rw	0.620s	20.341us	20	20	100.00
		rv_timer_csr_aliasing	0.730s	47.912us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	41.977us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.610s	19.354us	5	5	100.00
		rv_timer_csr_rw	0.620s	20.341us	20	20	100.00
		rv_timer_csr_aliasing	0.730s	47.912us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	41.977us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	0.960s	321.530us	5	5	100.00
		rv_timer_tl_intg_err	1.410s	512.036us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.410s	512.036us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	21.619m	207.317ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			576	620	92.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.55	99.36	98.73	100.00	--	100.00	100.00	99.21

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:
- Test rv_timer_stress_all_with_rand_reset has 39 failures.
  - 0.rv_timer_stress_all_with_rand_reset.12079650194719718937227474810384051572818189997175173926312775868461297675697
    Line 885, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59919189065 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 59919189065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.66575782043620191288744447861836334981796256036799982809443669413450873249101
    Line 498, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20646388907 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20646388907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 37 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 2.rv_timer_stress_all_with_rand_reset.64259767334616475246250971161291912288206501498440629987280195737679706216687
    Line 1413, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 464347071290 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 464347071290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_timer_stress_all_with_rand_reset.9346126554442304013193449173304414190271794018276624011803751223431909480111
    Line 323, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24939063678 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 24939063678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test rv_timer_random has 2 failures.
  - 6.rv_timer_random.81392650666390113688352351563805155824798543604644928262939897175447189433315
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_random/latest/run.log
```
  Job ID: smart:9e1cbe2a-c083-4436-ac0a-c9f122fb68d9
```
  - 17.rv_timer_random.100422081934444061042885418244622089080137299959977548634991855688095836266672
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_random/latest/run.log
```
  Job ID: smart:e59ad0ee-2af0-485c-8161-eca64633cf70
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rv_timer_disabled has 1 failures.
  - 22.rv_timer_disabled.104214303909397481069450868955981221654256783905864174344519274303482728934123
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8cb25a6867`