dd5ad5fb77| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 36.883m | 864.420ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 46.690us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 27.450us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.510s | 1.871ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.810s | 496.693us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.560s | 38.255us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 27.450us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.810s | 496.693us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 13.574m | 164.373ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.272m | 733.030ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 26.296m | 6.935s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 26.296m | 6.935s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.191h | 1.545s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.650s | 56.511us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.580s | 187.156us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.580s | 187.156us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 46.690us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 27.450us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 496.693us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 18.392us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 46.690us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 27.450us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 496.693us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 18.392us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.890s | 155.778us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.400s | 918.981us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.400s | 918.981us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 18.831m | 346.008ms | 17 | 50 | 34.00 |
| V3 | TOTAL | 17 | 50 | 34.00 | |||
| TOTAL | 585 | 620 | 94.35 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.57 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.32 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
0.rv_timer_stress_all_with_rand_reset.108908892596404097806245038829199579538086260884044804446256805955302224617388
Line 432, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 137064244991 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 137064244991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.18812175564807989043846036267231237798823522956075883257194646169947279416898
Line 515, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16749526210 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16749526210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
33.rv_timer_disabled.65292879960439015405433957436822832398272760793881286373131472414016733298787
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
169.rv_timer_random.45209498572016610658329131348872427679025789030512132265085221183409044992173
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/169.rv_timer_random/latest/run.log
Job ID: smart:a9607ca9-fdb6-4d19-a151-492d4b09e388