8fdb25c8d9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.462m | 210.969ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 51.965us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.610s | 46.137us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.100s | 424.770us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.850s | 19.064us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.360s | 109.739us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.610s | 46.137us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.850s | 19.064us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 21.542m | 303.279ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.216m | 995.978ms | 45 | 50 | 90.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 19.094m | 2.246s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 19.094m | 2.246s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.116h | 611.905ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 83.309us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.860s | 322.339us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.860s | 322.339us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 51.965us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 46.137us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 19.064us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 41.374us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 51.965us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 46.137us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 19.064us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 41.374us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.920s | 76.969us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.370s | 598.486us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.370s | 598.486us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 19.927m | 310.702ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 574 | 620 | 92.58 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.53 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.09 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:
1.rv_timer_stress_all_with_rand_reset.33761480582990351805710824836062262150391386235126811536235291957991134541638
Line 542, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24892480765 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24892480765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.95250484085554587805834577947781215679748113825022141387340319029670323282658
Line 903, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 194997006504 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 194997006504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
11.rv_timer_disabled.69586048028384803892290877438608844481305825679418431326901621223235085002493
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_timer_disabled.4279410965365877208467269424968067911542490813971165397219639619684424444156
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.