eca25c0ff8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 53.120m | 642.553ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 53.177us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 18.767us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.660s | 570.909us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.810s | 58.591us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.420s | 62.066us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 18.767us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.810s | 58.591us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 28.951m | 194.705ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.826m | 874.447ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 24.214m | 835.721ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 24.214m | 835.721ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.033h | 691.691ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.590s | 63.443us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.170s | 154.543us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.170s | 154.543us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 53.177us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 18.767us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 58.591us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 125.929us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 53.177us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 18.767us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 58.591us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 125.929us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.920s | 347.503us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.340s | 124.276us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.340s | 124.276us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 29.762m | 375.239ms | 14 | 50 | 28.00 |
| V3 | TOTAL | 14 | 50 | 28.00 | |||
| TOTAL | 579 | 620 | 93.39 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.49 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.87 |
UVM_ERROR (cip_base_vseq.sv:839) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
1.rv_timer_stress_all_with_rand_reset.65853803709978059289326185211745746419294822543477854898984694881270454883233
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2633839244 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2633839244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.16892371375006824945826734933810127618157560458319028910533076933065444328577
Line 387, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56590092700 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 56590092700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
8.rv_timer_disabled.89963608348233904668659015546496146387216099365405314653326266843388213518825
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_timer_disabled.106062846703321565256935141359226068748227131437929274744897139781685919292896
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:758) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
36.rv_timer_stress_all_with_rand_reset.103440212927855994679055460292289937439209044908692753583809426704356681967613
Line 495, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75346134146 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 75346134146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
77.rv_timer_random.34923708940886693863954794473879117583494234021038611315482741326975562300009
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/77.rv_timer_random/latest/run.log
Job ID: smart:d6931781-4ac5-443c-8b7b-9037204527c1