0bfa990ddc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 55.052m | 172.457ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 36.542us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.650s | 15.491us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.540s | 3.058ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.760s | 14.871us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.590s | 317.629us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.650s | 15.491us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.760s | 14.871us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 36.753m | 286.756ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.819m | 420.096ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 18.386m | 1.985s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 18.386m | 1.985s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.151h | 790.399ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.640s | 19.262us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.680s | 69.045us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.680s | 69.045us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 36.542us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 15.491us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 14.871us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 69.300us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 36.542us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 15.491us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 14.871us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.830s | 69.300us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.960s | 82.552us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 198.238us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 198.238us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 29.728m | 264.355ms | 14 | 50 | 28.00 |
| V3 | TOTAL | 14 | 50 | 28.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:839) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
0.rv_timer_stress_all_with_rand_reset.109891120446329478350724234859496141937116274981064520191733218584994610148657
Line 489, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26192013097 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 26192013097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.12997499731528908273661925686744015911199799718846748337276978235825925827634
Line 322, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28072904631 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10061 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 28072904631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
0.rv_timer_disabled.57016852281347964565620099622224428944881809535585491758360856556175928399280
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_disabled.78670330432325488460238944754717766179078125871080447848217178559554221948984
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.