RV_TIMER Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 55.052m 172.457ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.600s 36.542us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.650s 15.491us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.540s 3.058ms 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.760s 14.871us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.590s 317.629us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.650s 15.491us 20 20 100.00
rv_timer_csr_aliasing 0.760s 14.871us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 36.753m 286.756ms 50 50 100.00
V2 disabled rv_timer_disabled 4.819m 420.096ms 46 50 92.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 18.386m 1.985s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 18.386m 1.985s 50 50 100.00
V2 stress rv_timer_stress_all 1.151h 790.399ms 50 50 100.00
V2 intr_test rv_timer_intr_test 0.640s 19.262us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.680s 69.045us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.680s 69.045us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.600s 36.542us 5 5 100.00
rv_timer_csr_rw 0.650s 15.491us 20 20 100.00
rv_timer_csr_aliasing 0.760s 14.871us 5 5 100.00
rv_timer_same_csr_outstanding 0.830s 69.300us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.600s 36.542us 5 5 100.00
rv_timer_csr_rw 0.650s 15.491us 20 20 100.00
rv_timer_csr_aliasing 0.760s 14.871us 5 5 100.00
rv_timer_same_csr_outstanding 0.830s 69.300us 20 20 100.00
V2 TOTAL 286 290 98.62
V2S tl_intg_err rv_timer_sec_cm 0.960s 82.552us 5 5 100.00
rv_timer_tl_intg_err 1.410s 198.238us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.410s 198.238us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 29.728m 264.355ms 14 50 28.00
V3 TOTAL 14 50 28.00
TOTAL 580 620 93.55

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.62 99.36 98.73 100.00 -- 100.00 100.00 99.66

Failure Buckets

Past Results