3e0219a2c5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 50.745m | 315.726ms | 198 | 200 | 99.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.620s | 16.191us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 25.601us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.250s | 89.955us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.820s | 63.335us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.110s | 96.084us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 25.601us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.820s | 63.335us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 253 | 255 | 99.22 | |||
| V2 | random_reset | rv_timer_random_reset | 17.419m | 37.480ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.521m | 430.190ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 17.951m | 1.235s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 17.951m | 1.235s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.544h | 6.149s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 15.334us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.230s | 397.923us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.230s | 397.923us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.620s | 16.191us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 25.601us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 63.335us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.910s | 80.155us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.620s | 16.191us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 25.601us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 63.335us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.910s | 80.155us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 290 | 290 | 100.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.840s | 356.819us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.570s | 463.840us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.570s | 463.840us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 27.744m | 262.302ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 577 | 620 | 93.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 7 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:839) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:
0.rv_timer_stress_all_with_rand_reset.72791982737733629615429735391269783069810284154072661643844574745903899116065
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 918703738 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 918703738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.23141612675533714189690333599030612780115649893543438930511491894919536287922
Line 758, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 77378886919 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 77378886919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
4.rv_timer_random.41034961239552312484322056971270805617569715537327178163549009310400949595405
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_random/latest/run.log
Job ID: smart:48a1a85d-57a0-420e-b88b-37aaa03ebd6d
15.rv_timer_random.56290178533138509174592674770916359013598260506971982081624558222097164969132
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_random/latest/run.log
Job ID: smart:6287a6c0-5325-44b5-9db3-dd58bd5d99ac