39f3866b56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 53.980m | 776.213ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.660s | 160.046us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.600s | 23.605us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.670s | 3.703ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.850s | 123.160us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.230s | 30.912us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.600s | 23.605us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.850s | 123.160us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 12.478m | 507.604ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.744m | 981.146ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 19.886m | 4.911s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 19.886m | 4.911s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.169h | 1.113s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 27.271us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.790s | 150.010us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.790s | 150.010us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.660s | 160.046us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.600s | 23.605us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 123.160us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.780s | 18.644us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.660s | 160.046us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.600s | 23.605us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 123.160us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.780s | 18.644us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.900s | 90.467us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.380s | 208.513us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.380s | 208.513us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 26.877m | 158.853ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 580 | 620 | 93.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.64 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
1.rv_timer_stress_all_with_rand_reset.87494911584536328036570043547882774913269284286455951026622429395777629945270
Line 437, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21589251040 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21589251040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.109481534324879333471349412960670661698609855874464304781520258477408047658106
Line 860, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 74912544726 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10039 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 74912544726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
10.rv_timer_disabled.37505340194602631278975707868601659641894161122331088423161992654326362917030
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_timer_disabled.1116528786865556489997823109408243070568185395067518791517845871058969921086
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---