fdfa12db04| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 54.555m | 115.183ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 19.141us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 35.022us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.670s | 373.273us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.800s | 31.902us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.890s | 42.050us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 35.022us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.800s | 31.902us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 16.587m | 243.970ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 5.757m | 229.210ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 21.114m | 3.968s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 21.114m | 3.968s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.323h | 2.068s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 55.142us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.780s | 137.692us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.780s | 137.692us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 19.141us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 35.022us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.800s | 31.902us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 67.936us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 19.141us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 35.022us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.800s | 31.902us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 67.936us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.140s | 444.789us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.440s | 147.908us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.440s | 147.908us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 28.166m | 163.327ms | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 586 | 620 | 94.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
2.rv_timer_stress_all_with_rand_reset.24289459509602426626621747020193135510603806036115067577799955436575728196143
Line 479, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 71962446680 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 71962446680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_timer_stress_all_with_rand_reset.46801279879493592884822885795376146641082612497543169243157710350091172512620
Line 664, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111187176071 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111187176071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test rv_timer_disabled has 1 failures.
39.rv_timer_disabled.25140066816427854088932301720637934440040865706312447927169404015690484059812
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
45.rv_timer_random_reset.77753196146957893746335703280556337736595399258027841425787383441247718586377
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/45.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
35.rv_timer_stress_all_with_rand_reset.55040099033146126060341312091849476966870777603620886909401050133593309614123
Line 930, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 236524331472 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 236524331472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---