Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59437665	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60415483	1		T1	13		T2	1		T3	182

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	118992095	1		T1	9		T2	1		T3	320
values[0x0]	409773	1		T1	5		T3	10		T5	6
values[0x1]	451280	1		T1	5		T3	8		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47475335	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	72377813	1		T1	15		T2	1		T3	220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	352765	1		T3	4		T5	37		T7	2
valid_sources[0x01]	1325036	1		T5	11		T7	2		T14	45
valid_sources[0x02]	352296	1		T3	1		T5	2		T7	2
valid_sources[0x03]	1432619	1		T3	3		T5	54		T7	3
valid_sources[0x04]	354751	1		T5	7		T7	4		T14	54
valid_sources[0x05]	352987	1		T5	60		T7	2		T14	40
valid_sources[0x06]	1246049	1		T3	1		T5	66		T7	1
valid_sources[0x07]	354350	1		T3	1		T5	73		T7	1
valid_sources[0x08]	358194	1		T3	1		T5	50		T10	2
valid_sources[0x09]	351161	1		T3	1		T5	2		T7	3
valid_sources[0x0a]	353245	1		T5	38		T7	2		T14	33
valid_sources[0x0b]	354240	1		T5	38		T7	3		T14	43
valid_sources[0x0c]	352110	1		T3	2		T5	34		T7	2
valid_sources[0x0d]	358169	1		T5	4		T7	1		T10	3
valid_sources[0x0e]	353581	1		T3	4		T5	38		T7	2
valid_sources[0x0f]	350431	1		T3	2		T5	53		T7	2
valid_sources[0x10]	351783	1		T3	2		T5	42		T7	3
valid_sources[0x11]	371894	1		T5	11		T7	1		T14	42
valid_sources[0x12]	353970	1		T3	1		T5	21		T7	3
valid_sources[0x13]	355237	1		T5	63		T7	2		T14	39
valid_sources[0x14]	354114	1		T3	7		T5	72		T7	2
valid_sources[0x15]	353015	1		T3	2		T5	52		T7	2
valid_sources[0x16]	351759	1		T3	2		T5	33		T7	1
valid_sources[0x17]	354239	1		T3	1		T5	51		T7	4
valid_sources[0x18]	487413	1		T3	3		T5	45		T7	1
valid_sources[0x19]	353800	1		T5	81		T14	41		T15	14
valid_sources[0x1a]	493442	1		T3	1		T5	2		T7	3
valid_sources[0x1b]	350977	1		T3	1		T5	45		T7	3
valid_sources[0x1c]	386197	1		T3	4		T5	30		T10	1
valid_sources[0x1d]	354400	1		T3	1		T5	115		T7	4
valid_sources[0x1e]	354118	1		T3	4		T5	87		T7	3
valid_sources[0x1f]	1523025	1		T3	1		T5	25		T7	1
valid_sources[0x20]	351886	1		T3	1		T5	25		T7	2
valid_sources[0x21]	350781	1		T3	1		T5	26		T7	1
valid_sources[0x22]	353373	1		T3	1		T5	70		T10	3
valid_sources[0x23]	354521	1		T3	1		T5	23		T7	1
valid_sources[0x24]	353951	1		T3	1		T5	5		T10	1
valid_sources[0x25]	354378	1		T3	1		T5	57		T7	4
valid_sources[0x26]	354191	1		T5	36		T7	3		T14	44
valid_sources[0x27]	352781	1		T3	3		T5	100		T7	5
valid_sources[0x28]	349635	1		T3	2		T5	2		T7	2
valid_sources[0x29]	1018557	1		T5	27		T7	4		T10	3
valid_sources[0x2a]	353274	1		T5	50		T10	3		T14	44
valid_sources[0x2b]	454436	1		T3	1		T5	10		T14	41
valid_sources[0x2c]	1175424	1		T5	54		T14	43		T15	26
valid_sources[0x2d]	660488	1		T3	2		T5	91		T7	3
valid_sources[0x2e]	351113	1		T3	1		T5	22		T7	1
valid_sources[0x2f]	353239	1		T3	1		T5	21		T7	4
valid_sources[0x30]	352225	1		T3	2		T5	64		T10	2
valid_sources[0x31]	354589	1		T3	5		T5	66		T10	3
valid_sources[0x32]	4134771	1		T3	2		T5	22		T7	1
valid_sources[0x33]	351081	1		T3	3		T5	35		T7	2
valid_sources[0x34]	351010	1		T5	38		T7	2		T14	49
valid_sources[0x35]	349102	1		T5	122		T7	1		T14	41
valid_sources[0x36]	442916	1		T1	2		T3	3		T5	30
valid_sources[0x37]	2765878	1		T3	2		T5	134		T10	3
valid_sources[0x38]	357731	1		T1	1		T3	2		T5	46
valid_sources[0x39]	386406	1		T3	2		T5	18		T14	65
valid_sources[0x3a]	354576	1		T3	4		T5	12		T7	1
valid_sources[0x3b]	352967	1		T5	31		T7	2		T10	1
valid_sources[0x3c]	353025	1		T3	1		T5	16		T7	1
valid_sources[0x3d]	356987	1		T5	23		T7	1		T10	1
valid_sources[0x3e]	399932	1		T1	1		T3	1		T5	8
valid_sources[0x3f]	349582	1		T3	1		T5	75		T14	41
valid_sources[0x40]	513335	1		T7	1		T14	52		T15	38
valid_sources[0x41]	357732	1		T3	3		T5	130		T14	47
valid_sources[0x42]	703500	1		T5	112		T7	2		T14	50
valid_sources[0x43]	5432747	1		T5	3		T7	1		T10	6
valid_sources[0x44]	354663	1		T5	10		T7	3		T10	3
valid_sources[0x45]	352523	1		T3	4		T5	58		T7	1
valid_sources[0x46]	356241	1		T3	1		T5	6		T7	3
valid_sources[0x47]	351995	1		T3	1		T5	16		T7	2
valid_sources[0x48]	356340	1		T5	29		T7	1		T14	41
valid_sources[0x49]	353069	1		T3	1		T5	4		T7	2
valid_sources[0x4a]	351436	1		T3	1		T5	14		T10	10
valid_sources[0x4b]	459394	1		T3	2		T5	10		T14	44
valid_sources[0x4c]	356655	1		T3	1		T5	26		T10	1
valid_sources[0x4d]	350811	1		T3	1		T5	48		T7	2
valid_sources[0x4e]	371138	1		T3	1		T10	1		T14	52
valid_sources[0x4f]	353832	1		T1	1		T5	4		T6	1
valid_sources[0x50]	355742	1		T1	1		T5	41		T7	3
valid_sources[0x51]	363088	1		T1	1		T3	1		T5	48
valid_sources[0x52]	360322	1		T5	10		T7	4		T10	1
valid_sources[0x53]	351543	1		T3	1		T5	40		T10	2
valid_sources[0x54]	352486	1		T5	51		T10	2		T14	37
valid_sources[0x55]	353203	1		T3	2		T5	19		T7	1
valid_sources[0x56]	601136	1		T5	40		T7	4		T14	40
valid_sources[0x57]	353366	1		T3	5		T5	33		T7	3
valid_sources[0x58]	352625	1		T3	3		T5	44		T7	2
valid_sources[0x59]	356883	1		T5	46		T7	5		T10	1
valid_sources[0x5a]	351990	1		T3	1		T5	126		T7	1
valid_sources[0x5b]	352909	1		T3	4		T5	21		T7	1
valid_sources[0x5c]	351387	1		T3	4		T5	33		T10	4
valid_sources[0x5d]	354675	1		T5	34		T7	1		T14	46
valid_sources[0x5e]	1112312	1		T3	1		T5	40		T7	4
valid_sources[0x5f]	353502	1		T3	2		T5	53		T7	1
valid_sources[0x60]	352459	1		T3	1		T5	4		T7	1
valid_sources[0x61]	620056	1		T3	4		T5	51		T14	50
valid_sources[0x62]	353940	1		T5	33		T7	1		T10	4
valid_sources[0x63]	356954	1		T3	1		T5	52		T7	2
valid_sources[0x64]	351466	1		T3	3		T5	56		T7	1
valid_sources[0x65]	354936	1		T3	1		T5	13		T7	1
valid_sources[0x66]	370803	1		T5	32		T7	2		T10	1
valid_sources[0x67]	355258	1		T3	3		T5	14		T7	1
valid_sources[0x68]	351711	1		T5	133		T7	1		T14	45
valid_sources[0x69]	1411119	1		T3	2		T5	60		T14	42
valid_sources[0x6a]	353497	1		T5	22		T7	2		T10	9
valid_sources[0x6b]	351655	1		T5	35		T7	1		T14	41
valid_sources[0x6c]	361023	1		T3	3		T5	42		T7	2
valid_sources[0x6d]	352086	1		T5	13		T7	3		T10	2
valid_sources[0x6e]	387682	1		T5	51		T10	1		T14	44
valid_sources[0x6f]	353234	1		T5	22		T7	2		T14	44
valid_sources[0x70]	350947	1		T5	39		T7	1		T14	53
valid_sources[0x71]	352999	1		T5	12		T7	1		T14	56
valid_sources[0x72]	478822	1		T3	2		T5	47		T7	1
valid_sources[0x73]	383279	1		T1	1		T3	1		T28	1
valid_sources[0x74]	354071	1		T5	37		T7	3		T14	43
valid_sources[0x75]	660006	1		T3	1		T5	128		T7	5
valid_sources[0x76]	354937	1		T7	2		T10	7		T14	43
valid_sources[0x77]	1052096	1		T3	3		T5	23		T10	4
valid_sources[0x78]	491573	1		T5	39		T7	3		T28	1
valid_sources[0x79]	1393002	1		T3	3		T5	48		T14	39
valid_sources[0x7a]	349900	1		T5	12		T7	2		T14	46
valid_sources[0x7b]	381938	1		T1	1		T5	23		T7	1
valid_sources[0x7c]	356737	1		T3	2		T5	58		T7	2
valid_sources[0x7d]	352630	1		T5	4		T7	1		T10	5
valid_sources[0x7e]	351875	1		T3	2		T5	23		T7	3
valid_sources[0x7f]	354109	1		T3	2		T5	58		T7	1
valid_sources[0x80]	383195	1		T5	23		T7	1		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59615019

1

T1

6

T2

1

T3

170

values[0x0]

all_enables

biggest_size

400926

1

T1

4

T3

9

T5

5

values[0x1]

all_enables

biggest_size

399538

1

T1

3

T3

3

T5

7