Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	69254983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

69347690

1

T1

1

T3

506

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138501516	1			T1	1		T2	1		T3	962
values[0x0]	48984	1			T3	3		T5	20		T8	11
values[0x1]	52173	1			T3	7		T5	21		T8	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55338067	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

83264606

1

T1

1

T3

599

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	614927	1			T3	3		T5	1		T8	125
valid_sources[0x01]	444838	1			T3	6		T8	102		T10	1
valid_sources[0x02]	447150	1			T3	2		T5	3		T8	87
valid_sources[0x03]	443138	1			T3	4		T5	1		T8	79
valid_sources[0x04]	439605	1			T3	4		T5	1		T8	95
valid_sources[0x05]	811977	1			T3	2		T5	2		T8	106
valid_sources[0x06]	438375	1			T3	4		T8	70		T11	52
valid_sources[0x07]	761263	1			T3	5		T5	3		T8	93
valid_sources[0x08]	439284	1			T3	1		T5	1		T8	88
valid_sources[0x09]	439841	1			T3	5		T5	1		T8	82
valid_sources[0x0a]	436465	1			T5	2		T8	100		T11	38
valid_sources[0x0b]	439988	1			T3	5		T5	1		T8	116
valid_sources[0x0c]	436803	1			T3	4		T5	3		T8	90
valid_sources[0x0d]	438181	1			T3	5		T8	109		T11	38
valid_sources[0x0e]	439665	1			T3	4		T5	1		T8	96
valid_sources[0x0f]	437351	1			T3	3		T5	1		T8	109
valid_sources[0x10]	440117	1			T5	1		T8	110		T10	7
valid_sources[0x11]	438586	1			T3	4		T5	4		T8	91
valid_sources[0x12]	437493	1			T3	4		T8	99		T11	41
valid_sources[0x13]	451552	1			T3	5		T8	84		T10	9
valid_sources[0x14]	438817	1			T3	3		T8	103		T11	32
valid_sources[0x15]	439476	1			T3	3		T8	83		T11	47
valid_sources[0x16]	437413	1			T3	3		T5	2		T8	89
valid_sources[0x17]	438153	1			T3	3		T8	95		T11	35
valid_sources[0x18]	457357	1			T3	8		T8	102		T11	39
valid_sources[0x19]	438988	1			T3	7		T5	1		T8	87
valid_sources[0x1a]	1544702	1			T3	5		T5	1		T8	103
valid_sources[0x1b]	695986	1			T3	3		T5	1		T8	94
valid_sources[0x1c]	439763	1			T3	9		T8	100		T10	12
valid_sources[0x1d]	666549	1			T3	3		T5	1		T8	85
valid_sources[0x1e]	438707	1			T3	2		T8	93		T10	16
valid_sources[0x1f]	581101	1			T3	1		T5	2		T8	124
valid_sources[0x20]	436987	1			T3	5		T5	1		T8	94
valid_sources[0x21]	438720	1			T3	5		T8	85		T11	39
valid_sources[0x22]	441217	1			T3	5		T8	74		T10	1
valid_sources[0x23]	438583	1			T3	5		T5	2		T8	106
valid_sources[0x24]	463048	1			T3	3		T8	95		T11	51
valid_sources[0x25]	439762	1			T3	4		T5	1		T8	96
valid_sources[0x26]	439008	1			T3	9		T5	1		T8	102
valid_sources[0x27]	436302	1			T3	6		T8	90		T11	42
valid_sources[0x28]	518710	1			T3	2		T8	111		T10	1
valid_sources[0x29]	437991	1			T3	7		T5	1		T8	74
valid_sources[0x2a]	457308	1			T3	6		T8	112		T11	40
valid_sources[0x2b]	440160	1			T3	2		T8	114		T11	25
valid_sources[0x2c]	846983	1			T3	6		T8	99		T11	30
valid_sources[0x2d]	438704	1			T3	12		T5	2		T8	78
valid_sources[0x2e]	439169	1			T3	5		T8	93		T11	47
valid_sources[0x2f]	659210	1			T3	3		T5	1		T8	85
valid_sources[0x30]	439959	1			T3	2		T8	61		T10	1
valid_sources[0x31]	437579	1			T3	4		T5	3		T8	86
valid_sources[0x32]	435996	1			T3	5		T8	90		T11	55
valid_sources[0x33]	437594	1			T3	3		T5	2		T8	100
valid_sources[0x34]	547457	1			T3	1		T8	90		T11	43
valid_sources[0x35]	1386241	1			T3	6		T8	92		T11	52
valid_sources[0x36]	437650	1			T3	7		T5	3		T8	85
valid_sources[0x37]	436757	1			T3	5		T5	1		T8	90
valid_sources[0x38]	541053	1			T3	5		T8	124		T11	42
valid_sources[0x39]	446388	1			T3	2		T8	118		T11	30
valid_sources[0x3a]	439865	1			T3	6		T8	118		T11	39
valid_sources[0x3b]	439990	1			T3	4		T5	1		T8	93
valid_sources[0x3c]	437858	1			T3	1		T5	1		T8	83
valid_sources[0x3d]	436791	1			T3	3		T8	112		T10	4
valid_sources[0x3e]	438990	1			T3	3		T8	68		T10	1
valid_sources[0x3f]	436573	1			T3	1		T8	97		T11	57
valid_sources[0x40]	605204	1			T3	3		T8	82		T11	38
valid_sources[0x41]	437436	1			T3	3		T8	88		T11	33
valid_sources[0x42]	437328	1			T3	4		T5	2		T8	97
valid_sources[0x43]	884156	1			T3	9		T5	1		T8	96
valid_sources[0x44]	438081	1			T5	2		T8	96		T10	3
valid_sources[0x45]	438813	1			T3	1		T5	1		T8	74
valid_sources[0x46]	439813	1			T3	5		T8	124		T10	27
valid_sources[0x47]	439197	1			T3	3		T8	105		T10	22
valid_sources[0x48]	439467	1			T3	2		T8	121		T11	26
valid_sources[0x49]	872873	1			T3	1		T8	81		T10	4
valid_sources[0x4a]	440520	1			T3	2		T8	73		T11	31
valid_sources[0x4b]	435722	1			T3	7		T5	1		T8	100
valid_sources[0x4c]	439986	1			T3	2		T8	90		T10	5
valid_sources[0x4d]	440481	1			T3	6		T5	1		T8	86
valid_sources[0x4e]	438735	1			T3	2		T5	2		T8	87
valid_sources[0x4f]	438259	1			T3	9		T5	1		T8	83
valid_sources[0x50]	437417	1			T3	3		T5	1		T8	86
valid_sources[0x51]	437637	1			T3	3		T8	102		T11	25
valid_sources[0x52]	439765	1			T3	2		T5	1		T8	82
valid_sources[0x53]	437544	1			T3	7		T8	106		T10	5
valid_sources[0x54]	503617	1			T3	3		T8	77		T10	1
valid_sources[0x55]	435713	1			T5	1		T8	105		T10	1
valid_sources[0x56]	441338	1			T3	3		T8	111		T11	20
valid_sources[0x57]	439954	1			T3	5		T8	84		T11	30
valid_sources[0x58]	437046	1			T3	4		T8	107		T11	41
valid_sources[0x59]	435976	1			T3	2		T8	92		T11	45
valid_sources[0x5a]	438549	1			T3	7		T8	103		T11	34
valid_sources[0x5b]	439907	1			T2	1		T3	2		T8	83
valid_sources[0x5c]	436460	1			T3	4		T8	122		T11	40
valid_sources[0x5d]	592267	1			T3	2		T8	94		T10	11
valid_sources[0x5e]	439891	1			T3	4		T5	1		T8	126
valid_sources[0x5f]	440529	1			T3	3		T5	1		T8	94
valid_sources[0x60]	444430	1			T3	3		T5	2		T8	111
valid_sources[0x61]	438141	1			T3	7		T5	2		T8	124
valid_sources[0x62]	438606	1			T3	4		T5	1		T8	102
valid_sources[0x63]	439194	1			T3	3		T8	103		T11	42
valid_sources[0x64]	436639	1			T3	3		T8	102		T10	12
valid_sources[0x65]	439880	1			T3	4		T8	115		T11	41
valid_sources[0x66]	440907	1			T3	2		T5	4		T8	121
valid_sources[0x67]	435016	1			T3	3		T8	106		T11	41
valid_sources[0x68]	1764584	1			T3	2		T5	3		T8	98
valid_sources[0x69]	440059	1			T3	1		T8	93		T10	8
valid_sources[0x6a]	439863	1			T3	3		T5	1		T8	92
valid_sources[0x6b]	738450	1			T3	3		T5	1		T8	97
valid_sources[0x6c]	471557	1			T3	4		T8	78		T10	1
valid_sources[0x6d]	438889	1			T3	3		T8	98		T10	13
valid_sources[0x6e]	586730	1			T3	1		T5	2		T8	82
valid_sources[0x6f]	438101	1			T3	1		T8	79		T11	27
valid_sources[0x70]	438365	1			T3	6		T5	1		T8	85
valid_sources[0x71]	440959	1			T3	5		T5	1		T8	93
valid_sources[0x72]	444054	1			T3	4		T5	1		T8	78
valid_sources[0x73]	440737	1			T3	8		T8	108		T11	42
valid_sources[0x74]	439317	1			T3	5		T5	2		T8	112
valid_sources[0x75]	1662604	1			T3	7		T5	1		T8	88
valid_sources[0x76]	435408	1			T3	3		T8	74		T10	2
valid_sources[0x77]	438249	1			T3	1		T5	1		T8	111
valid_sources[0x78]	438215	1			T3	5		T8	69		T10	7
valid_sources[0x79]	440396	1			T3	7		T8	104		T10	1
valid_sources[0x7a]	480430	1			T5	1		T8	73		T11	39
valid_sources[0x7b]	441306	1			T3	6		T5	1		T8	105
valid_sources[0x7c]	436452	1			T3	3		T8	109		T11	38
valid_sources[0x7d]	438233	1			T3	2		T8	86		T11	52
valid_sources[0x7e]	439993	1			T3	3		T5	1		T8	121
valid_sources[0x7f]	436163	1			T3	5		T8	96		T11	47
valid_sources[0x80]	439970	1			T3	3		T5	2		T8	99

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69261284

1

T1

1

T3

498

T4

1

values[0x0]

all_enables

biggest_size

43940

1

T3

1

T5

16

T8

9

values[0x1]

all_enables

biggest_size

42466

1

T3

7

T5

16

T8

15