Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

19 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rv_timer-0-prescale-0 100.00 1 100 1 64 64
rv_timer-0-prescale-1 100.00 1 100 1 64 64
rv_timer-0-prescale-10 100.00 1 100 1 64 64
rv_timer-0-prescale-11 100.00 1 100 1 64 64
rv_timer-0-prescale-2 100.00 1 100 1 64 64
rv_timer-0-prescale-3 100.00 1 100 1 64 64
rv_timer-0-prescale-4 100.00 1 100 1 64 64
rv_timer-0-prescale-5 100.00 1 100 1 64 64
rv_timer-0-prescale-6 100.00 1 100 1 64 64
rv_timer-0-prescale-7 100.00 1 100 1 64 64
rv_timer-0-prescale-8 100.00 1 100 1 64 64
rv_timer-0-prescale-9 100.00 1 100 1 64 64
rv_timer_sticky_intr_pin0 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max 100.00 1 100 1 64 64



Group Instance : rv_timer-0-prescale-0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-0
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-1
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-10
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-10

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-10
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-11
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-11

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-11
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-2
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-3
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-4
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-5
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-6
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-7
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-8
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer-0-prescale-9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer-0-prescale-9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-9
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : rv_timer_sticky_intr_pin0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance rv_timer_sticky_intr_pin0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer_sticky_intr_pin0
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 214 1 T100 1 T132 1 T133 1
rising 206 1 T16 1 T95 1 T100 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 611 1 T5 1 T14 1 T16 1
auto[1] 594 1 T15 1 T16 1 T20 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 216 1 T95 1 T133 1 T106 1
rising 222 1 T100 1 T96 1 T117 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 615 1 T5 1 T15 1 T20 2
auto[1] 590 1 T14 1 T16 2 T124 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 225 1 T149 1 T95 1 T100 1
rising 230 1 T16 1 T100 2 T106 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 608 1 T16 1 T149 1 T124 1
auto[1] 597 1 T5 1 T14 1 T15 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 239 1 T20 1 T95 1 T100 2
rising 212 1 T16 1 T95 1 T100 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 583 1 T15 1 T16 1 T20 1
auto[1] 622 1 T5 1 T14 1 T16 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 202 1 T20 1 T149 1 T100 1
rising 228 1 T95 1 T132 1 T133 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 603 1 T15 1 T20 1 T149 1
auto[1] 602 1 T5 1 T14 1 T16 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 233 1 T95 1 T100 2 T132 1
rising 231 1 T16 1 T149 1 T100 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 596 1 T5 1 T15 1 T16 1
auto[1] 609 1 T14 1 T16 1 T20 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 216 1 T100 2 T133 1 T97 1
rising 211 1 T95 1 T100 1 T133 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 560 1 T15 1 T149 2 T95 1
auto[1] 645 1 T5 1 T14 1 T16 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 206 1 T100 1 T133 1 T96 1
rising 206 1 T16 1 T95 1 T100 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 627 1 T5 1 T15 1 T16 1
auto[1] 578 1 T14 1 T16 1 T149 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 213 1 T149 1 T95 1 T132 1
rising 222 1 T95 1 T133 1 T106 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 613 1 T5 1 T15 1 T16 2
auto[1] 592 1 T14 1 T20 2 T149 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 210 1 T16 1 T95 1 T100 2
rising 215 1 T100 1 T144 1 T133 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 625 1 T14 1 T15 1 T16 1
auto[1] 580 1 T5 1 T16 1 T95 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 222 1 T20 1 T95 1 T100 1
rising 216 1 T16 1 T149 1 T95 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 582 1 T16 1 T20 1 T149 1
auto[1] 623 1 T5 1 T14 1 T15 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 233 1 T16 1 T95 1 T100 2
rising 206 1 T149 1 T95 1 T100 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 609 1 T5 1 T14 1 T15 1
auto[1] 596 1 T16 1 T20 2 T149 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 74 1 T15 1 T16 1 T143 1
rising 74 1 T15 1 T16 1 T143 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 6797 1 T1 4 T3 6 T5 5
auto[1] 113 1 T15 2 T16 1 T143 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 256061 1 T12 9113 T18 10043 T19 7261
rising 256063 1 T12 9113 T18 10044 T19 7261


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1752087 1 T12 59552 T18 68250 T19 51059
auto[1] 306220 1 T12 10930 T18 12082 T19 8679


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 492855 1 T12 16711 T18 19235 T19 14470
rising 492851 1 T12 16711 T18 19235 T19 14470


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1224146 1 T12 42369 T18 47748 T19 35211
auto[1] 834161 1 T12 28113 T18 32584 T19 24527


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 492855 1 T12 16711 T18 19235 T19 14470
rising 492851 1 T12 16711 T18 19235 T19 14470


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1224146 1 T12 42369 T18 47748 T19 35211
auto[1] 834161 1 T12 28113 T18 32584 T19 24527


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 502145 1 T12 17184 T18 19509 T19 14611
rising 502144 1 T12 17184 T18 19509 T19 14611


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1106944 1 T12 38729 T18 43329 T19 31598
auto[1] 951363 1 T12 31753 T18 37003 T19 28140


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 363855 1 T12 12377 T18 14301 T19 10485
rising 363839 1 T12 12376 T18 14300 T19 10484


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1581927 1 T12 54232 T18 61574 T19 46097
auto[1] 476380 1 T12 16250 T18 18758 T19 13641


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 371184 1 T12 12610 T18 14553 T19 10811
rising 371192 1 T12 12610 T18 14553 T19 10812


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1572292 1 T12 54084 T18 61276 T19 45626
auto[1] 486015 1 T12 16398 T18 19056 T19 14112