Line Coverage for Module :
prim_onehot_check
| Line No. | Total | Covered | Percent |
TOTAL | | 57 | 57 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 0 | 0 | |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 0 | 0 | |
CONT_ASSIGN | 95 | 0 | 0 | |
CONT_ASSIGN | 95 | 0 | 0 | |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 0 | 0 | |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 0 | 0 | |
CONT_ASSIGN | 96 | 0 | 0 | |
CONT_ASSIGN | 96 | 0 | 0 | |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 0 | 0 | |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 0 | 0 | |
CONT_ASSIGN | 98 | 0 | 0 | |
CONT_ASSIGN | 98 | 0 | 0 | |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' or '../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
86 |
10 |
10 |
87 |
10 |
10 |
95 |
11 |
11(4 unreachable) |
96 |
11 |
11(4 unreachable) |
98 |
11 |
11(4 unreachable) |
108 |
1 |
1 |
111 |
1 |
1 |
121 |
1 |
1 |
136 |
1 |
1 |
Cond Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Conditions | 165 | 163 | 98.79 |
Logical | 165 | 163 | 98.79 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 95
EXPRESSION (or_tree[gen_tree[0].gen_level[0].C0] || or_tree[gen_tree[0].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[1].gen_level[0].C0] || or_tree[gen_tree[1].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[1].gen_level[1].C0] || or_tree[gen_tree[1].gen_level[1].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[2].gen_level[0].C0] || or_tree[gen_tree[2].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[2].gen_level[1].C0] || or_tree[gen_tree[2].gen_level[1].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[2].gen_level[2].C0] || or_tree[gen_tree[2].gen_level[2].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[2].gen_level[3].C0] || or_tree[gen_tree[2].gen_level[3].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[0].C0] || or_tree[gen_tree[3].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T5,T6 |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[1].C0] || or_tree[gen_tree[3].gen_level[1].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[2].C0] || or_tree[gen_tree[3].gen_level[2].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[3].C0] || or_tree[gen_tree[3].gen_level[3].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[4].C0] || or_tree[gen_tree[3].gen_level[4].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[5].C0] || or_tree[gen_tree[3].gen_level[5].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[6].C0] || or_tree[gen_tree[3].gen_level[6].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 95
EXPRESSION (or_tree[gen_tree[3].gen_level[7].C0] || or_tree[gen_tree[3].gen_level[7].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 0)])) && and_tree[gen_tree[0].gen_level[0].C0]) ||
2 (addr_i[((AddrWidth - 1) - 0)] && and_tree[gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T10 |
1 | 0 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 0)])) && and_tree[gen_tree[0].gen_level[0].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 0)] && and_tree[gen_tree[0].gen_level[0].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T10 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[0].C0]) ||
2 (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T10 |
1 | 0 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[0].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[0].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T10 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[1].C0]) ||
2 (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[1].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[1].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[0].C0]) ||
2 (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[0].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[0].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T11 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[1].C0]) ||
2 (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[1].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[1].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T11 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[2].C0]) ||
2 (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[2].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[2].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[2].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[3].C0]) ||
2 (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[3].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[3].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[3].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[0].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[0].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[0].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T11 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[1].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[1].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[1].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T11 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[2].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[2].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[2].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[2].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T11 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[3].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[3].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[3].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T11,T10 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[3].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T11 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[4].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[4].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[4].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T4,T5,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[4].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T8,T9 |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | T4,T5,T11 |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[5].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[5].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[5].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[5].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[6].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[6].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[6].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[6].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | |
LINE 96
EXPRESSION
Number Term
1 (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[7].C0]) ||
2 (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[7].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 96
SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[7].C0])
-----------------1---------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 96
SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[7].C1])
--------------1-------------- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | T4,T5,T11 |
1 | 1 | Unreachable | |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[0].gen_level[0].C0] && or_tree[gen_tree[0].gen_level[0].C1]) ||
2 err_tree[gen_tree[0].gen_level[0].C0] ||
3 err_tree[gen_tree[0].gen_level[0].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T4,T5,T11 |
1 | 0 | 0 | Covered | T4 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[0].gen_level[0].C0] && or_tree[gen_tree[0].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[1].gen_level[0].C0] && or_tree[gen_tree[1].gen_level[0].C1]) ||
2 err_tree[gen_tree[1].gen_level[0].C0] ||
3 err_tree[gen_tree[1].gen_level[0].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T10 |
0 | 1 | 0 | Covered | T5,T10,T12 |
1 | 0 | 0 | Covered | T4,T5,T10 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[1].gen_level[0].C0] && or_tree[gen_tree[1].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[1].gen_level[1].C0] && or_tree[gen_tree[1].gen_level[1].C1]) ||
2 err_tree[gen_tree[1].gen_level[1].C0] ||
3 err_tree[gen_tree[1].gen_level[1].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Covered | T4,T5,T11 |
1 | 0 | 0 | Unreachable | |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[1].gen_level[1].C0] && or_tree[gen_tree[1].gen_level[1].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[2].gen_level[0].C0] && or_tree[gen_tree[2].gen_level[0].C1]) ||
2 err_tree[gen_tree[2].gen_level[0].C0] ||
3 err_tree[gen_tree[2].gen_level[0].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T5,T10 |
0 | 1 | 0 | Covered | T4,T10,T12 |
1 | 0 | 0 | Covered | T4,T5,T11 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[0].C0] && or_tree[gen_tree[2].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[2].gen_level[1].C0] && or_tree[gen_tree[2].gen_level[1].C1]) ||
2 err_tree[gen_tree[2].gen_level[1].C0] ||
3 err_tree[gen_tree[2].gen_level[1].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T4,T11 |
0 | 1 | 0 | Not Covered | |
1 | 0 | 0 | Covered | T4,T5,T10 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[1].C0] && or_tree[gen_tree[2].gen_level[1].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[2].gen_level[2].C0] && or_tree[gen_tree[2].gen_level[2].C1]) ||
2 err_tree[gen_tree[2].gen_level[2].C0] ||
3 err_tree[gen_tree[2].gen_level[2].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Covered | T4,T5,T11 |
1 | 0 | 0 | Unreachable | |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[2].C0] && or_tree[gen_tree[2].gen_level[2].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[2].gen_level[3].C0] && or_tree[gen_tree[2].gen_level[3].C1]) ||
2 err_tree[gen_tree[2].gen_level[3].C0] ||
3 err_tree[gen_tree[2].gen_level[3].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Unreachable | |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[3].C0] && or_tree[gen_tree[2].gen_level[3].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[0].C0] && or_tree[gen_tree[3].gen_level[0].C1]) ||
2 err_tree[gen_tree[3].gen_level[0].C0] ||
3 err_tree[gen_tree[3].gen_level[0].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Covered | T4,T5,T11 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[0].C0] && or_tree[gen_tree[3].gen_level[0].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[1].C0] && or_tree[gen_tree[3].gen_level[1].C1]) ||
2 err_tree[gen_tree[3].gen_level[1].C0] ||
3 err_tree[gen_tree[3].gen_level[1].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Covered | T4,T5,T11 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[1].C0] && or_tree[gen_tree[3].gen_level[1].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[2].C0] && or_tree[gen_tree[3].gen_level[2].C1]) ||
2 err_tree[gen_tree[3].gen_level[2].C0] ||
3 err_tree[gen_tree[3].gen_level[2].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Covered | T4,T5,T11 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[2].C0] && or_tree[gen_tree[3].gen_level[2].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[3].C0] && or_tree[gen_tree[3].gen_level[3].C1]) ||
2 err_tree[gen_tree[3].gen_level[3].C0] ||
3 err_tree[gen_tree[3].gen_level[3].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Covered | T4,T11,T10 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[3].C0] && or_tree[gen_tree[3].gen_level[3].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T11,T10 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[4].C0] && or_tree[gen_tree[3].gen_level[4].C1]) ||
2 err_tree[gen_tree[3].gen_level[4].C0] ||
3 err_tree[gen_tree[3].gen_level[4].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Covered | T4,T5,T11 |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[4].C0] && or_tree[gen_tree[3].gen_level[4].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[5].C0] && or_tree[gen_tree[3].gen_level[5].C1]) ||
2 err_tree[gen_tree[3].gen_level[5].C0] ||
3 err_tree[gen_tree[3].gen_level[5].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Unreachable | |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[5].C0] && or_tree[gen_tree[3].gen_level[5].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[6].C0] && or_tree[gen_tree[3].gen_level[6].C1]) ||
2 err_tree[gen_tree[3].gen_level[6].C0] ||
3 err_tree[gen_tree[3].gen_level[6].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Unreachable | |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[6].C0] && or_tree[gen_tree[3].gen_level[6].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 98
EXPRESSION
Number Term
1 (or_tree[gen_tree[3].gen_level[7].C0] && or_tree[gen_tree[3].gen_level[7].C1]) ||
2 err_tree[gen_tree[3].gen_level[7].C0] ||
3 err_tree[gen_tree[3].gen_level[7].C1])
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Unreachable | |
LINE 98
SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[7].C0] && or_tree[gen_tree[3].gen_level[7].C1])
------------------1----------------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 108
EXPRESSION (oh0_err || enable_err || addr_err)
---1--- -----2---- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Unreachable | |
0 | 1 | 0 | Covered | T4,T5,T11 |
1 | 0 | 0 | Covered | T4,T5,T11 |
LINE 121
EXPRESSION (((!en_i)) && or_tree[0])
----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T11 |
Assert Coverage for Module :
prim_onehot_check
Assertion Details
AddrImpliesEnable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620 |
620 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
AddrRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620 |
620 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
AddrWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620 |
620 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
NumSources_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620 |
620 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
Onehot0Check_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
54 |
0 |
0 |
T4 |
7126 |
14 |
0 |
0 |
T5 |
7574 |
10 |
0 |
0 |
T10 |
7792 |
15 |
0 |
0 |
T11 |
3280 |
4 |
0 |
0 |
T12 |
8695 |
11 |
0 |
0 |
gen_enable_check.gen_not_strict.EnableCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
96 |
0 |
0 |
T4 |
7126 |
23 |
0 |
0 |
T5 |
7574 |
18 |
0 |
0 |
T10 |
7792 |
20 |
0 |
0 |
T11 |
3280 |
8 |
0 |
0 |
T12 |
8695 |
27 |
0 |
0 |
gen_generic.AssertConnected_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620 |
620 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |