Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.60 100.00 98.79 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check 99.60 100.00 98.79 100.00



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.60 100.00 98.79 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.60 100.00 98.79 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_onehot_check
Line No.TotalCoveredPercent
TOTAL5757100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9500
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9500
CONT_ASSIGN9500
CONT_ASSIGN9500
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9600
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9600
CONT_ASSIGN9600
CONT_ASSIGN9600
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9800
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9800
CONT_ASSIGN9800
CONT_ASSIGN9800
CONT_ASSIGN10811100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN13611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' or '../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
86 10 10
87 10 10
95 11 11(4 unreachable)
96 11 11(4 unreachable)
98 11 11(4 unreachable)
108 1 1
111 1 1
121 1 1
136 1 1


Cond Coverage for Module : prim_onehot_check
TotalCoveredPercent
Conditions16516398.79
Logical16516398.79
Non-Logical00
Event00

 LINE       95
 EXPRESSION (or_tree[gen_tree[0].gen_level[0].C0] || or_tree[gen_tree[0].gen_level[0].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[1].gen_level[0].C0] || or_tree[gen_tree[1].gen_level[0].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[1].gen_level[1].C0] || or_tree[gen_tree[1].gen_level[1].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[2].gen_level[0].C0] || or_tree[gen_tree[2].gen_level[0].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[2].gen_level[1].C0] || or_tree[gen_tree[2].gen_level[1].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[2].gen_level[2].C0] || or_tree[gen_tree[2].gen_level[2].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[2].gen_level[3].C0] || or_tree[gen_tree[2].gen_level[3].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[0].C0] || or_tree[gen_tree[3].gen_level[0].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T5,T6

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[1].C0] || or_tree[gen_tree[3].gen_level[1].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[2].C0] || or_tree[gen_tree[3].gen_level[2].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[3].C0] || or_tree[gen_tree[3].gen_level[3].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[4].C0] || or_tree[gen_tree[3].gen_level[4].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T8,T9
10CoveredT1,T2,T3

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[5].C0] || or_tree[gen_tree[3].gen_level[5].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[6].C0] || or_tree[gen_tree[3].gen_level[6].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       95
 EXPRESSION (or_tree[gen_tree[3].gen_level[7].C0] || or_tree[gen_tree[3].gen_level[7].C1])
             ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 0)])) && and_tree[gen_tree[0].gen_level[0].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 0)] && and_tree[gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T10
10CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 0)])) && and_tree[gen_tree[0].gen_level[0].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 0)] && and_tree[gen_tree[0].gen_level[0].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT4,T5,T11
11UnreachableT4,T5,T10

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[0].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T10
10CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[0].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[0].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT4,T5,T11
11UnreachableT4,T5,T10

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[1].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 1)])) && and_tree[gen_tree[1].gen_level[1].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 1)] && and_tree[gen_tree[1].gen_level[1].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10UnreachableT4,T5,T11
11Unreachable

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[0].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T11
10CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[0].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[0].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT4,T5,T11
11UnreachableT4,T5,T11

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[1].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T11
10CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[1].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[1].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT4,T5,T11
11UnreachableT4,T5,T11

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[2].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[2].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[2].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[2].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10UnreachableT4,T5,T11
11Unreachable

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[3].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[3].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 2)])) && and_tree[gen_tree[2].gen_level[3].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 2)] && and_tree[gen_tree[2].gen_level[3].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10UnreachableT4,T5,T11
11Unreachable

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[0].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T11
10CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[0].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[0].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT4,T5,T11
11UnreachableT4,T5,T11

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[1].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T11
10CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[1].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[1].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT4,T5,T11
11UnreachableT4,T5,T11

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[2].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[2].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T11
10CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[2].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[2].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT4,T5,T11
11UnreachableT4,T5,T11

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[3].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[3].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T11
10CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[3].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T11,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[3].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT1,T3,T7
10UnreachableT4,T5,T11
11UnreachableT4,T5,T11

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[4].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[4].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT4,T5,T11
10CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[4].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01UnreachableT4,T5,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[4].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01CoveredT3,T8,T9
10UnreachableT4,T5,T11
11UnreachableT4,T5,T11

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[5].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[5].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[5].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[5].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10UnreachableT4,T5,T11
11Unreachable

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[6].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[6].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[6].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[6].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10UnreachableT4,T5,T11
11Unreachable

 LINE       96
 EXPRESSION 
 Number  Term
      1  (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[7].C0]) || 
      2  (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[7].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       96
 SUB-EXPRESSION (((!addr_i[((AddrWidth - 1) - 3)])) && and_tree[gen_tree[3].gen_level[7].C0])
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       96
 SUB-EXPRESSION (addr_i[((AddrWidth - 1) - 3)] && and_tree[gen_tree[3].gen_level[7].C1])
                 --------------1--------------    ------------------2------------------
-1--2-StatusTests
01Unreachable
10UnreachableT4,T5,T11
11Unreachable

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[0].gen_level[0].C0] && or_tree[gen_tree[0].gen_level[0].C1]) || 
      2  err_tree[gen_tree[0].gen_level[0].C0] || 
      3  err_tree[gen_tree[0].gen_level[0].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT4,T5,T11
100CoveredT4

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[0].gen_level[0].C0] && or_tree[gen_tree[0].gen_level[0].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[1].gen_level[0].C0] && or_tree[gen_tree[1].gen_level[0].C1]) || 
      2  err_tree[gen_tree[1].gen_level[0].C0] || 
      3  err_tree[gen_tree[1].gen_level[0].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10
010CoveredT5,T10,T12
100CoveredT4,T5,T10

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[1].gen_level[0].C0] && or_tree[gen_tree[1].gen_level[0].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[1].gen_level[1].C0] && or_tree[gen_tree[1].gen_level[1].C1]) || 
      2  err_tree[gen_tree[1].gen_level[1].C0] || 
      3  err_tree[gen_tree[1].gen_level[1].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010CoveredT4,T5,T11
100Unreachable

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[1].gen_level[1].C0] && or_tree[gen_tree[1].gen_level[1].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[2].gen_level[0].C0] && or_tree[gen_tree[2].gen_level[0].C1]) || 
      2  err_tree[gen_tree[2].gen_level[0].C0] || 
      3  err_tree[gen_tree[2].gen_level[0].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T10
010CoveredT4,T10,T12
100CoveredT4,T5,T11

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[0].C0] && or_tree[gen_tree[2].gen_level[0].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[2].gen_level[1].C0] && or_tree[gen_tree[2].gen_level[1].C1]) || 
      2  err_tree[gen_tree[2].gen_level[1].C0] || 
      3  err_tree[gen_tree[2].gen_level[1].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT4,T11
010Not Covered
100CoveredT4,T5,T10

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[1].C0] && or_tree[gen_tree[2].gen_level[1].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[2].gen_level[2].C0] && or_tree[gen_tree[2].gen_level[2].C1]) || 
      2  err_tree[gen_tree[2].gen_level[2].C0] || 
      3  err_tree[gen_tree[2].gen_level[2].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010CoveredT4,T5,T11
100Unreachable

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[2].C0] && or_tree[gen_tree[2].gen_level[2].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[2].gen_level[3].C0] && or_tree[gen_tree[2].gen_level[3].C1]) || 
      2  err_tree[gen_tree[2].gen_level[3].C0] || 
      3  err_tree[gen_tree[2].gen_level[3].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100Unreachable

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[2].gen_level[3].C0] && or_tree[gen_tree[2].gen_level[3].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[0].C0] && or_tree[gen_tree[3].gen_level[0].C1]) || 
      2  err_tree[gen_tree[3].gen_level[0].C0] || 
      3  err_tree[gen_tree[3].gen_level[0].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100CoveredT4,T5,T11

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[0].C0] && or_tree[gen_tree[3].gen_level[0].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[1].C0] && or_tree[gen_tree[3].gen_level[1].C1]) || 
      2  err_tree[gen_tree[3].gen_level[1].C0] || 
      3  err_tree[gen_tree[3].gen_level[1].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100CoveredT4,T5,T11

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[1].C0] && or_tree[gen_tree[3].gen_level[1].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[2].C0] && or_tree[gen_tree[3].gen_level[2].C1]) || 
      2  err_tree[gen_tree[3].gen_level[2].C0] || 
      3  err_tree[gen_tree[3].gen_level[2].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100CoveredT4,T5,T11

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[2].C0] && or_tree[gen_tree[3].gen_level[2].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[3].C0] && or_tree[gen_tree[3].gen_level[3].C1]) || 
      2  err_tree[gen_tree[3].gen_level[3].C0] || 
      3  err_tree[gen_tree[3].gen_level[3].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100CoveredT4,T11,T10

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[3].C0] && or_tree[gen_tree[3].gen_level[3].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T3,T7
10CoveredT1,T2,T3
11CoveredT4,T11,T10

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[4].C0] && or_tree[gen_tree[3].gen_level[4].C1]) || 
      2  err_tree[gen_tree[3].gen_level[4].C0] || 
      3  err_tree[gen_tree[3].gen_level[4].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100CoveredT4,T5,T11

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[4].C0] && or_tree[gen_tree[3].gen_level[4].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT3,T8,T9
10CoveredT1,T2,T3
11CoveredT4,T5,T11

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[5].C0] && or_tree[gen_tree[3].gen_level[5].C1]) || 
      2  err_tree[gen_tree[3].gen_level[5].C0] || 
      3  err_tree[gen_tree[3].gen_level[5].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100Unreachable

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[5].C0] && or_tree[gen_tree[3].gen_level[5].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[6].C0] && or_tree[gen_tree[3].gen_level[6].C1]) || 
      2  err_tree[gen_tree[3].gen_level[6].C0] || 
      3  err_tree[gen_tree[3].gen_level[6].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100Unreachable

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[6].C0] && or_tree[gen_tree[3].gen_level[6].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       98
 EXPRESSION 
 Number  Term
      1  (or_tree[gen_tree[3].gen_level[7].C0] && or_tree[gen_tree[3].gen_level[7].C1]) || 
      2  err_tree[gen_tree[3].gen_level[7].C0] || 
      3  err_tree[gen_tree[3].gen_level[7].C1])
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010Unreachable
100Unreachable

 LINE       98
 SUB-EXPRESSION (or_tree[gen_tree[3].gen_level[7].C0] && or_tree[gen_tree[3].gen_level[7].C1])
                 ------------------1-----------------    ------------------2-----------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       108
 EXPRESSION (oh0_err || enable_err || addr_err)
             ---1---    -----2----    ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010CoveredT4,T5,T11
100CoveredT4,T5,T11

 LINE       121
 EXPRESSION (((!en_i)) && or_tree[0])
             ----1----    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T11

Assert Coverage for Module : prim_onehot_check
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrImpliesEnable_A 620 620 0 0
AddrRange_A 620 620 0 0
AddrWidth_A 620 620 0 0
NumSources_A 620 620 0 0
Onehot0Check_A 2147483647 54 0 0
gen_enable_check.gen_not_strict.EnableCheck_A 2147483647 96 0 0
gen_generic.AssertConnected_A 620 620 0 0


AddrImpliesEnable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

AddrRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

AddrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

NumSources_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

Onehot0Check_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 54 0 0
T4 7126 14 0 0
T5 7574 10 0 0
T10 7792 15 0 0
T11 3280 4 0 0
T12 8695 11 0 0

gen_enable_check.gen_not_strict.EnableCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 96 0 0
T4 7126 23 0 0
T5 7574 18 0 0
T10 7792 20 0 0
T11 3280 8 0 0
T12 8695 27 0 0

gen_generic.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 620 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%