Unified Coverage Report :: Module :: tlul_adapter_reg

Module : tlul_adapter_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_reg_if	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_reg_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_reg

	Line No.	Total	Covered	Percent
TOTAL		35	35	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	72	6	6	100.00
ALWAYS	78	8	8	100.00
ALWAYS	91	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
ALWAYS	143	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
55	1	1
57	1	1
58	1	1
60	1	1
61	1	1
62	1	1
63	1	1
68	1	1
72	2	2
73	2	2
74	2	2
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
			MISSING_ELSE
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
			MISSING_ELSE
113	1	1
133	1	1
136	1	1
143	1	1
145	1	1
148	1	1

---

Cond Coverage for Module : tlul_adapter_reg

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       86
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 SUB-EXPRESSION (error_i || err_internal || wr_req)
                 ---1---    ------2-----    ---3--

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T8,T9,T21
1	0	0	Covered	T8,T9,T21

---

Branch Coverage for Module : tlul_adapter_reg

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
IF	72	4	4	100.00
IF	78	4	4	100.00
IF	91	4	4	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	if ((!rst_ni))
-2-:	73	if (a_ack)
-3-:	74	if (d_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	78	if ((!rst_ni))
-2-:	82	if (a_ack)
-3-:	86	(rd_req) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	if ((!rst_ni))
-2-:	94	if (a_ack)
-3-:	95	(((error_i || err_internal) || wr_req)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if (wr_req)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MatchedWidthAssert	620	620	0	0

MatchedWidthAssert

Name	Attempts	Real Successes	Failures	Incomplete
Total	620	620	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0