Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8274350	0	0
cfg0_rd_A	2147483647	16666	0	0
compare_lower0_0_rd_A	2147483647	18558	0	0
compare_upper0_0_rd_A	2147483647	16457	0	0
ctrl_rd_A	2147483647	16831	0	0
intr_enable0_rd_A	2147483647	21193	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8274350	0	0
T1	200877	82474	0	0
T2	365056	0	0	0
T3	318723	0	0	0
T4	939643	0	0	0
T5	395578	102743	0	0
T6	328514	0	0	0
T7	649695	0	0	0
T8	433191	109964	0	0
T9	849181	0	0	0
T10	128846	0	0	0
T12	0	83	0	0
T13	0	20	0	0
T30	0	140607	0	0
T31	0	203158	0	0
T32	0	158030	0	0
T33	0	144349	0	0
T34	0	528	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16666	0	0
T5	395578	557	0	0
T6	328514	0	0	0
T7	649695	0	0	0
T8	433191	911	0	0
T9	849181	0	0	0
T10	128846	0	0	0
T12	0	15	0	0
T30	338800	0	0	0
T31	717196	0	0	0
T35	0	15	0	0
T36	0	10	0	0
T37	0	4	0	0
T38	0	58	0	0
T39	0	6	0	0
T40	0	16	0	0
T41	0	64	0	0
T42	146328	0	0	0
T43	674308	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18558	0	0
T5	395578	602	0	0
T6	328514	0	0	0
T7	649695	0	0	0
T8	433191	1256	0	0
T9	849181	0	0	0
T10	128846	0	0	0
T12	0	1	0	0
T30	338800	0	0	0
T31	717196	0	0	0
T35	0	10	0	0
T36	0	8	0	0
T37	0	2	0	0
T38	0	41	0	0
T39	0	6	0	0
T40	0	15	0	0
T41	0	39	0	0
T42	146328	0	0	0
T43	674308	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16457	0	0
T5	395578	484	0	0
T6	328514	0	0	0
T7	649695	0	0	0
T8	433191	1121	0	0
T9	849181	0	0	0
T10	128846	0	0	0
T12	0	9	0	0
T30	338800	0	0	0
T31	717196	0	0	0
T35	0	6	0	0
T36	0	30	0	0
T38	0	49	0	0
T39	0	16	0	0
T40	0	10	0	0
T41	0	44	0	0
T42	146328	0	0	0
T43	674308	0	0	0
T44	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16831	0	0
T5	395578	484	0	0
T6	328514	0	0	0
T7	649695	0	0	0
T8	433191	1105	0	0
T9	849181	0	0	0
T10	128846	0	0	0
T12	0	16	0	0
T30	338800	0	0	0
T31	717196	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	5	0	0
T38	0	39	0	0
T40	0	12	0	0
T41	0	36	0	0
T42	146328	0	0	0
T43	674308	0	0	0
T45	0	30	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21193	0	0
T5	395578	577	0	0
T6	328514	0	0	0
T7	649695	0	0	0
T8	433191	1545	0	0
T9	849181	0	0	0
T10	128846	0	0	0
T12	0	18	0	0
T30	338800	0	0	0
T31	717196	0	0	0
T35	0	34	0	0
T36	0	12	0	0
T37	0	1	0	0
T38	0	37	0	0
T42	146328	0	0	0
T43	674308	0	0	0
T46	0	50	0	0
T47	0	22	0	0
T48	0	29	0	0