Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8739807	0	0
cfg0_rd_A	2147483647	18256	0	0
compare_lower0_0_rd_A	2147483647	20394	0	0
compare_upper0_0_rd_A	2147483647	17814	0	0
ctrl_rd_A	2147483647	17678	0	0
intr_enable0_rd_A	2147483647	22811	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8739807	0	0
T11	316191	131377	0	0
T12	673141	207770	0	0
T13	779137	201326	0	0
T14	0	11	0	0
T15	0	10	0	0
T16	0	96	0	0
T33	0	119	0	0
T35	0	194	0	0
T36	0	502	0	0
T37	0	877	0	0
T38	314976	0	0	0
T39	924395	0	0	0
T40	782895	0	0	0
T41	207346	0	0	0
T42	118976	0	0	0
T43	167964	0	0	0
T44	601739	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18256	0	0
T13	779137	843	0	0
T16	0	17	0	0
T43	167964	0	0	0
T44	601739	0	0	0
T45	0	63	0	0
T46	0	1	0	0
T47	0	8	0	0
T48	0	8	0	0
T49	0	53	0	0
T50	0	45	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	368524	0	0	0
T54	8726	0	0	0
T55	792072	0	0	0
T56	134663	0	0	0
T57	238569	0	0	0
T58	438875	0	0	0
T59	136217	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20394	0	0
T13	779137	1087	0	0
T16	0	7	0	0
T43	167964	0	0	0
T44	601739	0	0	0
T45	0	110	0	0
T47	0	8	0	0
T48	0	4	0	0
T49	0	21	0	0
T50	0	33	0	0
T51	0	8	0	0
T52	0	4	0	0
T53	368524	0	0	0
T54	8726	0	0	0
T55	792072	0	0	0
T56	134663	0	0	0
T57	238569	0	0	0
T58	438875	0	0	0
T59	136217	0	0	0
T60	0	8	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17814	0	0
T13	779137	999	0	0
T16	0	8	0	0
T36	0	6	0	0
T43	167964	0	0	0
T44	601739	0	0	0
T45	0	78	0	0
T46	0	12	0	0
T47	0	7	0	0
T48	0	11	0	0
T49	0	78	0	0
T50	0	32	0	0
T51	0	10	0	0
T53	368524	0	0	0
T54	8726	0	0	0
T55	792072	0	0	0
T56	134663	0	0	0
T57	238569	0	0	0
T58	438875	0	0	0
T59	136217	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17678	0	0
T13	779137	1031	0	0
T16	0	5	0	0
T36	0	9	0	0
T43	167964	0	0	0
T44	601739	0	0	0
T45	0	67	0	0
T46	0	22	0	0
T47	0	7	0	0
T48	0	9	0	0
T49	0	48	0	0
T50	0	31	0	0
T51	0	17	0	0
T53	368524	0	0	0
T54	8726	0	0	0
T55	792072	0	0	0
T56	134663	0	0	0
T57	238569	0	0	0
T58	438875	0	0	0
T59	136217	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22811	0	0
T6	790061	63	0	0
T7	122342	0	0	0
T8	746452	0	0	0
T9	499181	0	0	0
T10	618139	0	0	0
T13	0	1273	0	0
T16	0	5	0	0
T34	567478	0	0	0
T36	0	3	0	0
T44	0	19	0	0
T61	0	25	0	0
T62	0	16	0	0
T63	0	22	0	0
T64	0	30	0	0
T65	0	9	0	0
T66	859999	0	0	0
T67	352748	0	0	0
T68	180667	0	0	0
T69	413466	0	0	0