Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3222388	0	0
cfg0_rd_A	2147483647	1777	0	0
compare_lower0_0_rd_A	2147483647	1678	0	0
compare_upper0_0_rd_A	2147483647	1702	0	0
ctrl_rd_A	2147483647	1586	0	0
intr_enable0_rd_A	2147483647	2111	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3222388	0	0
T11	319303	96124	0	0
T12	621336	0	0	0
T13	125038	0	0	0
T14	832147	345929	0	0
T15	0	92175	0	0
T36	0	193399	0	0
T37	0	105402	0	0
T38	0	93028	0	0
T39	0	165587	0	0
T40	0	121822	0	0
T41	0	85796	0	0
T42	0	292283	0	0
T43	130522	0	0	0
T44	602683	0	0	0
T45	668664	0	0	0
T46	129916	0	0	0
T47	738658	0	0	0
T48	113245	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1777	0	0
T32	12025	185	0	0
T35	1578	9	0	0
T49	4787	6	0	0
T50	3303	61	0	0
T51	4638	56	0	0
T52	1708	18	0	0
T53	7295	83	0	0
T54	1990	5	0	0
T55	1954	13	0	0
T56	3400	56	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1678	0	0
T32	12025	130	0	0
T34	1447	1	0	0
T35	1578	12	0	0
T50	3303	85	0	0
T51	4638	45	0	0
T52	1708	14	0	0
T53	7295	49	0	0
T54	1990	6	0	0
T57	1180	10	0	0
T58	16247	27	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1702	0	0
T32	12025	148	0	0
T35	1578	13	0	0
T49	4787	9	0	0
T50	3303	67	0	0
T51	4638	30	0	0
T52	1708	7	0	0
T53	7295	53	0	0
T54	1990	7	0	0
T55	1954	5	0	0
T58	16247	14	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1586	0	0
T32	12025	118	0	0
T34	1447	7	0	0
T35	1578	1	0	0
T50	3303	67	0	0
T51	4638	45	0	0
T52	1708	11	0	0
T53	7295	39	0	0
T54	1990	1	0	0
T57	1180	6	0	0
T58	16247	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2111	0	0
T34	0	5	0	0
T59	630360	5	0	0
T60	0	26	0	0
T61	0	9	0	0
T62	0	22	0	0
T63	0	6	0	0
T64	0	28	0	0
T65	0	77	0	0
T66	0	57	0	0
T67	0	19	0	0
T68	102420	0	0	0
T69	103416	0	0	0
T70	147030	0	0	0
T71	342427	0	0	0
T72	246171	0	0	0
T73	139925	0	0	0
T74	438472	0	0	0
T75	278157	0	0	0
T76	866380	0	0	0