Module Definition
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Module : rv_timer_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.77 100.00 99.09 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_cfg0_prescale 100.00 100.00 100.00 100.00
u_cfg0_step 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00
u_compare_lower0_0 100.00 100.00 100.00 100.00
u_compare_lower0_00_qe 100.00 100.00 100.00
u_compare_upper0_0 100.00 100.00 100.00 100.00
u_compare_upper0_00_qe 100.00 100.00 100.00
u_ctrl 100.00 100.00 100.00 100.00
u_intr_enable0 100.00 100.00 100.00 100.00
u_intr_state0 100.00 100.00 100.00 100.00
u_intr_test0 100.00 100.00
u_prim_reg_we_check 99.60 100.00 98.79 100.00
u_reg_if 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_timer_v_lower0 100.00 100.00 100.00 100.00
u_timer_v_upper0 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_timer_reg_top
Line No.TotalCoveredPercent
TOTAL7373100.00
ALWAYS7144100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN46411100.00
ALWAYS4701111100.00
CONT_ASSIGN48311100.00
ALWAYS48711100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50911100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51211100.00
CONT_ASSIGN51411100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN51711100.00
CONT_ASSIGN51811100.00
CONT_ASSIGN52011100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52411100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53211100.00
ALWAYS5361111100.00
ALWAYS5511313100.00
CONT_ASSIGN60500
CONT_ASSIGN61311100.00
CONT_ASSIGN61411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
71 1 1
72 1 1
73 1 1
74 1 1
MISSING_ELSE
80 1 1
118 1 1
119 1 1
159 1 1
173 1 1
348 1 1
387 1 1
450 1 1
464 1 1
470 1 1
471 1 1
472 1 1
473 1 1
474 1 1
475 1 1
476 1 1
477 1 1
478 1 1
479 1 1
480 1 1
483 1 1
487 1 1
501 1 1
503 1 1
504 1 1
506 1 1
507 1 1
509 1 1
511 1 1
512 1 1
514 1 1
515 1 1
517 1 1
518 1 1
520 1 1
521 1 1
523 1 1
524 1 1
526 1 1
527 1 1
529 1 1
530 1 1
532 1 1
536 1 1
537 1 1
538 1 1
539 1 1
540 1 1
541 1 1
542 1 1
543 1 1
544 1 1
545 1 1
546 1 1
551 1 1
552 1 1
554 1 1
558 1 1
562 1 1
563 1 1
567 1 1
571 1 1
575 1 1
579 1 1
583 1 1
587 1 1
591 1 1
605 unreachable
613 1 1
614 1 1


Cond Coverage for Module : rv_timer_reg_top
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T11
10CoveredT18,T19,T20

 LINE       483
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       483
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

Branch Coverage for Module : rv_timer_reg_top
Line No.TotalCoveredPercent
Branches 16 16 100.00
TERNARY 483 2 2 100.00
IF 71 3 3 100.00
CASE 552 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 483 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 71 if ((!rst_ni)) -2-: 73 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T5,T18
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 552 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : rv_timer_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 2147483647 129820778 0 0
reAfterRv 2147483647 129820761 0 0
rePulse 2147483647 129452336 0 0
wePulse 2147483647 368425 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 129820778 0 0
T1 477985 6950 0 0
T2 354148 18412 0 0
T3 666162 52881 0 0
T7 147294 17136 0 0
T8 757495 84576 0 0
T13 780230 245846 0 0
T14 186487 1445 0 0
T15 104656 63992 0 0
T16 368577 122658 0 0
T17 109089 370203 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 129820761 0 0
T1 477985 6950 0 0
T2 354148 18412 0 0
T3 666162 52881 0 0
T7 147294 17136 0 0
T8 757495 84576 0 0
T13 780230 245846 0 0
T14 186487 1445 0 0
T15 104656 63992 0 0
T16 368577 122658 0 0
T17 109089 370203 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 129452336 0 0
T1 477985 6931 0 0
T2 354148 18403 0 0
T3 666162 52610 0 0
T7 147294 17110 0 0
T8 757495 74328 0 0
T13 780230 245737 0 0
T14 186487 1431 0 0
T15 104656 63943 0 0
T16 368577 122639 0 0
T17 109089 370164 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 368425 0 0
T1 477985 19 0 0
T2 354148 9 0 0
T3 666162 271 0 0
T7 147294 26 0 0
T8 757495 10248 0 0
T13 780230 109 0 0
T14 186487 14 0 0
T15 104656 49 0 0
T16 368577 19 0 0
T17 109089 39 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%