Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	226307	0	0
cfg0_rd_A	2147483647	2446	0	0
compare_lower0_0_rd_A	2147483647	2214	0	0
compare_upper0_0_rd_A	2147483647	2199	0	0
ctrl_rd_A	2147483647	2102	0	0
intr_enable0_rd_A	2147483647	3183	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	226307	0	0
T9	364132	9424	0	0
T10	25444	0	0	0
T11	261360	7123	0	0
T12	256405	9722	0	0
T13	266039	0	0	0
T14	113230	0	0	0
T15	326231	0	0	0
T21	2691	0	0	0
T22	513275	0	0	0
T23	0	6201	0	0
T24	0	5171	0	0
T25	0	11858	0	0
T26	0	7812	0	0
T27	0	4063	0	0
T28	0	6551	0	0
T29	0	5837	0	0
T30	3156	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2446	0	0
T9	364132	106	0	0
T10	25444	0	0	0
T11	261360	114	0	0
T12	256405	0	0	0
T13	266039	0	0	0
T14	113230	0	0	0
T15	326231	0	0	0
T16	0	195	0	0
T21	2691	0	0	0
T22	513275	0	0	0
T23	0	55	0	0
T24	0	35	0	0
T30	3156	0	0	0
T31	0	275	0	0
T32	0	7	0	0
T33	0	5	0	0
T34	0	4	0	0
T35	0	2	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2214	0	0
T9	364132	167	0	0
T10	25444	0	0	0
T11	261360	146	0	0
T12	256405	0	0	0
T13	266039	0	0	0
T14	113230	0	0	0
T15	326231	0	0	0
T16	0	130	0	0
T21	2691	0	0	0
T22	513275	0	0	0
T23	0	22	0	0
T24	0	50	0	0
T30	3156	0	0	0
T31	0	308	0	0
T32	0	10	0	0
T33	0	1	0	0
T35	0	5	0	0
T36	0	2	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2199	0	0
T9	364132	114	0	0
T10	25444	0	0	0
T11	261360	137	0	0
T12	256405	0	0	0
T13	266039	0	0	0
T14	113230	0	0	0
T15	326231	0	0	0
T16	0	131	0	0
T21	2691	0	0	0
T22	513275	0	0	0
T23	0	55	0	0
T24	0	42	0	0
T30	3156	0	0	0
T31	0	208	0	0
T32	0	9	0	0
T33	0	8	0	0
T34	0	38	0	0
T35	0	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2102	0	0
T9	364132	136	0	0
T10	25444	0	0	0
T11	261360	98	0	0
T12	256405	0	0	0
T13	266039	0	0	0
T14	113230	0	0	0
T15	326231	0	0	0
T16	0	120	0	0
T21	2691	0	0	0
T22	513275	0	0	0
T23	0	57	0	0
T24	0	25	0	0
T30	3156	0	0	0
T31	0	263	0	0
T32	0	5	0	0
T34	0	12	0	0
T37	0	110	0	0
T38	0	366	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3183	0	0
T9	364132	249	0	0
T10	25444	0	0	0
T11	261360	257	0	0
T12	256405	0	0	0
T13	266039	0	0	0
T14	113230	0	0	0
T15	326231	0	0	0
T21	2691	0	0	0
T22	513275	0	0	0
T23	0	94	0	0
T24	0	128	0	0
T30	3156	0	0	0
T31	0	433	0	0
T39	0	37	0	0
T40	0	26	0	0
T41	0	8	0	0
T42	0	6	0	0
T43	0	25	0	0