Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1365056	0	0
cfg0_rd_A	2147483647	4820	0	0
compare_lower0_0_rd_A	2147483647	5089	0	0
compare_upper0_0_rd_A	2147483647	4815	0	0
ctrl_rd_A	2147483647	4372	0	0
intr_enable0_rd_A	2147483647	5631	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1365056	0	0
T12	191255	46660	0	0
T13	235080	0	0	0
T18	0	51250	0	0
T19	0	40036	0	0
T30	0	237147	0	0
T31	0	73904	0	0
T32	0	51387	0	0
T33	0	213154	0	0
T34	0	252113	0	0
T35	0	101679	0	0
T36	0	285965	0	0
T37	154369	0	0	0
T38	739464	0	0	0
T39	995963	0	0	0
T40	380433	0	0	0
T41	171788	0	0	0
T42	841089	0	0	0
T43	140856	0	0	0
T44	135284	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4820	0	0
T12	191255	470	0	0
T13	235080	0	0	0
T19	0	376	0	0
T22	0	120	0	0
T24	0	165	0	0
T32	0	508	0	0
T34	0	2597	0	0
T37	154369	0	0	0
T38	739464	0	0	0
T39	995963	0	0	0
T40	380433	0	0	0
T41	171788	0	0	0
T42	841089	0	0	0
T43	140856	0	0	0
T44	135284	0	0	0
T45	0	59	0	0
T46	0	10	0	0
T47	0	32	0	0
T48	0	6	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5089	0	0
T12	191255	524	0	0
T13	235080	0	0	0
T19	0	415	0	0
T22	0	75	0	0
T24	0	101	0	0
T32	0	578	0	0
T34	0	2961	0	0
T37	154369	0	0	0
T38	739464	0	0	0
T39	995963	0	0	0
T40	380433	0	0	0
T41	171788	0	0	0
T42	841089	0	0	0
T43	140856	0	0	0
T44	135284	0	0	0
T45	0	39	0	0
T46	0	13	0	0
T47	0	47	0	0
T48	0	2	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4815	0	0
T12	191255	480	0	0
T13	235080	0	0	0
T19	0	356	0	0
T22	0	76	0	0
T24	0	118	0	0
T32	0	425	0	0
T34	0	2841	0	0
T37	154369	0	0	0
T38	739464	0	0	0
T39	995963	0	0	0
T40	380433	0	0	0
T41	171788	0	0	0
T42	841089	0	0	0
T43	140856	0	0	0
T44	135284	0	0	0
T45	0	55	0	0
T46	0	9	0	0
T47	0	27	0	0
T48	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4372	0	0
T12	191255	385	0	0
T13	235080	0	0	0
T19	0	441	0	0
T22	0	74	0	0
T24	0	127	0	0
T32	0	456	0	0
T34	0	2392	0	0
T37	154369	0	0	0
T38	739464	0	0	0
T39	995963	0	0	0
T40	380433	0	0	0
T41	171788	0	0	0
T42	841089	0	0	0
T43	140856	0	0	0
T44	135284	0	0	0
T45	0	47	0	0
T46	0	11	0	0
T47	0	52	0	0
T49	0	8	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5631	0	0
T12	191255	553	0	0
T13	235080	0	0	0
T19	0	490	0	0
T32	0	618	0	0
T34	0	2913	0	0
T37	154369	0	0	0
T38	739464	0	0	0
T39	995963	0	0	0
T40	380433	0	0	0
T41	171788	0	0	0
T42	841089	0	0	0
T43	140856	0	0	0
T44	135284	0	0	0
T50	0	2	0	0
T51	0	12	0	0
T52	0	18	0	0
T53	0	13	0	0
T54	0	42	0	0
T55	0	89	0	0