Module Definition
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Module : rv_timer_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_timer_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_timer_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_timer_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 2147483647 9982556 0 0
cfg0_rd_A 2147483647 25653 0 0
compare_lower0_0_rd_A 2147483647 21611 0 0
compare_upper0_0_rd_A 2147483647 25261 0 0
ctrl_rd_A 2147483647 21725 0 0
intr_enable0_rd_A 2147483647 23577 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 9982556 0 0
T8 757495 313737 0 0
T9 459904 118741 0 0
T21 645207 260405 0 0
T22 376276 152659 0 0
T23 799418 212994 0 0
T24 665838 206549 0 0
T25 240591 72787 0 0
T26 134781 40312 0 0
T27 112490 294174 0 0
T28 2170 265 0 0

cfg0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 25653 0 0
T9 459904 1335 0 0
T29 12366 23 0 0
T30 3815 95 0 0
T31 2559 33 0 0
T32 1559 13 0 0
T33 1600 5 0 0
T34 1186 7 0 0
T35 15776 13 0 0
T36 16821 4 0 0
T37 2335 12 0 0

compare_lower0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 21611 0 0
T9 459904 1107 0 0
T30 3815 30 0 0
T31 2559 14 0 0
T32 1559 9 0 0
T33 1600 7 0 0
T34 1186 1 0 0
T35 15776 7 0 0
T36 16821 6 0 0
T37 2335 6 0 0
T38 20136 9 0 0

compare_upper0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 25261 0 0
T9 459904 1363 0 0
T29 12366 6 0 0
T30 3815 28 0 0
T31 2559 16 0 0
T32 1559 19 0 0
T33 1600 10 0 0
T34 1186 1 0 0
T35 15776 14 0 0
T36 16821 1 0 0
T37 2335 10 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 21725 0 0
T9 459904 1249 0 0
T29 12366 4 0 0
T30 3815 30 0 0
T31 2559 32 0 0
T32 1559 19 0 0
T33 1600 8 0 0
T34 1186 1 0 0
T35 15776 7 0 0
T36 16821 12 0 0
T37 2335 15 0 0

intr_enable0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 23577 0 0
T9 459904 1328 0 0
T29 12366 4 0 0
T30 3815 34 0 0
T31 2559 19 0 0
T32 1559 6 0 0
T33 1600 9 0 0
T39 1037 18 0 0
T40 1364 26 0 0
T41 1254 8 0 0
T42 1458 9 0 0

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