Module Definition
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Module : tlul_data_integ_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_chk.u_tlul_data_integ_dec 100.00 100.00



Module Instance : tb.dut.u_reg.u_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%