T357 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.1829710086 |
|
|
Feb 08 09:41:03 AM UTC 25 |
Feb 08 09:48:52 AM UTC 25 |
784882845041 ps |
T195 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.2280589484 |
|
|
Feb 08 09:41:11 AM UTC 25 |
Feb 08 09:48:53 AM UTC 25 |
1426014044232 ps |
T255 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.2111160214 |
|
|
Feb 08 09:38:26 AM UTC 25 |
Feb 08 09:48:54 AM UTC 25 |
529272787126 ps |
T336 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.1908812144 |
|
|
Feb 08 09:45:53 AM UTC 25 |
Feb 08 09:49:07 AM UTC 25 |
180909850745 ps |
T242 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.83027052 |
|
|
Feb 08 09:48:49 AM UTC 25 |
Feb 08 09:49:29 AM UTC 25 |
32974181754 ps |
T213 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.3637785440 |
|
|
Feb 08 09:45:05 AM UTC 25 |
Feb 08 09:49:42 AM UTC 25 |
93432951105 ps |
T252 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3782440230 |
|
|
Feb 08 09:44:17 AM UTC 25 |
Feb 08 09:49:56 AM UTC 25 |
57704075140 ps |
T361 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.145196029 |
|
|
Feb 08 09:47:53 AM UTC 25 |
Feb 08 09:49:59 AM UTC 25 |
38513054660 ps |
T225 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.2892767678 |
|
|
Feb 08 09:42:28 AM UTC 25 |
Feb 08 09:50:12 AM UTC 25 |
125672658572 ps |
T198 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.1778696784 |
|
|
Feb 08 09:45:52 AM UTC 25 |
Feb 08 09:50:12 AM UTC 25 |
142518753173 ps |
T199 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2065026049 |
|
|
Feb 08 09:50:14 AM UTC 25 |
Feb 08 09:50:18 AM UTC 25 |
2120806844 ps |
T282 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.2005823250 |
|
|
Feb 08 09:43:13 AM UTC 25 |
Feb 08 09:50:22 AM UTC 25 |
609267779663 ps |
T268 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.733942777 |
|
|
Feb 08 09:46:44 AM UTC 25 |
Feb 08 09:50:22 AM UTC 25 |
61143168414 ps |
T272 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.4190467838 |
|
|
Feb 08 09:43:52 AM UTC 25 |
Feb 08 09:50:27 AM UTC 25 |
1323985677315 ps |
T236 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.3780707220 |
|
|
Feb 08 09:46:47 AM UTC 25 |
Feb 08 09:50:37 AM UTC 25 |
723634926995 ps |
T164 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1196681231 |
|
|
Feb 08 09:16:12 AM UTC 25 |
Feb 08 09:50:43 AM UTC 25 |
3307209557262 ps |
T183 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1005895598 |
|
|
Feb 08 09:44:08 AM UTC 25 |
Feb 08 09:50:46 AM UTC 25 |
454122556586 ps |
T312 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.914100445 |
|
|
Feb 08 09:47:11 AM UTC 25 |
Feb 08 09:50:51 AM UTC 25 |
320608408398 ps |
T226 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.784129672 |
|
|
Feb 08 09:26:07 AM UTC 25 |
Feb 08 09:50:59 AM UTC 25 |
255784203893 ps |
T228 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.2911590636 |
|
|
Feb 08 09:46:30 AM UTC 25 |
Feb 08 09:51:33 AM UTC 25 |
205581914603 ps |
T372 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.1148596412 |
|
|
Feb 08 09:45:38 AM UTC 25 |
Feb 08 09:51:34 AM UTC 25 |
359612938650 ps |
T234 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.2401745396 |
|
|
Feb 08 09:50:52 AM UTC 25 |
Feb 08 09:51:48 AM UTC 25 |
113028750720 ps |
T313 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3947060079 |
|
|
Feb 08 09:40:33 AM UTC 25 |
Feb 08 09:52:06 AM UTC 25 |
1224441953557 ps |
T179 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.1265688867 |
|
|
Feb 08 09:15:21 AM UTC 25 |
Feb 08 09:52:11 AM UTC 25 |
68603892591 ps |
T378 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.1435666993 |
|
|
Feb 08 09:47:42 AM UTC 25 |
Feb 08 09:52:11 AM UTC 25 |
163112598063 ps |
T180 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3399966695 |
|
|
Feb 08 09:37:59 AM UTC 25 |
Feb 08 09:52:11 AM UTC 25 |
700085518402 ps |
T154 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.3472719189 |
|
|
Feb 08 09:46:21 AM UTC 25 |
Feb 08 09:52:24 AM UTC 25 |
328541256696 ps |
T315 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.3252895823 |
|
|
Feb 08 09:50:44 AM UTC 25 |
Feb 08 09:52:24 AM UTC 25 |
53416800413 ps |
T215 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.647213846 |
|
|
Feb 08 09:45:26 AM UTC 25 |
Feb 08 09:52:31 AM UTC 25 |
361280707827 ps |
T376 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.2836603984 |
|
|
Feb 08 09:48:34 AM UTC 25 |
Feb 08 09:52:38 AM UTC 25 |
57969587255 ps |
T243 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.1193984822 |
|
|
Feb 08 09:47:33 AM UTC 25 |
Feb 08 09:52:44 AM UTC 25 |
54332058463 ps |
T220 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2495319944 |
|
|
Feb 08 09:48:55 AM UTC 25 |
Feb 08 09:53:08 AM UTC 25 |
230709449685 ps |
T356 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.2506398275 |
|
|
Feb 08 09:44:58 AM UTC 25 |
Feb 08 09:53:13 AM UTC 25 |
39703631961 ps |
T310 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.710022837 |
|
|
Feb 08 09:50:38 AM UTC 25 |
Feb 08 09:53:14 AM UTC 25 |
269646024405 ps |
T288 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.2756744185 |
|
|
Feb 08 09:39:33 AM UTC 25 |
Feb 08 09:53:26 AM UTC 25 |
1550904299672 ps |
T285 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2879732539 |
|
|
Feb 08 09:42:25 AM UTC 25 |
Feb 08 09:53:26 AM UTC 25 |
2370888350690 ps |
T244 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1884701703 |
|
|
Feb 08 09:46:24 AM UTC 25 |
Feb 08 09:53:33 AM UTC 25 |
92904576027 ps |
T157 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.937300530 |
|
|
Feb 08 09:42:50 AM UTC 25 |
Feb 08 09:53:38 AM UTC 25 |
395485685547 ps |
T339 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.3628121146 |
|
|
Feb 08 09:52:45 AM UTC 25 |
Feb 08 09:53:47 AM UTC 25 |
23109525394 ps |
T273 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3961258810 |
|
|
Feb 08 09:18:00 AM UTC 25 |
Feb 08 09:53:52 AM UTC 25 |
3565463171053 ps |
T192 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.17831543 |
|
|
Feb 08 09:43:57 AM UTC 25 |
Feb 08 09:54:10 AM UTC 25 |
537672518085 ps |
T324 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.4183144754 |
|
|
Feb 08 09:52:11 AM UTC 25 |
Feb 08 09:54:19 AM UTC 25 |
111099024976 ps |
T175 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3636056027 |
|
|
Feb 08 09:51:49 AM UTC 25 |
Feb 08 09:54:28 AM UTC 25 |
316062073546 ps |
T266 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2310305784 |
|
|
Feb 08 09:47:35 AM UTC 25 |
Feb 08 09:54:52 AM UTC 25 |
158757088508 ps |
T271 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.901749189 |
|
|
Feb 08 09:49:07 AM UTC 25 |
Feb 08 09:55:01 AM UTC 25 |
1353897172111 ps |
T355 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.2056640050 |
|
|
Feb 08 09:52:12 AM UTC 25 |
Feb 08 09:55:05 AM UTC 25 |
79855500917 ps |
T200 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.2670918439 |
|
|
Feb 08 09:24:29 AM UTC 25 |
Feb 08 09:55:10 AM UTC 25 |
471047051760 ps |
T204 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.2618486032 |
|
|
Feb 08 09:51:34 AM UTC 25 |
Feb 08 09:55:12 AM UTC 25 |
208835753040 ps |
T303 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.3076784470 |
|
|
Feb 08 09:24:29 AM UTC 25 |
Feb 08 09:55:30 AM UTC 25 |
2716662738667 ps |
T280 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.1993673872 |
|
|
Feb 08 09:52:07 AM UTC 25 |
Feb 08 09:55:43 AM UTC 25 |
167305174792 ps |
T246 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.950736489 |
|
|
Feb 08 09:36:14 AM UTC 25 |
Feb 08 09:55:46 AM UTC 25 |
466431409967 ps |
T340 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.1820822499 |
|
|
Feb 08 09:54:28 AM UTC 25 |
Feb 08 09:55:46 AM UTC 25 |
34339806448 ps |
T159 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.3050037072 |
|
|
Feb 08 09:49:56 AM UTC 25 |
Feb 08 09:55:48 AM UTC 25 |
275435354554 ps |
T207 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.1659218186 |
|
|
Feb 08 09:50:00 AM UTC 25 |
Feb 08 09:55:49 AM UTC 25 |
382719036049 ps |
T269 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.2902086404 |
|
|
Feb 08 09:53:34 AM UTC 25 |
Feb 08 09:55:56 AM UTC 25 |
145782434955 ps |
T168 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.147498207 |
|
|
Feb 08 09:55:46 AM UTC 25 |
Feb 08 09:56:39 AM UTC 25 |
65220348333 ps |
T300 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.2490738708 |
|
|
Feb 08 09:38:58 AM UTC 25 |
Feb 08 09:56:43 AM UTC 25 |
1558419817241 ps |
T307 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.3104806906 |
|
|
Feb 08 09:52:25 AM UTC 25 |
Feb 08 09:56:44 AM UTC 25 |
736999059060 ps |
T206 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.403513622 |
|
|
Feb 08 09:42:11 AM UTC 25 |
Feb 08 09:56:53 AM UTC 25 |
645721781140 ps |
T277 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.2760275110 |
|
|
Feb 08 09:53:48 AM UTC 25 |
Feb 08 09:57:16 AM UTC 25 |
220359120115 ps |
T188 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.1231688908 |
|
|
Feb 08 09:38:56 AM UTC 25 |
Feb 08 09:57:29 AM UTC 25 |
227592350990 ps |
T247 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.3503848252 |
|
|
Feb 08 09:50:12 AM UTC 25 |
Feb 08 09:57:34 AM UTC 25 |
602321867857 ps |
T321 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.3517092147 |
|
|
Feb 08 09:44:11 AM UTC 25 |
Feb 08 09:58:01 AM UTC 25 |
524150385462 ps |
T194 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.25189563 |
|
|
Feb 08 09:36:15 AM UTC 25 |
Feb 08 09:58:02 AM UTC 25 |
351726260912 ps |
T330 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1370530624 |
|
|
Feb 08 09:53:39 AM UTC 25 |
Feb 08 09:58:13 AM UTC 25 |
163396384407 ps |
T441 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.3342661826 |
|
|
Feb 08 09:57:35 AM UTC 25 |
Feb 08 09:58:21 AM UTC 25 |
21643476475 ps |
T165 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.3077883261 |
|
|
Feb 08 09:16:22 AM UTC 25 |
Feb 08 09:58:24 AM UTC 25 |
657416755667 ps |
T260 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.3788108297 |
|
|
Feb 08 09:54:20 AM UTC 25 |
Feb 08 09:58:32 AM UTC 25 |
63414647475 ps |
T158 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1487097021 |
|
|
Feb 08 09:52:39 AM UTC 25 |
Feb 08 09:58:35 AM UTC 25 |
333589719352 ps |
T442 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.4002623286 |
|
|
Feb 08 09:57:31 AM UTC 25 |
Feb 08 09:58:43 AM UTC 25 |
22854381117 ps |
T160 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.2189854612 |
|
|
Feb 08 09:40:25 AM UTC 25 |
Feb 08 09:58:45 AM UTC 25 |
2811735155816 ps |
T245 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3630526839 |
|
|
Feb 08 09:50:46 AM UTC 25 |
Feb 08 09:59:07 AM UTC 25 |
594814244578 ps |
T443 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.1355961521 |
|
|
Feb 08 09:48:53 AM UTC 25 |
Feb 08 09:59:14 AM UTC 25 |
83932970485 ps |
T297 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2248847016 |
|
|
Feb 08 09:48:50 AM UTC 25 |
Feb 08 09:59:20 AM UTC 25 |
289713836873 ps |
T222 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.568992140 |
|
|
Feb 08 09:55:44 AM UTC 25 |
Feb 08 09:59:21 AM UTC 25 |
103789998337 ps |
T267 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.3630077233 |
|
|
Feb 08 09:36:49 AM UTC 25 |
Feb 08 09:59:22 AM UTC 25 |
1544078031424 ps |
T208 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.2585061498 |
|
|
Feb 08 09:56:45 AM UTC 25 |
Feb 08 09:59:33 AM UTC 25 |
169236647244 ps |
T276 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.2631475026 |
|
|
Feb 08 09:58:21 AM UTC 25 |
Feb 08 09:59:50 AM UTC 25 |
162318076070 ps |
T187 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2391387263 |
|
|
Feb 08 09:55:11 AM UTC 25 |
Feb 08 09:59:54 AM UTC 25 |
92050315189 ps |
T291 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.905488593 |
|
|
Feb 08 09:50:28 AM UTC 25 |
Feb 08 10:00:13 AM UTC 25 |
221706778300 ps |
T373 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.3115953053 |
|
|
Feb 08 09:58:33 AM UTC 25 |
Feb 08 10:00:16 AM UTC 25 |
7673334598 ps |
T335 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.127464222 |
|
|
Feb 08 09:53:14 AM UTC 25 |
Feb 08 10:00:16 AM UTC 25 |
633475343056 ps |
T258 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.213123313 |
|
|
Feb 08 09:50:19 AM UTC 25 |
Feb 08 10:00:21 AM UTC 25 |
426293424349 ps |
T281 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.1928677589 |
|
|
Feb 08 09:52:32 AM UTC 25 |
Feb 08 10:00:28 AM UTC 25 |
899699517046 ps |
T250 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.3288363081 |
|
|
Feb 08 09:58:46 AM UTC 25 |
Feb 08 10:00:35 AM UTC 25 |
188750291635 ps |
T229 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.2564446253 |
|
|
Feb 08 09:59:56 AM UTC 25 |
Feb 08 10:00:43 AM UTC 25 |
12943665566 ps |
T331 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1078721381 |
|
|
Feb 08 09:53:09 AM UTC 25 |
Feb 08 10:00:45 AM UTC 25 |
133115706214 ps |
T240 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.2461731450 |
|
|
Feb 08 09:47:56 AM UTC 25 |
Feb 08 10:00:49 AM UTC 25 |
813097782863 ps |
T327 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.3257085603 |
|
|
Feb 08 09:55:47 AM UTC 25 |
Feb 08 10:00:59 AM UTC 25 |
117081898054 ps |
T155 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.2713476540 |
|
|
Feb 08 09:59:16 AM UTC 25 |
Feb 08 10:01:20 AM UTC 25 |
186270290670 ps |
T368 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.401307163 |
|
|
Feb 08 09:58:03 AM UTC 25 |
Feb 08 10:01:32 AM UTC 25 |
71575332611 ps |
T314 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.4036934721 |
|
|
Feb 08 09:50:13 AM UTC 25 |
Feb 08 10:01:42 AM UTC 25 |
278314571513 ps |
T253 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.2062753041 |
|
|
Feb 08 09:30:43 AM UTC 25 |
Feb 08 10:01:54 AM UTC 25 |
490419733413 ps |
T342 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.593174457 |
|
|
Feb 08 10:00:31 AM UTC 25 |
Feb 08 10:01:55 AM UTC 25 |
27219907999 ps |
T318 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.2027185115 |
|
|
Feb 08 09:55:48 AM UTC 25 |
Feb 08 10:01:58 AM UTC 25 |
455765589296 ps |
T235 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1747810120 |
|
|
Feb 08 09:51:00 AM UTC 25 |
Feb 08 10:02:05 AM UTC 25 |
677727191550 ps |
T294 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.556503581 |
|
|
Feb 08 09:52:25 AM UTC 25 |
Feb 08 10:02:13 AM UTC 25 |
737841655408 ps |
T319 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.2979435991 |
|
|
Feb 08 09:58:02 AM UTC 25 |
Feb 08 10:02:14 AM UTC 25 |
118420188739 ps |
T189 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.2185426799 |
|
|
Feb 08 09:24:58 AM UTC 25 |
Feb 08 10:02:15 AM UTC 25 |
494876301369 ps |
T261 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.1593229485 |
|
|
Feb 08 09:58:36 AM UTC 25 |
Feb 08 10:02:16 AM UTC 25 |
245472067048 ps |
T344 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.360431844 |
|
|
Feb 08 10:00:36 AM UTC 25 |
Feb 08 10:02:20 AM UTC 25 |
61267261892 ps |
T370 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1375839368 |
|
|
Feb 08 09:59:22 AM UTC 25 |
Feb 08 10:02:25 AM UTC 25 |
220355535543 ps |
T349 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.4016689879 |
|
|
Feb 08 09:28:49 AM UTC 25 |
Feb 08 10:02:29 AM UTC 25 |
126888543511 ps |
T257 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.1574077625 |
|
|
Feb 08 09:54:11 AM UTC 25 |
Feb 08 10:02:32 AM UTC 25 |
76849346646 ps |
T173 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.1891615317 |
|
|
Feb 08 09:55:14 AM UTC 25 |
Feb 08 10:02:40 AM UTC 25 |
477446058262 ps |
T196 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2178505435 |
|
|
Feb 08 09:23:58 AM UTC 25 |
Feb 08 10:02:53 AM UTC 25 |
844335821996 ps |
T363 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.4201125752 |
|
|
Feb 08 10:00:29 AM UTC 25 |
Feb 08 10:03:03 AM UTC 25 |
52582487539 ps |
T360 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.184650193 |
|
|
Feb 08 09:57:29 AM UTC 25 |
Feb 08 10:03:19 AM UTC 25 |
167861266408 ps |
T334 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.2968374444 |
|
|
Feb 08 10:01:55 AM UTC 25 |
Feb 08 10:03:35 AM UTC 25 |
25399794737 ps |
T201 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1481561670 |
|
|
Feb 08 10:02:15 AM UTC 25 |
Feb 08 10:03:43 AM UTC 25 |
149594689955 ps |
T328 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.471840541 |
|
|
Feb 08 09:59:21 AM UTC 25 |
Feb 08 10:03:46 AM UTC 25 |
111079203809 ps |
T350 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.1648240360 |
|
|
Feb 08 09:58:25 AM UTC 25 |
Feb 08 10:03:46 AM UTC 25 |
204229196779 ps |
T270 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.578204895 |
|
|
Feb 08 09:55:57 AM UTC 25 |
Feb 08 10:03:47 AM UTC 25 |
264556934929 ps |
T351 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.4290884419 |
|
|
Feb 08 10:00:44 AM UTC 25 |
Feb 08 10:03:53 AM UTC 25 |
98638023891 ps |
T444 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.1513821713 |
|
|
Feb 08 09:55:06 AM UTC 25 |
Feb 08 10:04:26 AM UTC 25 |
563130513788 ps |
T311 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.1339799127 |
|
|
Feb 08 10:00:29 AM UTC 25 |
Feb 08 10:04:33 AM UTC 25 |
161595519385 ps |
T265 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.1769979196 |
|
|
Feb 08 09:58:44 AM UTC 25 |
Feb 08 10:04:47 AM UTC 25 |
221267204605 ps |
T445 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.1695840463 |
|
|
Feb 08 09:53:53 AM UTC 25 |
Feb 08 10:04:54 AM UTC 25 |
76036608278 ps |
T184 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.3157673165 |
|
|
Feb 08 09:59:50 AM UTC 25 |
Feb 08 10:05:05 AM UTC 25 |
106208908196 ps |
T348 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.237408903 |
|
|
Feb 08 09:50:22 AM UTC 25 |
Feb 08 10:05:07 AM UTC 25 |
531683388292 ps |
T446 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.678432118 |
|
|
Feb 08 09:56:40 AM UTC 25 |
Feb 08 10:05:11 AM UTC 25 |
22508868582 ps |
T295 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.2707414159 |
|
|
Feb 08 09:55:31 AM UTC 25 |
Feb 08 10:05:16 AM UTC 25 |
85374141261 ps |
T329 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2216162335 |
|
|
Feb 08 10:02:16 AM UTC 25 |
Feb 08 10:05:18 AM UTC 25 |
417674517577 ps |
T209 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.3021787738 |
|
|
Feb 08 09:33:31 AM UTC 25 |
Feb 08 10:05:38 AM UTC 25 |
534240618570 ps |
T362 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.4251734093 |
|
|
Feb 08 10:00:46 AM UTC 25 |
Feb 08 10:05:40 AM UTC 25 |
375936250452 ps |
T218 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3875576009 |
|
|
Feb 08 10:01:55 AM UTC 25 |
Feb 08 10:06:04 AM UTC 25 |
464910233092 ps |
T447 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.3075039199 |
|
|
Feb 08 09:54:53 AM UTC 25 |
Feb 08 10:06:23 AM UTC 25 |
279888220826 ps |
T369 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.3988442413 |
|
|
Feb 08 10:00:50 AM UTC 25 |
Feb 08 10:06:31 AM UTC 25 |
627156184372 ps |
T380 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3072575131 |
|
|
Feb 08 09:57:16 AM UTC 25 |
Feb 08 10:06:31 AM UTC 25 |
570299778367 ps |
T197 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.3826790988 |
|
|
Feb 08 09:55:50 AM UTC 25 |
Feb 08 10:06:56 AM UTC 25 |
391764372685 ps |
T202 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1729277406 |
|
|
Feb 08 10:01:21 AM UTC 25 |
Feb 08 10:07:13 AM UTC 25 |
222046325582 ps |
T377 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3737885853 |
|
|
Feb 08 09:58:14 AM UTC 25 |
Feb 08 10:07:19 AM UTC 25 |
102857246189 ps |
T366 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.2116169473 |
|
|
Feb 08 09:53:26 AM UTC 25 |
Feb 08 10:07:19 AM UTC 25 |
206413747394 ps |
T343 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.877749558 |
|
|
Feb 08 09:55:02 AM UTC 25 |
Feb 08 10:07:31 AM UTC 25 |
580822561678 ps |
T448 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.701678920 |
|
|
Feb 08 09:59:23 AM UTC 25 |
Feb 08 10:07:32 AM UTC 25 |
288112080939 ps |
T326 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3540862958 |
|
|
Feb 08 10:00:29 AM UTC 25 |
Feb 08 10:07:41 AM UTC 25 |
380907352465 ps |
T449 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.1316458081 |
|
|
Feb 08 10:02:06 AM UTC 25 |
Feb 08 10:07:43 AM UTC 25 |
88542011078 ps |
T359 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.32701539 |
|
|
Feb 08 10:01:33 AM UTC 25 |
Feb 08 10:08:13 AM UTC 25 |
166139465019 ps |
T219 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.252723642 |
|
|
Feb 08 09:59:34 AM UTC 25 |
Feb 08 10:08:26 AM UTC 25 |
51080737342 ps |
T365 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.3382400247 |
|
|
Feb 08 10:02:14 AM UTC 25 |
Feb 08 10:09:11 AM UTC 25 |
736439151874 ps |
T203 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.412845919 |
|
|
Feb 08 10:01:43 AM UTC 25 |
Feb 08 10:09:13 AM UTC 25 |
161180971985 ps |
T358 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.3427133759 |
|
|
Feb 08 09:24:14 AM UTC 25 |
Feb 08 10:10:04 AM UTC 25 |
633624736690 ps |
T337 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.43764325 |
|
|
Feb 08 10:01:59 AM UTC 25 |
Feb 08 10:10:29 AM UTC 25 |
154366561666 ps |
T320 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.3405329199 |
|
|
Feb 08 10:00:29 AM UTC 25 |
Feb 08 10:11:54 AM UTC 25 |
187765176988 ps |
T211 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.1385717105 |
|
|
Feb 08 09:52:12 AM UTC 25 |
Feb 08 10:12:00 AM UTC 25 |
193447928957 ps |
T283 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.3863743495 |
|
|
Feb 08 10:00:59 AM UTC 25 |
Feb 08 10:12:18 AM UTC 25 |
166051512407 ps |
T181 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.674892065 |
|
|
Feb 08 09:50:23 AM UTC 25 |
Feb 08 10:12:36 AM UTC 25 |
807068099319 ps |
T217 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.2325750207 |
|
|
Feb 08 09:53:26 AM UTC 25 |
Feb 08 10:12:51 AM UTC 25 |
372346202471 ps |
T450 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.2652541058 |
|
|
Feb 08 09:51:35 AM UTC 25 |
Feb 08 10:12:59 AM UTC 25 |
119876515261 ps |
T371 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.1104771614 |
|
|
Feb 08 09:56:44 AM UTC 25 |
Feb 08 10:13:24 AM UTC 25 |
92308363790 ps |
T221 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.1999220453 |
|
|
Feb 08 09:59:08 AM UTC 25 |
Feb 08 10:13:35 AM UTC 25 |
391505213375 ps |
T251 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.3434109230 |
|
|
Feb 08 09:50:23 AM UTC 25 |
Feb 08 10:13:44 AM UTC 25 |
841999464734 ps |
T379 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.1036933588 |
|
|
Feb 08 09:53:15 AM UTC 25 |
Feb 08 10:13:46 AM UTC 25 |
372094822478 ps |
T375 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.4011447421 |
|
|
Feb 08 09:49:30 AM UTC 25 |
Feb 08 10:15:41 AM UTC 25 |
242013461369 ps |
T341 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.2562478417 |
|
|
Feb 08 09:56:53 AM UTC 25 |
Feb 08 10:18:10 AM UTC 25 |
55253124620 ps |
T451 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.2398919296 |
|
|
Feb 08 09:49:43 AM UTC 25 |
Feb 08 10:18:48 AM UTC 25 |
569353012606 ps |
T316 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.2001863014 |
|
|
Feb 08 09:39:17 AM UTC 25 |
Feb 08 10:23:07 AM UTC 25 |
2604899236900 ps |
T364 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1118125631 |
|
|
Feb 08 09:32:46 AM UTC 25 |
Feb 08 10:23:11 AM UTC 25 |
1721737196369 ps |
T162 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.2878713718 |
|
|
Feb 08 09:29:43 AM UTC 25 |
Feb 08 10:23:25 AM UTC 25 |
3634824003608 ps |
T354 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.2777879706 |
|
|
Feb 08 09:48:54 AM UTC 25 |
Feb 08 10:23:25 AM UTC 25 |
752604440163 ps |
T293 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.545885873 |
|
|
Feb 08 09:46:18 AM UTC 25 |
Feb 08 10:24:07 AM UTC 25 |
689329300987 ps |
T182 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.3727672420 |
|
|
Feb 08 09:34:24 AM UTC 25 |
Feb 08 10:38:13 AM UTC 25 |
2147192455997 ps |
T177 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.3650386653 |
|
|
Feb 08 09:28:45 AM UTC 25 |
Feb 08 10:38:21 AM UTC 25 |
997065198266 ps |
T22 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1023579301 |
|
|
Feb 08 09:14:26 AM UTC 25 |
Feb 08 09:14:30 AM UTC 25 |
91440294 ps |
T452 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.1045465891 |
|
|
Feb 08 09:14:26 AM UTC 25 |
Feb 08 09:14:31 AM UTC 25 |
145277704 ps |
T453 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.3865676593 |
|
|
Feb 08 09:14:30 AM UTC 25 |
Feb 08 09:14:32 AM UTC 25 |
14428573 ps |
T26 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.653603852 |
|
|
Feb 08 09:14:30 AM UTC 25 |
Feb 08 09:14:32 AM UTC 25 |
44311239 ps |
T27 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.1676045219 |
|
|
Feb 08 09:14:31 AM UTC 25 |
Feb 08 09:14:33 AM UTC 25 |
12545440 ps |
T86 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2127750832 |
|
|
Feb 08 09:14:32 AM UTC 25 |
Feb 08 09:14:35 AM UTC 25 |
240758555 ps |
T79 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3220560161 |
|
|
Feb 08 09:14:33 AM UTC 25 |
Feb 08 09:14:36 AM UTC 25 |
26469856 ps |
T454 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2651529872 |
|
|
Feb 08 09:14:33 AM UTC 25 |
Feb 08 09:14:36 AM UTC 25 |
15945551 ps |
T455 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2700911381 |
|
|
Feb 08 09:14:32 AM UTC 25 |
Feb 08 09:14:36 AM UTC 25 |
100572580 ps |
T23 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3712494273 |
|
|
Feb 08 09:14:35 AM UTC 25 |
Feb 08 09:14:38 AM UTC 25 |
334169843 ps |
T456 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.876093461 |
|
|
Feb 08 09:14:34 AM UTC 25 |
Feb 08 09:14:39 AM UTC 25 |
87585510 ps |
T64 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1564191430 |
|
|
Feb 08 09:14:37 AM UTC 25 |
Feb 08 09:14:39 AM UTC 25 |
12058459 ps |
T65 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4117767556 |
|
|
Feb 08 09:14:37 AM UTC 25 |
Feb 08 09:14:39 AM UTC 25 |
17016228 ps |
T457 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.1962985551 |
|
|
Feb 08 09:14:37 AM UTC 25 |
Feb 08 09:14:39 AM UTC 25 |
14492137 ps |
T45 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.691151165 |
|
|
Feb 08 09:14:39 AM UTC 25 |
Feb 08 09:14:41 AM UTC 25 |
138914873 ps |
T80 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3813894016 |
|
|
Feb 08 09:14:39 AM UTC 25 |
Feb 08 09:14:42 AM UTC 25 |
38884271 ps |
T46 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1145009624 |
|
|
Feb 08 09:14:41 AM UTC 25 |
Feb 08 09:14:44 AM UTC 25 |
70016005 ps |
T458 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2816069276 |
|
|
Feb 08 09:14:41 AM UTC 25 |
Feb 08 09:14:44 AM UTC 25 |
19741395 ps |
T459 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3605828898 |
|
|
Feb 08 09:14:41 AM UTC 25 |
Feb 08 09:14:44 AM UTC 25 |
27914469 ps |
T460 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.2072909016 |
|
|
Feb 08 09:14:41 AM UTC 25 |
Feb 08 09:14:44 AM UTC 25 |
37711734 ps |
T24 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1767961650 |
|
|
Feb 08 09:14:41 AM UTC 25 |
Feb 08 09:14:45 AM UTC 25 |
131721169 ps |
T66 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2636604625 |
|
|
Feb 08 09:14:39 AM UTC 25 |
Feb 08 09:14:45 AM UTC 25 |
284810694 ps |
T461 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.685227705 |
|
|
Feb 08 09:14:43 AM UTC 25 |
Feb 08 09:14:46 AM UTC 25 |
15418385 ps |
T67 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.491539633 |
|
|
Feb 08 09:14:43 AM UTC 25 |
Feb 08 09:14:46 AM UTC 25 |
52514068 ps |
T47 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3505095459 |
|
|
Feb 08 09:14:43 AM UTC 25 |
Feb 08 09:14:46 AM UTC 25 |
21012645 ps |
T462 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3920014134 |
|
|
Feb 08 09:14:43 AM UTC 25 |
Feb 08 09:14:47 AM UTC 25 |
198811887 ps |
T48 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3586497436 |
|
|
Feb 08 09:14:44 AM UTC 25 |
Feb 08 09:14:48 AM UTC 25 |
68261385 ps |
T463 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3533629483 |
|
|
Feb 08 09:14:46 AM UTC 25 |
Feb 08 09:14:48 AM UTC 25 |
32915173 ps |
T88 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2489457387 |
|
|
Feb 08 09:14:46 AM UTC 25 |
Feb 08 09:14:49 AM UTC 25 |
72816994 ps |
T49 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.257049322 |
|
|
Feb 08 09:14:47 AM UTC 25 |
Feb 08 09:14:49 AM UTC 25 |
32973165 ps |
T68 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.416765590 |
|
|
Feb 08 09:14:47 AM UTC 25 |
Feb 08 09:14:50 AM UTC 25 |
58389424 ps |
T464 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3909249606 |
|
|
Feb 08 09:14:47 AM UTC 25 |
Feb 08 09:14:50 AM UTC 25 |
20385676 ps |
T465 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.2993416904 |
|
|
Feb 08 09:14:46 AM UTC 25 |
Feb 08 09:14:50 AM UTC 25 |
316026220 ps |
T69 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1597878962 |
|
|
Feb 08 09:14:47 AM UTC 25 |
Feb 08 09:14:50 AM UTC 25 |
68882653 ps |
T466 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2057450490 |
|
|
Feb 08 09:14:47 AM UTC 25 |
Feb 08 09:14:50 AM UTC 25 |
74373920 ps |
T467 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.31166812 |
|
|
Feb 08 09:14:49 AM UTC 25 |
Feb 08 09:14:52 AM UTC 25 |
20071894 ps |
T468 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3082584843 |
|
|
Feb 08 09:14:49 AM UTC 25 |
Feb 08 09:14:52 AM UTC 25 |
54781029 ps |
T87 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.394475948 |
|
|
Feb 08 09:14:49 AM UTC 25 |
Feb 08 09:14:52 AM UTC 25 |
309208839 ps |
T469 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.3046828153 |
|
|
Feb 08 09:14:49 AM UTC 25 |
Feb 08 09:14:52 AM UTC 25 |
21560652 ps |
T470 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.421576295 |
|
|
Feb 08 09:14:49 AM UTC 25 |
Feb 08 09:14:53 AM UTC 25 |
289114332 ps |
T70 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.75151469 |
|
|
Feb 08 09:14:51 AM UTC 25 |
Feb 08 09:14:53 AM UTC 25 |
26861330 ps |
T81 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1274054 |
|
|
Feb 08 09:14:51 AM UTC 25 |
Feb 08 09:14:54 AM UTC 25 |
15075195 ps |
T471 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.1018656103 |
|
|
Feb 08 09:14:49 AM UTC 25 |
Feb 08 09:14:54 AM UTC 25 |
192440349 ps |
T472 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3819930864 |
|
|
Feb 08 09:14:51 AM UTC 25 |
Feb 08 09:14:54 AM UTC 25 |
117185314 ps |
T473 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.1018950098 |
|
|
Feb 08 09:14:51 AM UTC 25 |
Feb 08 09:14:54 AM UTC 25 |
201260219 ps |
T474 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.4130954531 |
|
|
Feb 08 09:14:52 AM UTC 25 |
Feb 08 09:14:55 AM UTC 25 |
22755073 ps |
T475 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3930790627 |
|
|
Feb 08 09:14:52 AM UTC 25 |
Feb 08 09:14:55 AM UTC 25 |
25169126 ps |
T476 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.341242565 |
|
|
Feb 08 09:14:52 AM UTC 25 |
Feb 08 09:14:55 AM UTC 25 |
47873031 ps |
T82 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2714523479 |
|
|
Feb 08 09:14:53 AM UTC 25 |
Feb 08 09:14:56 AM UTC 25 |
36396913 ps |
T71 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1151304397 |
|
|
Feb 08 09:14:51 AM UTC 25 |
Feb 08 09:14:56 AM UTC 25 |
344011746 ps |
T477 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1306392627 |
|
|
Feb 08 09:14:53 AM UTC 25 |
Feb 08 09:14:56 AM UTC 25 |
54816475 ps |
T91 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1753685335 |
|
|
Feb 08 09:14:53 AM UTC 25 |
Feb 08 09:14:57 AM UTC 25 |
115846965 ps |
T478 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.905581153 |
|
|
Feb 08 09:14:55 AM UTC 25 |
Feb 08 09:14:57 AM UTC 25 |
44891640 ps |
T479 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.2288900161 |
|
|
Feb 08 09:14:55 AM UTC 25 |
Feb 08 09:14:58 AM UTC 25 |
20655781 ps |
T480 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.824709262 |
|
|
Feb 08 09:14:55 AM UTC 25 |
Feb 08 09:14:58 AM UTC 25 |
16461823 ps |
T83 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.4217002520 |
|
|
Feb 08 09:14:55 AM UTC 25 |
Feb 08 09:14:58 AM UTC 25 |
64399851 ps |
T481 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.931226786 |
|
|
Feb 08 09:14:55 AM UTC 25 |
Feb 08 09:14:58 AM UTC 25 |
28616300 ps |
T482 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.379124746 |
|
|
Feb 08 09:14:55 AM UTC 25 |
Feb 08 09:14:59 AM UTC 25 |
1178740898 ps |
T483 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.283595655 |
|
|
Feb 08 09:14:53 AM UTC 25 |
Feb 08 09:14:59 AM UTC 25 |
727828451 ps |
T72 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.505537906 |
|
|
Feb 08 09:14:56 AM UTC 25 |
Feb 08 09:14:59 AM UTC 25 |
58320377 ps |
T84 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1810427228 |
|
|
Feb 08 09:14:56 AM UTC 25 |
Feb 08 09:14:59 AM UTC 25 |
91343527 ps |
T484 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1780532857 |
|
|
Feb 08 09:14:56 AM UTC 25 |
Feb 08 09:14:59 AM UTC 25 |
73254488 ps |
T485 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.665706978 |
|
|
Feb 08 09:14:55 AM UTC 25 |
Feb 08 09:15:00 AM UTC 25 |
280439913 ps |
T486 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.752722113 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
50217489 ps |
T85 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1147977586 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
34969196 ps |
T73 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.4089075132 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
36354607 ps |
T487 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3060912077 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
16673534 ps |
T488 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2786315457 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
21614215 ps |
T89 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.926175026 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
90912534 ps |
T489 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.890569516 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
29529048 ps |
T490 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2485846010 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:02 AM UTC 25 |
22459772 ps |
T491 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3665061293 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:03 AM UTC 25 |
15540551 ps |
T492 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2851260707 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:03 AM UTC 25 |
41305031 ps |
T493 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3661986180 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:03 AM UTC 25 |
83705064 ps |
T494 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.2407784809 |
|
|
Feb 08 09:14:59 AM UTC 25 |
Feb 08 09:15:03 AM UTC 25 |
221336652 ps |
T495 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.587148704 |
|
|
Feb 08 09:15:01 AM UTC 25 |
Feb 08 09:15:04 AM UTC 25 |
16777077 ps |
T496 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.2322304116 |
|
|
Feb 08 09:15:01 AM UTC 25 |
Feb 08 09:15:04 AM UTC 25 |
14472474 ps |
T497 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.748385323 |
|
|
Feb 08 09:15:01 AM UTC 25 |
Feb 08 09:15:04 AM UTC 25 |
47444404 ps |
T498 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4036806065 |
|
|
Feb 08 09:15:01 AM UTC 25 |
Feb 08 09:15:04 AM UTC 25 |
139201470 ps |
T499 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3690367957 |
|
|
Feb 08 09:15:01 AM UTC 25 |
Feb 08 09:15:05 AM UTC 25 |
155626637 ps |
T90 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1127488666 |
|
|
Feb 08 09:15:01 AM UTC 25 |
Feb 08 09:15:05 AM UTC 25 |
850231363 ps |
T500 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.3508591057 |
|
|
Feb 08 09:15:02 AM UTC 25 |
Feb 08 09:15:06 AM UTC 25 |
141872850 ps |
T501 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.69395507 |
|
|
Feb 08 09:15:04 AM UTC 25 |
Feb 08 09:15:06 AM UTC 25 |
22553071 ps |
T502 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.288895762 |
|
|
Feb 08 09:15:04 AM UTC 25 |
Feb 08 09:15:06 AM UTC 25 |
13755249 ps |
T503 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.4182541921 |
|
|
Feb 08 09:15:04 AM UTC 25 |
Feb 08 09:15:06 AM UTC 25 |
10490934 ps |
T504 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.72692418 |
|
|
Feb 08 09:15:04 AM UTC 25 |
Feb 08 09:15:06 AM UTC 25 |
47937952 ps |
T505 |
/workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4257305762 |
|
|
Feb 08 09:15:04 AM UTC 25 |
Feb 08 09:15:06 AM UTC 25 |
117736742 ps |