| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.61 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.55 |
| T506 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1146425048 | Feb 08 09:15:04 AM UTC 25 | Feb 08 09:15:06 AM UTC 25 | 121061432 ps | ||
| T507 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1348286544 | Feb 08 09:15:04 AM UTC 25 | Feb 08 09:15:06 AM UTC 25 | 56366571 ps | ||
| T508 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.890559904 | Feb 08 09:15:04 AM UTC 25 | Feb 08 09:15:07 AM UTC 25 | 65980039 ps | ||
| T509 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3587401196 | Feb 08 09:15:04 AM UTC 25 | Feb 08 09:15:07 AM UTC 25 | 55585251 ps | ||
| T510 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2111068518 | Feb 08 09:15:04 AM UTC 25 | Feb 08 09:15:07 AM UTC 25 | 414198653 ps | ||
| T511 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3566260297 | Feb 08 09:15:04 AM UTC 25 | Feb 08 09:15:07 AM UTC 25 | 309306066 ps | ||
| T512 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3518955083 | Feb 08 09:15:04 AM UTC 25 | Feb 08 09:15:07 AM UTC 25 | 77799194 ps | ||
| T513 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.336639722 | Feb 08 09:15:05 AM UTC 25 | Feb 08 09:15:08 AM UTC 25 | 13759539 ps | ||
| T514 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2452304416 | Feb 08 09:15:05 AM UTC 25 | Feb 08 09:15:08 AM UTC 25 | 71987424 ps | ||
| T515 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1621328030 | Feb 08 09:15:05 AM UTC 25 | Feb 08 09:15:08 AM UTC 25 | 95637553 ps | ||
| T516 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3259820031 | Feb 08 09:15:06 AM UTC 25 | Feb 08 09:15:08 AM UTC 25 | 470583109 ps | ||
| T517 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1348822537 | Feb 08 09:15:06 AM UTC 25 | Feb 08 09:15:09 AM UTC 25 | 110716025 ps | ||
| T518 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1478292250 | Feb 08 09:15:06 AM UTC 25 | Feb 08 09:15:09 AM UTC 25 | 106681815 ps | ||
| T519 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.167656699 | Feb 08 09:15:05 AM UTC 25 | Feb 08 09:15:09 AM UTC 25 | 80807654 ps | ||
| T520 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.972304115 | Feb 08 09:15:07 AM UTC 25 | Feb 08 09:15:10 AM UTC 25 | 50086055 ps | ||
| T74 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3811902479 | Feb 08 09:15:07 AM UTC 25 | Feb 08 09:15:10 AM UTC 25 | 126671511 ps | ||
| T521 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3662634843 | Feb 08 09:15:07 AM UTC 25 | Feb 08 09:15:10 AM UTC 25 | 30429919 ps | ||
| T522 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.788570966 | Feb 08 09:15:05 AM UTC 25 | Feb 08 09:15:10 AM UTC 25 | 219571350 ps | ||
| T523 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1944889322 | Feb 08 09:15:07 AM UTC 25 | Feb 08 09:15:10 AM UTC 25 | 164527153 ps | ||
| T75 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.1421753914 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:10 AM UTC 25 | 14674807 ps | ||
| T524 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2304040139 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:10 AM UTC 25 | 24105592 ps | ||
| T76 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.4044692917 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:11 AM UTC 25 | 40107906 ps | ||
| T525 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.3253758813 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:11 AM UTC 25 | 33664795 ps | ||
| T526 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.723185074 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:11 AM UTC 25 | 137583729 ps | ||
| T527 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3499226 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:11 AM UTC 25 | 693487607 ps | ||
| T528 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.263354542 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:11 AM UTC 25 | 73858755 ps | ||
| T529 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4098412456 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:11 AM UTC 25 | 846396400 ps | ||
| T530 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.285239759 | Feb 08 09:15:08 AM UTC 25 | Feb 08 09:15:12 AM UTC 25 | 72724551 ps | ||
| T531 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4068343461 | Feb 08 09:15:10 AM UTC 25 | Feb 08 09:15:12 AM UTC 25 | 67826890 ps | ||
| T77 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2253443215 | Feb 08 09:15:10 AM UTC 25 | Feb 08 09:15:12 AM UTC 25 | 14028916 ps | ||
| T532 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.832446948 | Feb 08 09:15:10 AM UTC 25 | Feb 08 09:15:13 AM UTC 25 | 107107866 ps | ||
| T533 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.846285654 | Feb 08 09:15:10 AM UTC 25 | Feb 08 09:15:13 AM UTC 25 | 20971674 ps | ||
| T534 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3883845334 | Feb 08 09:15:10 AM UTC 25 | Feb 08 09:15:13 AM UTC 25 | 121090699 ps | ||
| T535 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.624066573 | Feb 08 09:15:10 AM UTC 25 | Feb 08 09:15:13 AM UTC 25 | 24014655 ps | ||
| T536 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2813517549 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:14 AM UTC 25 | 46601978 ps | ||
| T537 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2496169579 | Feb 08 09:15:10 AM UTC 25 | Feb 08 09:15:14 AM UTC 25 | 95972098 ps | ||
| T538 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.2369732569 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:14 AM UTC 25 | 16786589 ps | ||
| T539 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.721018936 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:14 AM UTC 25 | 102592964 ps | ||
| T540 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1229959336 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:14 AM UTC 25 | 33891167 ps | ||
| T541 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3723958919 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:14 AM UTC 25 | 45160934 ps | ||
| T542 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.752187297 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:14 AM UTC 25 | 348469305 ps | ||
| T543 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1780613999 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 22337733 ps | ||
| T544 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1465757348 | Feb 08 09:15:12 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 51719897 ps | ||
| T545 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1188410214 | Feb 08 09:15:11 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 910822212 ps | ||
| T546 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1727210330 | Feb 08 09:15:12 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 11217924 ps | ||
| T78 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2205410606 | Feb 08 09:15:12 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 15948936 ps | ||
| T547 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.1367407706 | Feb 08 09:15:12 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 11293588 ps | ||
| T548 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.745953422 | Feb 08 09:15:12 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 55135793 ps | ||
| T549 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.888811178 | Feb 08 09:15:12 AM UTC 25 | Feb 08 09:15:15 AM UTC 25 | 72175456 ps | ||
| T550 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1344282182 | Feb 08 09:15:12 AM UTC 25 | Feb 08 09:15:16 AM UTC 25 | 16990344 ps | ||
| T551 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2894487666 | Feb 08 09:15:13 AM UTC 25 | Feb 08 09:15:16 AM UTC 25 | 14695423 ps | ||
| T552 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3340157255 | Feb 08 09:15:13 AM UTC 25 | Feb 08 09:15:16 AM UTC 25 | 14683831 ps | ||
| T553 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2486040094 | Feb 08 09:15:13 AM UTC 25 | Feb 08 09:15:16 AM UTC 25 | 46698096 ps | ||
| T554 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.3519129241 | Feb 08 09:15:13 AM UTC 25 | Feb 08 09:15:16 AM UTC 25 | 49901251 ps | ||
| T555 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.3351965120 | Feb 08 09:15:13 AM UTC 25 | Feb 08 09:15:16 AM UTC 25 | 12379028 ps | ||
| T556 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3643589120 | Feb 08 09:15:15 AM UTC 25 | Feb 08 09:15:17 AM UTC 25 | 11235540 ps | ||
| T557 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.3746991874 | Feb 08 09:15:15 AM UTC 25 | Feb 08 09:15:17 AM UTC 25 | 25480780 ps | ||
| T558 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2805628206 | Feb 08 09:15:15 AM UTC 25 | Feb 08 09:15:17 AM UTC 25 | 21383877 ps | ||
| T559 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.3916490371 | Feb 08 09:15:15 AM UTC 25 | Feb 08 09:15:17 AM UTC 25 | 15743361 ps | ||
| T560 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1060342618 | Feb 08 09:15:15 AM UTC 25 | Feb 08 09:15:17 AM UTC 25 | 32202087 ps | ||
| T561 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.2518945836 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:18 AM UTC 25 | 86782616 ps | ||
| T562 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.1542526371 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:18 AM UTC 25 | 38670673 ps | ||
| T563 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.702555336 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:19 AM UTC 25 | 15218092 ps | ||
| T564 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.573097853 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:19 AM UTC 25 | 12560787 ps | ||
| T565 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1779736712 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:19 AM UTC 25 | 17428405 ps | ||
| T566 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.211077699 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:19 AM UTC 25 | 22617920 ps | ||
| T567 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.4023468992 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:19 AM UTC 25 | 57153664 ps | ||
| T568 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4287303217 | Feb 08 09:15:16 AM UTC 25 | Feb 08 09:15:19 AM UTC 25 | 42117743 ps | ||
| T569 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.2924030591 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:20 AM UTC 25 | 12273733 ps | ||
| T570 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.53104563 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:20 AM UTC 25 | 11171113 ps | ||
| T571 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.990120832 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:20 AM UTC 25 | 32309881 ps | ||
| T572 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.861653 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:20 AM UTC 25 | 20233387 ps | ||
| T573 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1041634403 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:20 AM UTC 25 | 78492223 ps | ||
| T574 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2031670465 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:20 AM UTC 25 | 38199452 ps | ||
| T575 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.3690234029 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:20 AM UTC 25 | 61473802 ps | ||
| T576 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.617675982 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:21 AM UTC 25 | 20508493 ps | ||
| T577 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.3788293763 | Feb 08 09:15:17 AM UTC 25 | Feb 08 09:15:21 AM UTC 25 | 14934629 ps | ||
| T578 | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.1572995519 | Feb 08 09:15:18 AM UTC 25 | Feb 08 09:15:21 AM UTC 25 | 11322615 ps |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.2876678722 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 52228915968 ps |
| CPU time | 35.14 seconds |
| Started | Feb 08 09:23:10 AM UTC 25 |
| Finished | Feb 08 09:23:47 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876678722 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.2876678722 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3572812109 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 124168340386 ps |
| CPU time | 98.08 seconds |
| Started | Feb 08 09:15:28 AM UTC 25 |
| Finished | Feb 08 09:17:09 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572812109 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3572812109 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all_with_rand_reset.4255416841 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 86935393723 ps |
| CPU time | 171.23 seconds |
| Started | Feb 08 09:19:38 AM UTC 25 |
| Finished | Feb 08 09:22:33 AM UTC 25 |
| Peak memory | 215624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=4255416841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_a ll_with_rand_reset.4255416841 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.3686136886 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 93054384 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 09:15:22 AM UTC 25 |
| Finished | Feb 08 09:15:25 AM UTC 25 |
| Peak memory | 231408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686136886 -assert nopostproc +UVM_TESTNAME=rv_timer_base _test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3686136886 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.2670918439 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 471047051760 ps |
| CPU time | 1821.02 seconds |
| Started | Feb 08 09:24:29 AM UTC 25 |
| Finished | Feb 08 09:55:10 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670918439 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.2670918439 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1476514725 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 541762767500 ps |
| CPU time | 434.06 seconds |
| Started | Feb 08 09:15:39 AM UTC 25 |
| Finished | Feb 08 09:22:59 AM UTC 25 |
| Peak memory | 199484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476514725 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1476514725 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2178505435 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 844335821996 ps |
| CPU time | 2310.56 seconds |
| Started | Feb 08 09:23:58 AM UTC 25 |
| Finished | Feb 08 10:02:53 AM UTC 25 |
| Peak memory | 202236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178505435 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.2178505435 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.3166691865 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1230123359469 ps |
| CPU time | 1294.54 seconds |
| Started | Feb 08 09:25:20 AM UTC 25 |
| Finished | Feb 08 09:47:10 AM UTC 25 |
| Peak memory | 201932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166691865 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.3166691865 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.3650386653 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 997065198266 ps |
| CPU time | 4134.26 seconds |
| Started | Feb 08 09:28:45 AM UTC 25 |
| Finished | Feb 08 10:38:21 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650386653 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.3650386653 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3810912501 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 396817369127 ps |
| CPU time | 1225.03 seconds |
| Started | Feb 08 09:15:36 AM UTC 25 |
| Finished | Feb 08 09:36:13 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810912501 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.3810912501 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4117767556 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 17016228 ps |
| CPU time | 0.89 seconds |
| Started | Feb 08 09:14:37 AM UTC 25 |
| Finished | Feb 08 09:14:39 AM UTC 25 |
| Peak memory | 199056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117767556 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.4117767556 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.3573493399 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 68599303551 ps |
| CPU time | 200.15 seconds |
| Started | Feb 08 09:15:20 AM UTC 25 |
| Finished | Feb 08 09:18:44 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573493399 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3573493399 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.2185426799 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 494876301369 ps |
| CPU time | 2214.36 seconds |
| Started | Feb 08 09:24:58 AM UTC 25 |
| Finished | Feb 08 10:02:15 AM UTC 25 |
| Peak memory | 202164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185426799 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.2185426799 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3961258810 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3565463171053 ps |
| CPU time | 2130.64 seconds |
| Started | Feb 08 09:18:00 AM UTC 25 |
| Finished | Feb 08 09:53:52 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961258810 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.3961258810 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1883923884 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 215073651484 ps |
| CPU time | 559.25 seconds |
| Started | Feb 08 09:29:10 AM UTC 25 |
| Finished | Feb 08 09:38:37 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883923884 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1883923884 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1196681231 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3307209557262 ps |
| CPU time | 2050.68 seconds |
| Started | Feb 08 09:16:12 AM UTC 25 |
| Finished | Feb 08 09:50:43 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196681231 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.1196681231 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1767961650 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 131721169 ps |
| CPU time | 2.15 seconds |
| Started | Feb 08 09:14:41 AM UTC 25 |
| Finished | Feb 08 09:14:45 AM UTC 25 |
| Peak memory | 201064 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767961650 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.1767961650 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.619824984 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 996109128628 ps |
| CPU time | 799.8 seconds |
| Started | Feb 08 09:27:07 AM UTC 25 |
| Finished | Feb 08 09:40:36 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619824984 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.619824984 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.2189854612 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2811735155816 ps |
| CPU time | 1088.47 seconds |
| Started | Feb 08 09:40:25 AM UTC 25 |
| Finished | Feb 08 09:58:45 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189854612 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.2189854612 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.700538117 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1995697677015 ps |
| CPU time | 441.93 seconds |
| Started | Feb 08 09:20:59 AM UTC 25 |
| Finished | Feb 08 09:28:26 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700538117 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.700538117 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.1178919619 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2859474288865 ps |
| CPU time | 1513.31 seconds |
| Started | Feb 08 09:17:41 AM UTC 25 |
| Finished | Feb 08 09:43:12 AM UTC 25 |
| Peak memory | 202036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178919619 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.1178919619 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.2878713718 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 3634824003608 ps |
| CPU time | 3187.46 seconds |
| Started | Feb 08 09:29:43 AM UTC 25 |
| Finished | Feb 08 10:23:25 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878713718 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.2878713718 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.2062753041 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 490419733413 ps |
| CPU time | 1850.76 seconds |
| Started | Feb 08 09:30:43 AM UTC 25 |
| Finished | Feb 08 10:01:54 AM UTC 25 |
| Peak memory | 202164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062753041 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.2062753041 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.2877320515 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 26775208275 ps |
| CPU time | 96.94 seconds |
| Started | Feb 08 09:15:30 AM UTC 25 |
| Finished | Feb 08 09:17:09 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877320515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2877320515 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.894186137 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 190430110948 ps |
| CPU time | 303.96 seconds |
| Started | Feb 08 09:19:29 AM UTC 25 |
| Finished | Feb 08 09:24:37 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894186137 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.894186137 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.3076784470 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2716662738667 ps |
| CPU time | 1840.45 seconds |
| Started | Feb 08 09:24:29 AM UTC 25 |
| Finished | Feb 08 09:55:30 AM UTC 25 |
| Peak memory | 202232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076784470 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3076784470 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1118125631 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1721737196369 ps |
| CPU time | 2993.72 seconds |
| Started | Feb 08 09:32:46 AM UTC 25 |
| Finished | Feb 08 10:23:11 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118125631 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1118125631 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.3573704117 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 32100920761 ps |
| CPU time | 66.96 seconds |
| Started | Feb 08 09:29:18 AM UTC 25 |
| Finished | Feb 08 09:30:27 AM UTC 25 |
| Peak memory | 199356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573704117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3573704117 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.3021787738 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 534240618570 ps |
| CPU time | 1906.37 seconds |
| Started | Feb 08 09:33:31 AM UTC 25 |
| Finished | Feb 08 10:05:38 AM UTC 25 |
| Peak memory | 202044 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021787738 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.3021787738 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.1701145087 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 400836129976 ps |
| CPU time | 615.93 seconds |
| Started | Feb 08 09:29:09 AM UTC 25 |
| Finished | Feb 08 09:39:33 AM UTC 25 |
| Peak memory | 199280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701145087 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.1701145087 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.3075039199 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 279888220826 ps |
| CPU time | 681.23 seconds |
| Started | Feb 08 09:54:53 AM UTC 25 |
| Finished | Feb 08 10:06:23 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075039199 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3075039199 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.32701539 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 166139465019 ps |
| CPU time | 394.91 seconds |
| Started | Feb 08 10:01:33 AM UTC 25 |
| Finished | Feb 08 10:08:13 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32701539 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.32701539 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.412845919 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 161180971985 ps |
| CPU time | 443.58 seconds |
| Started | Feb 08 10:01:43 AM UTC 25 |
| Finished | Feb 08 10:09:13 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412845919 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.412845919 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.3427133759 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 633624736690 ps |
| CPU time | 2721.7 seconds |
| Started | Feb 08 09:24:14 AM UTC 25 |
| Finished | Feb 08 10:10:04 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427133759 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3427133759 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.3503848252 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 602321867857 ps |
| CPU time | 436.52 seconds |
| Started | Feb 08 09:50:12 AM UTC 25 |
| Finished | Feb 08 09:57:34 AM UTC 25 |
| Peak memory | 199428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503848252 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3503848252 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3630526839 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 594814244578 ps |
| CPU time | 493.94 seconds |
| Started | Feb 08 09:50:46 AM UTC 25 |
| Finished | Feb 08 09:59:07 AM UTC 25 |
| Peak memory | 199428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630526839 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3630526839 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.877749558 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 580822561678 ps |
| CPU time | 738.68 seconds |
| Started | Feb 08 09:55:02 AM UTC 25 |
| Finished | Feb 08 10:07:31 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877749558 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.877749558 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.2027185115 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 455765589296 ps |
| CPU time | 364.76 seconds |
| Started | Feb 08 09:55:48 AM UTC 25 |
| Finished | Feb 08 10:01:58 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027185115 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2027185115 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.3863743495 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 166051512407 ps |
| CPU time | 670.5 seconds |
| Started | Feb 08 10:00:59 AM UTC 25 |
| Finished | Feb 08 10:12:18 AM UTC 25 |
| Peak memory | 201984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863743495 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3863743495 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3875576009 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 464910233092 ps |
| CPU time | 244.16 seconds |
| Started | Feb 08 10:01:55 AM UTC 25 |
| Finished | Feb 08 10:06:04 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875576009 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3875576009 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.3082922607 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 3726488307377 ps |
| CPU time | 1180.51 seconds |
| Started | Feb 08 09:23:25 AM UTC 25 |
| Finished | Feb 08 09:43:18 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082922607 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.3082922607 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.880833308 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1818202417797 ps |
| CPU time | 700.71 seconds |
| Started | Feb 08 09:15:24 AM UTC 25 |
| Finished | Feb 08 09:27:13 AM UTC 25 |
| Peak memory | 202056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880833308 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.880833308 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.3727672420 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2147192455997 ps |
| CPU time | 3787.53 seconds |
| Started | Feb 08 09:34:24 AM UTC 25 |
| Finished | Feb 08 10:38:13 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727672420 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.3727672420 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3810929311 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 227726327152 ps |
| CPU time | 179.14 seconds |
| Started | Feb 08 09:36:57 AM UTC 25 |
| Finished | Feb 08 09:39:59 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810929311 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3810929311 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.3657116099 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 272163688381 ps |
| CPU time | 409.83 seconds |
| Started | Feb 08 09:38:57 AM UTC 25 |
| Finished | Feb 08 09:45:52 AM UTC 25 |
| Peak memory | 199412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657116099 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3657116099 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.2777879706 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 752604440163 ps |
| CPU time | 2046.79 seconds |
| Started | Feb 08 09:48:54 AM UTC 25 |
| Finished | Feb 08 10:23:25 AM UTC 25 |
| Peak memory | 202232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777879706 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2777879706 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/99.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.701678920 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 288112080939 ps |
| CPU time | 482.49 seconds |
| Started | Feb 08 09:59:23 AM UTC 25 |
| Finished | Feb 08 10:07:32 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701678920 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.701678920 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.888209348 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 155938130473 ps |
| CPU time | 692.87 seconds |
| Started | Feb 08 09:26:54 AM UTC 25 |
| Finished | Feb 08 09:38:35 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888209348 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.888209348 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.933897455 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 556748455578 ps |
| CPU time | 436.73 seconds |
| Started | Feb 08 09:39:23 AM UTC 25 |
| Finished | Feb 08 09:46:46 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933897455 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.933897455 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.127464222 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 633475343056 ps |
| CPU time | 416.45 seconds |
| Started | Feb 08 09:53:14 AM UTC 25 |
| Finished | Feb 08 10:00:16 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127464222 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.127464222 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.1891615317 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 477446058262 ps |
| CPU time | 439.91 seconds |
| Started | Feb 08 09:55:14 AM UTC 25 |
| Finished | Feb 08 10:02:40 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891615317 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1891615317 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.3826790988 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 391764372685 ps |
| CPU time | 656.63 seconds |
| Started | Feb 08 09:55:50 AM UTC 25 |
| Finished | Feb 08 10:06:56 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826790988 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3826790988 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.85209096 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 842797702439 ps |
| CPU time | 576.04 seconds |
| Started | Feb 08 09:22:51 AM UTC 25 |
| Finished | Feb 08 09:32:35 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85209096 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.85209096 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.2434659095 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1275341392080 ps |
| CPU time | 773.77 seconds |
| Started | Feb 08 09:27:01 AM UTC 25 |
| Finished | Feb 08 09:40:04 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434659095 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2434659095 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.4065495504 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 302887498918 ps |
| CPU time | 209.14 seconds |
| Started | Feb 08 09:35:23 AM UTC 25 |
| Finished | Feb 08 09:38:56 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065495504 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4065495504 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.1231688908 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 227592350990 ps |
| CPU time | 1100.54 seconds |
| Started | Feb 08 09:38:56 AM UTC 25 |
| Finished | Feb 08 09:57:29 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231688908 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.1231688908 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.1778696784 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 142518753173 ps |
| CPU time | 256.69 seconds |
| Started | Feb 08 09:45:52 AM UTC 25 |
| Finished | Feb 08 09:50:12 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778696784 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1778696784 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3220560161 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 26469856 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 09:14:33 AM UTC 25 |
| Finished | Feb 08 09:14:36 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220560161 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.3220560161 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.4044692917 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 40107906 ps |
| CPU time | 0.69 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:11 AM UTC 25 |
| Peak memory | 198868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044692917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4044692917 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.544119808 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 61728872256 ps |
| CPU time | 134.09 seconds |
| Started | Feb 08 09:17:10 AM UTC 25 |
| Finished | Feb 08 09:19:27 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544119808 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.544119808 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.2401745396 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 113028750720 ps |
| CPU time | 53.14 seconds |
| Started | Feb 08 09:50:52 AM UTC 25 |
| Finished | Feb 08 09:51:48 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401745396 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2401745396 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.4183144754 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 111099024976 ps |
| CPU time | 125.28 seconds |
| Started | Feb 08 09:52:11 AM UTC 25 |
| Finished | Feb 08 09:54:19 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183144754 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4183144754 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.556503581 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 737841655408 ps |
| CPU time | 579.59 seconds |
| Started | Feb 08 09:52:25 AM UTC 25 |
| Finished | Feb 08 10:02:13 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556503581 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.556503581 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.3628121146 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 23109525394 ps |
| CPU time | 60.09 seconds |
| Started | Feb 08 09:52:45 AM UTC 25 |
| Finished | Feb 08 09:53:47 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628121146 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3628121146 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.1574077625 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 76849346646 ps |
| CPU time | 494.81 seconds |
| Started | Feb 08 09:54:11 AM UTC 25 |
| Finished | Feb 08 10:02:32 AM UTC 25 |
| Peak memory | 199364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574077625 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1574077625 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.2979435991 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 118420188739 ps |
| CPU time | 248.18 seconds |
| Started | Feb 08 09:58:02 AM UTC 25 |
| Finished | Feb 08 10:02:14 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979435991 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2979435991 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.3157673165 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 106208908196 ps |
| CPU time | 310.32 seconds |
| Started | Feb 08 09:59:50 AM UTC 25 |
| Finished | Feb 08 10:05:05 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157673165 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3157673165 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.3405329199 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 187765176988 ps |
| CPU time | 674.45 seconds |
| Started | Feb 08 10:00:29 AM UTC 25 |
| Finished | Feb 08 10:11:54 AM UTC 25 |
| Peak memory | 201748 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405329199 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3405329199 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.2517998421 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1510749993506 ps |
| CPU time | 487.64 seconds |
| Started | Feb 08 09:22:12 AM UTC 25 |
| Finished | Feb 08 09:30:26 AM UTC 25 |
| Peak memory | 199484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517998421 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2517998421 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.2609866914 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 561894168495 ps |
| CPU time | 577.81 seconds |
| Started | Feb 08 09:24:38 AM UTC 25 |
| Finished | Feb 08 09:34:23 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609866914 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2609866914 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.3049070418 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 434606723006 ps |
| CPU time | 1074.08 seconds |
| Started | Feb 08 09:15:25 AM UTC 25 |
| Finished | Feb 08 09:33:30 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049070418 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.3049070418 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.2187988575 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 45627366246 ps |
| CPU time | 75.78 seconds |
| Started | Feb 08 09:28:32 AM UTC 25 |
| Finished | Feb 08 09:29:49 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187988575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2187988575 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1993765912 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 509114864606 ps |
| CPU time | 544.4 seconds |
| Started | Feb 08 09:29:47 AM UTC 25 |
| Finished | Feb 08 09:38:58 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993765912 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1993765912 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2593263946 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 137084417687 ps |
| CPU time | 412.87 seconds |
| Started | Feb 08 09:39:44 AM UTC 25 |
| Finished | Feb 08 09:46:43 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593263946 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2593263946 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1005895598 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 454122556586 ps |
| CPU time | 392.08 seconds |
| Started | Feb 08 09:44:08 AM UTC 25 |
| Finished | Feb 08 09:50:46 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005895598 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1005895598 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.3472719189 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 328541256696 ps |
| CPU time | 357.85 seconds |
| Started | Feb 08 09:46:21 AM UTC 25 |
| Finished | Feb 08 09:52:24 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472719189 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3472719189 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.733942777 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 61143168414 ps |
| CPU time | 214.95 seconds |
| Started | Feb 08 09:46:44 AM UTC 25 |
| Finished | Feb 08 09:50:22 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733942777 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.733942777 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1127488666 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 850231363 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 09:15:01 AM UTC 25 |
| Finished | Feb 08 09:15:05 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127488666 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.1127488666 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2495319944 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 230709449685 ps |
| CPU time | 249.41 seconds |
| Started | Feb 08 09:48:55 AM UTC 25 |
| Finished | Feb 08 09:53:08 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495319944 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2495319944 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.4011447421 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 242013461369 ps |
| CPU time | 1553.43 seconds |
| Started | Feb 08 09:49:30 AM UTC 25 |
| Finished | Feb 08 10:15:41 AM UTC 25 |
| Peak memory | 201976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011447421 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4011447421 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.1659218186 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 382719036049 ps |
| CPU time | 345.26 seconds |
| Started | Feb 08 09:50:00 AM UTC 25 |
| Finished | Feb 08 09:55:49 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659218186 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1659218186 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.2154140809 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 307396341889 ps |
| CPU time | 670.1 seconds |
| Started | Feb 08 09:17:51 AM UTC 25 |
| Finished | Feb 08 09:29:09 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154140809 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.2154140809 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.237408903 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 531683388292 ps |
| CPU time | 875.39 seconds |
| Started | Feb 08 09:50:22 AM UTC 25 |
| Finished | Feb 08 10:05:07 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237408903 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.237408903 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.905488593 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 221706778300 ps |
| CPU time | 577.5 seconds |
| Started | Feb 08 09:50:28 AM UTC 25 |
| Finished | Feb 08 10:00:13 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905488593 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.905488593 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.2618486032 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 208835753040 ps |
| CPU time | 215.12 seconds |
| Started | Feb 08 09:51:34 AM UTC 25 |
| Finished | Feb 08 09:55:12 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618486032 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2618486032 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.2893575938 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 139782796543 ps |
| CPU time | 300.9 seconds |
| Started | Feb 08 09:18:31 AM UTC 25 |
| Finished | Feb 08 09:23:36 AM UTC 25 |
| Peak memory | 199196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893575938 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.2893575938 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.1820822499 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 34339806448 ps |
| CPU time | 75.77 seconds |
| Started | Feb 08 09:54:28 AM UTC 25 |
| Finished | Feb 08 09:55:46 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820822499 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1820822499 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.1513821713 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 563130513788 ps |
| CPU time | 553.08 seconds |
| Started | Feb 08 09:55:06 AM UTC 25 |
| Finished | Feb 08 10:04:26 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513821713 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1513821713 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.2562478417 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 55253124620 ps |
| CPU time | 1262.59 seconds |
| Started | Feb 08 09:56:53 AM UTC 25 |
| Finished | Feb 08 10:18:10 AM UTC 25 |
| Peak memory | 202240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562478417 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2562478417 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.2631475026 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 162318076070 ps |
| CPU time | 86.29 seconds |
| Started | Feb 08 09:58:21 AM UTC 25 |
| Finished | Feb 08 09:59:50 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631475026 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2631475026 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.3115953053 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 7673334598 ps |
| CPU time | 100.36 seconds |
| Started | Feb 08 09:58:33 AM UTC 25 |
| Finished | Feb 08 10:00:16 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115953053 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3115953053 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.2713476540 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 186270290670 ps |
| CPU time | 121.86 seconds |
| Started | Feb 08 09:59:16 AM UTC 25 |
| Finished | Feb 08 10:01:20 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713476540 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2713476540 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.471840541 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 111079203809 ps |
| CPU time | 261.31 seconds |
| Started | Feb 08 09:59:21 AM UTC 25 |
| Finished | Feb 08 10:03:46 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471840541 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.471840541 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1294499963 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 63353851021 ps |
| CPU time | 122.81 seconds |
| Started | Feb 08 09:21:00 AM UTC 25 |
| Finished | Feb 08 09:23:05 AM UTC 25 |
| Peak memory | 199076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294499963 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1294499963 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.2815567962 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 30330905015 ps |
| CPU time | 232.07 seconds |
| Started | Feb 08 09:21:02 AM UTC 25 |
| Finished | Feb 08 09:24:57 AM UTC 25 |
| Peak memory | 199204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815567962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2815567962 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.1495978947 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 940323865191 ps |
| CPU time | 454.87 seconds |
| Started | Feb 08 09:15:22 AM UTC 25 |
| Finished | Feb 08 09:23:03 AM UTC 25 |
| Peak memory | 199652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495978947 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.1495978947 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.1391304112 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 177503588282 ps |
| CPU time | 270.81 seconds |
| Started | Feb 08 09:26:19 AM UTC 25 |
| Finished | Feb 08 09:30:54 AM UTC 25 |
| Peak memory | 199396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391304112 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1391304112 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.1977829642 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 29947138718 ps |
| CPU time | 45.98 seconds |
| Started | Feb 08 09:27:49 AM UTC 25 |
| Finished | Feb 08 09:28:37 AM UTC 25 |
| Peak memory | 199264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977829642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1977829642 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.1353828632 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 731355082914 ps |
| CPU time | 516.94 seconds |
| Started | Feb 08 09:30:12 AM UTC 25 |
| Finished | Feb 08 09:38:56 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353828632 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1353828632 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.4022977571 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 110057530465 ps |
| CPU time | 311.18 seconds |
| Started | Feb 08 09:34:06 AM UTC 25 |
| Finished | Feb 08 09:39:23 AM UTC 25 |
| Peak memory | 199196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022977571 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.4022977571 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.2490738708 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1558419817241 ps |
| CPU time | 1053.34 seconds |
| Started | Feb 08 09:38:58 AM UTC 25 |
| Finished | Feb 08 09:56:43 AM UTC 25 |
| Peak memory | 201980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490738708 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2490738708 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1000786259 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 155142782261 ps |
| CPU time | 126.3 seconds |
| Started | Feb 08 09:42:35 AM UTC 25 |
| Finished | Feb 08 09:44:44 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000786259 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1000786259 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.1524253352 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 40975305805 ps |
| CPU time | 155.75 seconds |
| Started | Feb 08 09:43:39 AM UTC 25 |
| Finished | Feb 08 09:46:18 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524253352 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1524253352 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.3077883261 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 657416755667 ps |
| CPU time | 2495.19 seconds |
| Started | Feb 08 09:16:22 AM UTC 25 |
| Finished | Feb 08 09:58:24 AM UTC 25 |
| Peak memory | 202036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077883261 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.3077883261 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.3637785440 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 93432951105 ps |
| CPU time | 273.57 seconds |
| Started | Feb 08 09:45:05 AM UTC 25 |
| Finished | Feb 08 09:49:42 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637785440 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3637785440 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2127750832 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 240758555 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 09:14:32 AM UTC 25 |
| Finished | Feb 08 09:14:35 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127750832 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.2127750832 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2700911381 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 100572580 ps |
| CPU time | 2.27 seconds |
| Started | Feb 08 09:14:32 AM UTC 25 |
| Finished | Feb 08 09:14:36 AM UTC 25 |
| Peak memory | 200648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700911381 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.2700911381 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.653603852 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 44311239 ps |
| CPU time | 0.85 seconds |
| Started | Feb 08 09:14:30 AM UTC 25 |
| Finished | Feb 08 09:14:32 AM UTC 25 |
| Peak memory | 198860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653603852 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.653603852 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2651529872 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 15945551 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 09:14:33 AM UTC 25 |
| Finished | Feb 08 09:14:36 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26515 29872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_res et.2651529872 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.1676045219 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12545440 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 09:14:31 AM UTC 25 |
| Finished | Feb 08 09:14:33 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676045219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1676045219 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.3865676593 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 14428573 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 09:14:30 AM UTC 25 |
| Finished | Feb 08 09:14:32 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865676593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3865676593 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.1045465891 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 145277704 ps |
| CPU time | 2.8 seconds |
| Started | Feb 08 09:14:26 AM UTC 25 |
| Finished | Feb 08 09:14:31 AM UTC 25 |
| Peak memory | 200740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045465891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1045465891 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1023579301 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 91440294 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 09:14:26 AM UTC 25 |
| Finished | Feb 08 09:14:30 AM UTC 25 |
| Peak memory | 200116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023579301 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.1023579301 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.691151165 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 138914873 ps |
| CPU time | 0.78 seconds |
| Started | Feb 08 09:14:39 AM UTC 25 |
| Finished | Feb 08 09:14:41 AM UTC 25 |
| Peak memory | 199052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691151165 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.691151165 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2636604625 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 284810694 ps |
| CPU time | 4.92 seconds |
| Started | Feb 08 09:14:39 AM UTC 25 |
| Finished | Feb 08 09:14:45 AM UTC 25 |
| Peak memory | 200756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636604625 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.2636604625 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1145009624 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 70016005 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 09:14:41 AM UTC 25 |
| Finished | Feb 08 09:14:44 AM UTC 25 |
| Peak memory | 198956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11450 09624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_res et.1145009624 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1564191430 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 12058459 ps |
| CPU time | 0.85 seconds |
| Started | Feb 08 09:14:37 AM UTC 25 |
| Finished | Feb 08 09:14:39 AM UTC 25 |
| Peak memory | 198868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564191430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1564191430 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.1962985551 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 14492137 ps |
| CPU time | 0.8 seconds |
| Started | Feb 08 09:14:37 AM UTC 25 |
| Finished | Feb 08 09:14:39 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962985551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1962985551 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3813894016 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 38884271 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 09:14:39 AM UTC 25 |
| Finished | Feb 08 09:14:42 AM UTC 25 |
| Peak memory | 199180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813894016 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.3813894016 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.876093461 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 87585510 ps |
| CPU time | 2.62 seconds |
| Started | Feb 08 09:14:34 AM UTC 25 |
| Finished | Feb 08 09:14:39 AM UTC 25 |
| Peak memory | 201072 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876093461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.876093461 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3712494273 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 334169843 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 09:14:35 AM UTC 25 |
| Finished | Feb 08 09:14:38 AM UTC 25 |
| Peak memory | 198924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712494273 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.3712494273 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.748385323 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 47444404 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 09:15:01 AM UTC 25 |
| Finished | Feb 08 09:15:04 AM UTC 25 |
| Peak memory | 198812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74838 5323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.748385323 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.2322304116 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 14472474 ps |
| CPU time | 0.8 seconds |
| Started | Feb 08 09:15:01 AM UTC 25 |
| Finished | Feb 08 09:15:04 AM UTC 25 |
| Peak memory | 198868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322304116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2322304116 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.587148704 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 16777077 ps |
| CPU time | 0.75 seconds |
| Started | Feb 08 09:15:01 AM UTC 25 |
| Finished | Feb 08 09:15:04 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587148704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.587148704 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4036806065 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 139201470 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 09:15:01 AM UTC 25 |
| Finished | Feb 08 09:15:04 AM UTC 25 |
| Peak memory | 198800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036806065 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.4036806065 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3690367957 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 155626637 ps |
| CPU time | 1.5 seconds |
| Started | Feb 08 09:15:01 AM UTC 25 |
| Finished | Feb 08 09:15:05 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690367957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3690367957 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1146425048 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 121061432 ps |
| CPU time | 0.8 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 199008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11464 25048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_re set.1146425048 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.288895762 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 13755249 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 199056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288895762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_t est +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.288895762 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.69395507 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 22553071 ps |
| CPU time | 0.74 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69395507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.69395507 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1348286544 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 56366571 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 198800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348286544 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.1348286544 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.3508591057 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 141872850 ps |
| CPU time | 2 seconds |
| Started | Feb 08 09:15:02 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508591057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3508591057 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4257305762 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 117736742 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257305762 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.4257305762 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3566260297 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 309306066 ps |
| CPU time | 1.08 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:07 AM UTC 25 |
| Peak memory | 199008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35662 60297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_re set.3566260297 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.4182541921 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 10490934 ps |
| CPU time | 0.59 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182541921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4182541921 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.72692418 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 47937952 ps |
| CPU time | 0.82 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:06 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72692418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.72692418 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.890559904 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 65980039 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:07 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890559904 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.890559904 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3518955083 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 77799194 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:07 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518955083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3518955083 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2111068518 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 414198653 ps |
| CPU time | 1.67 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:07 AM UTC 25 |
| Peak memory | 198804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111068518 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.2111068518 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.788570966 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 219571350 ps |
| CPU time | 2.1 seconds |
| Started | Feb 08 09:15:05 AM UTC 25 |
| Finished | Feb 08 09:15:10 AM UTC 25 |
| Peak memory | 203092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78857 0966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.788570966 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.336639722 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 13759539 ps |
| CPU time | 0.7 seconds |
| Started | Feb 08 09:15:05 AM UTC 25 |
| Finished | Feb 08 09:15:08 AM UTC 25 |
| Peak memory | 199056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336639722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_t est +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.336639722 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1621328030 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 95637553 ps |
| CPU time | 0.77 seconds |
| Started | Feb 08 09:15:05 AM UTC 25 |
| Finished | Feb 08 09:15:08 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621328030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1621328030 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2452304416 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 71987424 ps |
| CPU time | 0.7 seconds |
| Started | Feb 08 09:15:05 AM UTC 25 |
| Finished | Feb 08 09:15:08 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452304416 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.2452304416 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3587401196 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 55585251 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 09:15:04 AM UTC 25 |
| Finished | Feb 08 09:15:07 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587401196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3587401196 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.167656699 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 80807654 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 09:15:05 AM UTC 25 |
| Finished | Feb 08 09:15:09 AM UTC 25 |
| Peak memory | 198924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167656699 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.167656699 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1944889322 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 164527153 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 09:15:07 AM UTC 25 |
| Finished | Feb 08 09:15:10 AM UTC 25 |
| Peak memory | 198816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19448 89322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_re set.1944889322 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3811902479 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 126671511 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 09:15:07 AM UTC 25 |
| Finished | Feb 08 09:15:10 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811902479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3811902479 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1348822537 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 110716025 ps |
| CPU time | 0.7 seconds |
| Started | Feb 08 09:15:06 AM UTC 25 |
| Finished | Feb 08 09:15:09 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348822537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1348822537 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3662634843 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 30429919 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 09:15:07 AM UTC 25 |
| Finished | Feb 08 09:15:10 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662634843 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.3662634843 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3259820031 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 470583109 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 09:15:06 AM UTC 25 |
| Finished | Feb 08 09:15:08 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259820031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3259820031 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1478292250 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 106681815 ps |
| CPU time | 1.1 seconds |
| Started | Feb 08 09:15:06 AM UTC 25 |
| Finished | Feb 08 09:15:09 AM UTC 25 |
| Peak memory | 198804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478292250 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.1478292250 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.723185074 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 137583729 ps |
| CPU time | 0.91 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:11 AM UTC 25 |
| Peak memory | 198828 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72318 5074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.723185074 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.1421753914 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 14674807 ps |
| CPU time | 0.62 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:10 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421753914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1421753914 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2304040139 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 24105592 ps |
| CPU time | 0.69 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:10 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304040139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2304040139 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.263354542 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 73858755 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:11 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263354542 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.263354542 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.972304115 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 50086055 ps |
| CPU time | 1.14 seconds |
| Started | Feb 08 09:15:07 AM UTC 25 |
| Finished | Feb 08 09:15:10 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972304115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.972304115 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3499226 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 693487607 ps |
| CPU time | 1.18 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:11 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499226 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3499226 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.624066573 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 24014655 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 09:15:10 AM UTC 25 |
| Finished | Feb 08 09:15:13 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62406 6573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.624066573 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.3253758813 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 33664795 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:11 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253758813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3253758813 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.832446948 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 107107866 ps |
| CPU time | 0.97 seconds |
| Started | Feb 08 09:15:10 AM UTC 25 |
| Finished | Feb 08 09:15:13 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832446948 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.832446948 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.285239759 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 72724551 ps |
| CPU time | 1.78 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:12 AM UTC 25 |
| Peak memory | 198804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285239759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.285239759 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4098412456 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 846396400 ps |
| CPU time | 1.55 seconds |
| Started | Feb 08 09:15:08 AM UTC 25 |
| Finished | Feb 08 09:15:11 AM UTC 25 |
| Peak memory | 198804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098412456 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.4098412456 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.721018936 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 102592964 ps |
| CPU time | 1.34 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:14 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72101 8936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.721018936 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2253443215 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 14028916 ps |
| CPU time | 0.62 seconds |
| Started | Feb 08 09:15:10 AM UTC 25 |
| Finished | Feb 08 09:15:12 AM UTC 25 |
| Peak memory | 198816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253443215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2253443215 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.846285654 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 20971674 ps |
| CPU time | 0.76 seconds |
| Started | Feb 08 09:15:10 AM UTC 25 |
| Finished | Feb 08 09:15:13 AM UTC 25 |
| Peak memory | 198940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846285654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.846285654 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4068343461 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 67826890 ps |
| CPU time | 0.66 seconds |
| Started | Feb 08 09:15:10 AM UTC 25 |
| Finished | Feb 08 09:15:12 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068343461 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.4068343461 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2496169579 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 95972098 ps |
| CPU time | 2.5 seconds |
| Started | Feb 08 09:15:10 AM UTC 25 |
| Finished | Feb 08 09:15:14 AM UTC 25 |
| Peak memory | 201092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496169579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2496169579 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3883845334 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 121090699 ps |
| CPU time | 1.39 seconds |
| Started | Feb 08 09:15:10 AM UTC 25 |
| Finished | Feb 08 09:15:13 AM UTC 25 |
| Peak memory | 198804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883845334 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.3883845334 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3723958919 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 45160934 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:14 AM UTC 25 |
| Peak memory | 199008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37239 58919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_re set.3723958919 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.2369732569 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 16786589 ps |
| CPU time | 0.72 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:14 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369732569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2369732569 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2813517549 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 46601978 ps |
| CPU time | 0.58 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:14 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813517549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2813517549 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1229959336 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 33891167 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:14 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229959336 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.1229959336 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1188410214 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 910822212 ps |
| CPU time | 1.58 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188410214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1188410214 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.752187297 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 348469305 ps |
| CPU time | 1.35 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:14 AM UTC 25 |
| Peak memory | 199116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752187297 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.752187297 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.745953422 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 55135793 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 09:15:12 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74595 3422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.745953422 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2205410606 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 15948936 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 09:15:12 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205410606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2205410606 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1465757348 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 51719897 ps |
| CPU time | 0.6 seconds |
| Started | Feb 08 09:15:12 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465757348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1465757348 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1344282182 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 16990344 ps |
| CPU time | 0.93 seconds |
| Started | Feb 08 09:15:12 AM UTC 25 |
| Finished | Feb 08 09:15:16 AM UTC 25 |
| Peak memory | 199176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344282182 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.1344282182 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1780613999 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 22337733 ps |
| CPU time | 1.04 seconds |
| Started | Feb 08 09:15:11 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 200912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780613999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1780613999 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.888811178 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 72175456 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 09:15:12 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 199116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888811178 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.888811178 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3505095459 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 21012645 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 09:14:43 AM UTC 25 |
| Finished | Feb 08 09:14:46 AM UTC 25 |
| Peak memory | 199056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505095459 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.3505095459 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3920014134 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 198811887 ps |
| CPU time | 2.15 seconds |
| Started | Feb 08 09:14:43 AM UTC 25 |
| Finished | Feb 08 09:14:47 AM UTC 25 |
| Peak memory | 200732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920014134 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.3920014134 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3605828898 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 27914469 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 09:14:41 AM UTC 25 |
| Finished | Feb 08 09:14:44 AM UTC 25 |
| Peak memory | 199056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605828898 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.3605828898 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3586497436 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 68261385 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 09:14:44 AM UTC 25 |
| Finished | Feb 08 09:14:48 AM UTC 25 |
| Peak memory | 198812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35864 97436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_res et.3586497436 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.685227705 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 15418385 ps |
| CPU time | 0.85 seconds |
| Started | Feb 08 09:14:43 AM UTC 25 |
| Finished | Feb 08 09:14:46 AM UTC 25 |
| Peak memory | 198844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685227705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_t est +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.685227705 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2816069276 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 19741395 ps |
| CPU time | 0.82 seconds |
| Started | Feb 08 09:14:41 AM UTC 25 |
| Finished | Feb 08 09:14:44 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816069276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2816069276 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.491539633 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 52514068 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 09:14:43 AM UTC 25 |
| Finished | Feb 08 09:14:46 AM UTC 25 |
| Peak memory | 199184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491539633 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.491539633 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.2072909016 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 37711734 ps |
| CPU time | 1.38 seconds |
| Started | Feb 08 09:14:41 AM UTC 25 |
| Finished | Feb 08 09:14:44 AM UTC 25 |
| Peak memory | 198804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072909016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2072909016 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.1367407706 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 11293588 ps |
| CPU time | 0.62 seconds |
| Started | Feb 08 09:15:12 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367407706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1367407706 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1727210330 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 11217924 ps |
| CPU time | 0.76 seconds |
| Started | Feb 08 09:15:12 AM UTC 25 |
| Finished | Feb 08 09:15:15 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727210330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1727210330 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2486040094 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 46698096 ps |
| CPU time | 0.75 seconds |
| Started | Feb 08 09:15:13 AM UTC 25 |
| Finished | Feb 08 09:15:16 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486040094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2486040094 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.3519129241 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 49901251 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 09:15:13 AM UTC 25 |
| Finished | Feb 08 09:15:16 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519129241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3519129241 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.3351965120 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 12379028 ps |
| CPU time | 0.78 seconds |
| Started | Feb 08 09:15:13 AM UTC 25 |
| Finished | Feb 08 09:15:16 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351965120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3351965120 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3340157255 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 14683831 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 09:15:13 AM UTC 25 |
| Finished | Feb 08 09:15:16 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340157255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3340157255 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2894487666 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 14695423 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 09:15:13 AM UTC 25 |
| Finished | Feb 08 09:15:16 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894487666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2894487666 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.3916490371 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 15743361 ps |
| CPU time | 0.69 seconds |
| Started | Feb 08 09:15:15 AM UTC 25 |
| Finished | Feb 08 09:15:17 AM UTC 25 |
| Peak memory | 198672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916490371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3916490371 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.3746991874 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 25480780 ps |
| CPU time | 0.69 seconds |
| Started | Feb 08 09:15:15 AM UTC 25 |
| Finished | Feb 08 09:15:17 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746991874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3746991874 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3643589120 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 11235540 ps |
| CPU time | 0.58 seconds |
| Started | Feb 08 09:15:15 AM UTC 25 |
| Finished | Feb 08 09:15:17 AM UTC 25 |
| Peak memory | 198868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643589120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3643589120 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3909249606 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 20385676 ps |
| CPU time | 0.78 seconds |
| Started | Feb 08 09:14:47 AM UTC 25 |
| Finished | Feb 08 09:14:50 AM UTC 25 |
| Peak memory | 199056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909249606 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.3909249606 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1597878962 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 68882653 ps |
| CPU time | 1.65 seconds |
| Started | Feb 08 09:14:47 AM UTC 25 |
| Finished | Feb 08 09:14:50 AM UTC 25 |
| Peak memory | 199056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597878962 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.1597878962 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2057450490 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 74373920 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 09:14:47 AM UTC 25 |
| Finished | Feb 08 09:14:50 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057450490 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2057450490 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.421576295 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 289114332 ps |
| CPU time | 2.29 seconds |
| Started | Feb 08 09:14:49 AM UTC 25 |
| Finished | Feb 08 09:14:53 AM UTC 25 |
| Peak memory | 200916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42157 6295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.421576295 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.257049322 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 32973165 ps |
| CPU time | 0.81 seconds |
| Started | Feb 08 09:14:47 AM UTC 25 |
| Finished | Feb 08 09:14:49 AM UTC 25 |
| Peak memory | 199052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257049322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_t est +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.257049322 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3533629483 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 32915173 ps |
| CPU time | 0.78 seconds |
| Started | Feb 08 09:14:46 AM UTC 25 |
| Finished | Feb 08 09:14:48 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533629483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3533629483 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.416765590 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 58389424 ps |
| CPU time | 0.87 seconds |
| Started | Feb 08 09:14:47 AM UTC 25 |
| Finished | Feb 08 09:14:50 AM UTC 25 |
| Peak memory | 199184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416765590 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.416765590 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.2993416904 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 316026220 ps |
| CPU time | 2.31 seconds |
| Started | Feb 08 09:14:46 AM UTC 25 |
| Finished | Feb 08 09:14:50 AM UTC 25 |
| Peak memory | 200968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993416904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2993416904 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2489457387 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 72816994 ps |
| CPU time | 1.66 seconds |
| Started | Feb 08 09:14:46 AM UTC 25 |
| Finished | Feb 08 09:14:49 AM UTC 25 |
| Peak memory | 198924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489457387 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.2489457387 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1060342618 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 32202087 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 09:15:15 AM UTC 25 |
| Finished | Feb 08 09:15:17 AM UTC 25 |
| Peak memory | 198820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060342618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1060342618 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2805628206 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 21383877 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 09:15:15 AM UTC 25 |
| Finished | Feb 08 09:15:17 AM UTC 25 |
| Peak memory | 198960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805628206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2805628206 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.702555336 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 15218092 ps |
| CPU time | 0.63 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:19 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702555336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.702555336 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.2518945836 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 86782616 ps |
| CPU time | 0.51 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:18 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518945836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2518945836 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.1542526371 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 38670673 ps |
| CPU time | 0.57 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:18 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542526371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1542526371 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.4023468992 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 57153664 ps |
| CPU time | 0.76 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:19 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023468992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.4023468992 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.573097853 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 12560787 ps |
| CPU time | 0.65 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:19 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573097853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.573097853 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1779736712 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 17428405 ps |
| CPU time | 0.81 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:19 AM UTC 25 |
| Peak memory | 198620 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779736712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1779736712 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.211077699 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 22617920 ps |
| CPU time | 0.72 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:19 AM UTC 25 |
| Peak memory | 198636 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211077699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.211077699 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4287303217 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 42117743 ps |
| CPU time | 0.63 seconds |
| Started | Feb 08 09:15:16 AM UTC 25 |
| Finished | Feb 08 09:15:19 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287303217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4287303217 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.75151469 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26861330 ps |
| CPU time | 1 seconds |
| Started | Feb 08 09:14:51 AM UTC 25 |
| Finished | Feb 08 09:14:53 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75151469 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.75151469 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1151304397 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 344011746 ps |
| CPU time | 4.03 seconds |
| Started | Feb 08 09:14:51 AM UTC 25 |
| Finished | Feb 08 09:14:56 AM UTC 25 |
| Peak memory | 201152 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151304397 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.1151304397 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3082584843 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 54781029 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 09:14:49 AM UTC 25 |
| Finished | Feb 08 09:14:52 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082584843 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_time r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.3082584843 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3819930864 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 117185314 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 09:14:51 AM UTC 25 |
| Finished | Feb 08 09:14:54 AM UTC 25 |
| Peak memory | 198812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38199 30864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_res et.3819930864 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.3046828153 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 21560652 ps |
| CPU time | 0.86 seconds |
| Started | Feb 08 09:14:49 AM UTC 25 |
| Finished | Feb 08 09:14:52 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046828153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3046828153 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.31166812 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 20071894 ps |
| CPU time | 0.85 seconds |
| Started | Feb 08 09:14:49 AM UTC 25 |
| Finished | Feb 08 09:14:52 AM UTC 25 |
| Peak memory | 198836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31166812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.31166812 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1274054 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 15075195 ps |
| CPU time | 1.05 seconds |
| Started | Feb 08 09:14:51 AM UTC 25 |
| Finished | Feb 08 09:14:54 AM UTC 25 |
| Peak memory | 199184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274054 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.1274054 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.1018656103 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 192440349 ps |
| CPU time | 2.78 seconds |
| Started | Feb 08 09:14:49 AM UTC 25 |
| Finished | Feb 08 09:14:54 AM UTC 25 |
| Peak memory | 200812 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018656103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1018656103 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.394475948 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 309208839 ps |
| CPU time | 1.21 seconds |
| Started | Feb 08 09:14:49 AM UTC 25 |
| Finished | Feb 08 09:14:52 AM UTC 25 |
| Peak memory | 198784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394475948 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.394475948 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2031670465 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 38199452 ps |
| CPU time | 0.69 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:20 AM UTC 25 |
| Peak memory | 198984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031670465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2031670465 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.990120832 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 32309881 ps |
| CPU time | 0.77 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:20 AM UTC 25 |
| Peak memory | 198952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990120832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.990120832 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.3690234029 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 61473802 ps |
| CPU time | 0.58 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:20 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690234029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3690234029 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1041634403 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 78492223 ps |
| CPU time | 0.67 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:20 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041634403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1041634403 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.617675982 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 20508493 ps |
| CPU time | 0.61 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:21 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617675982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.617675982 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.3788293763 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 14934629 ps |
| CPU time | 0.78 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:21 AM UTC 25 |
| Peak memory | 198864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788293763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3788293763 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.53104563 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 11171113 ps |
| CPU time | 0.74 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:20 AM UTC 25 |
| Peak memory | 198952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53104563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.53104563 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.2924030591 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 12273733 ps |
| CPU time | 0.51 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:20 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924030591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2924030591 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.861653 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 20233387 ps |
| CPU time | 0.64 seconds |
| Started | Feb 08 09:15:17 AM UTC 25 |
| Finished | Feb 08 09:15:20 AM UTC 25 |
| Peak memory | 198928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +U VM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.861653 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.1572995519 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 11322615 ps |
| CPU time | 0.71 seconds |
| Started | Feb 08 09:15:18 AM UTC 25 |
| Finished | Feb 08 09:15:21 AM UTC 25 |
| Peak memory | 198992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572995519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1572995519 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1306392627 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 54816475 ps |
| CPU time | 1.15 seconds |
| Started | Feb 08 09:14:53 AM UTC 25 |
| Finished | Feb 08 09:14:56 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13063 92627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_res et.1306392627 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3930790627 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 25169126 ps |
| CPU time | 0.83 seconds |
| Started | Feb 08 09:14:52 AM UTC 25 |
| Finished | Feb 08 09:14:55 AM UTC 25 |
| Peak memory | 199060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930790627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3930790627 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.4130954531 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 22755073 ps |
| CPU time | 0.68 seconds |
| Started | Feb 08 09:14:52 AM UTC 25 |
| Finished | Feb 08 09:14:55 AM UTC 25 |
| Peak memory | 198768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130954531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4130954531 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2714523479 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 36396913 ps |
| CPU time | 1.11 seconds |
| Started | Feb 08 09:14:53 AM UTC 25 |
| Finished | Feb 08 09:14:56 AM UTC 25 |
| Peak memory | 199180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714523479 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.2714523479 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.1018950098 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 201260219 ps |
| CPU time | 1.46 seconds |
| Started | Feb 08 09:14:51 AM UTC 25 |
| Finished | Feb 08 09:14:54 AM UTC 25 |
| Peak memory | 198804 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018950098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1018950098 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.341242565 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 47873031 ps |
| CPU time | 1.24 seconds |
| Started | Feb 08 09:14:52 AM UTC 25 |
| Finished | Feb 08 09:14:55 AM UTC 25 |
| Peak memory | 199116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341242565 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.341242565 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.931226786 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 28616300 ps |
| CPU time | 0.94 seconds |
| Started | Feb 08 09:14:55 AM UTC 25 |
| Finished | Feb 08 09:14:58 AM UTC 25 |
| Peak memory | 199000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93122 6786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.931226786 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.905581153 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 44891640 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 09:14:55 AM UTC 25 |
| Finished | Feb 08 09:14:57 AM UTC 25 |
| Peak memory | 198860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905581153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_t est +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.905581153 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.2288900161 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 20655781 ps |
| CPU time | 0.83 seconds |
| Started | Feb 08 09:14:55 AM UTC 25 |
| Finished | Feb 08 09:14:58 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288900161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2288900161 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.4217002520 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 64399851 ps |
| CPU time | 0.95 seconds |
| Started | Feb 08 09:14:55 AM UTC 25 |
| Finished | Feb 08 09:14:58 AM UTC 25 |
| Peak memory | 199180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217002520 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.4217002520 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.283595655 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 727828451 ps |
| CPU time | 3.3 seconds |
| Started | Feb 08 09:14:53 AM UTC 25 |
| Finished | Feb 08 09:14:59 AM UTC 25 |
| Peak memory | 200816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283595655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.283595655 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1753685335 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 115846965 ps |
| CPU time | 1.73 seconds |
| Started | Feb 08 09:14:53 AM UTC 25 |
| Finished | Feb 08 09:14:57 AM UTC 25 |
| Peak memory | 198924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753685335 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.1753685335 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1780532857 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 73254488 ps |
| CPU time | 0.88 seconds |
| Started | Feb 08 09:14:56 AM UTC 25 |
| Finished | Feb 08 09:14:59 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17805 32857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_res et.1780532857 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.505537906 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 58320377 ps |
| CPU time | 0.74 seconds |
| Started | Feb 08 09:14:56 AM UTC 25 |
| Finished | Feb 08 09:14:59 AM UTC 25 |
| Peak memory | 199052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505537906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_t est +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.505537906 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.824709262 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 16461823 ps |
| CPU time | 0.85 seconds |
| Started | Feb 08 09:14:55 AM UTC 25 |
| Finished | Feb 08 09:14:58 AM UTC 25 |
| Peak memory | 199000 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824709262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.824709262 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1810427228 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 91343527 ps |
| CPU time | 0.92 seconds |
| Started | Feb 08 09:14:56 AM UTC 25 |
| Finished | Feb 08 09:14:59 AM UTC 25 |
| Peak memory | 199180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810427228 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.1810427228 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.665706978 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 280439913 ps |
| CPU time | 3.7 seconds |
| Started | Feb 08 09:14:55 AM UTC 25 |
| Finished | Feb 08 09:15:00 AM UTC 25 |
| Peak memory | 202892 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665706978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.665706978 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.379124746 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1178740898 ps |
| CPU time | 1.62 seconds |
| Started | Feb 08 09:14:55 AM UTC 25 |
| Finished | Feb 08 09:14:59 AM UTC 25 |
| Peak memory | 199116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379124746 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.379124746 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.890569516 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 29529048 ps |
| CPU time | 1.06 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 198928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89056 9516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.890569516 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.4089075132 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 36354607 ps |
| CPU time | 0.78 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 199036 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089075132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4089075132 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2786315457 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 21614215 ps |
| CPU time | 0.72 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 198784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786315457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2786315457 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3060912077 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 16673534 ps |
| CPU time | 0.99 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 199180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060912077 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.3060912077 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.2407784809 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 221336652 ps |
| CPU time | 2.09 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:03 AM UTC 25 |
| Peak memory | 201132 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407784809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2407784809 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.926175026 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 90912534 ps |
| CPU time | 1.22 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 199116 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926175026 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.926175026 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2485846010 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 22459772 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24858 46010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_res et.2485846010 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3665061293 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 15540551 ps |
| CPU time | 0.82 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:03 AM UTC 25 |
| Peak memory | 198868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665061293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_ test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3665061293 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.752722113 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 50217489 ps |
| CPU time | 0.7 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 198936 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752722113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.752722113 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1147977586 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 34969196 ps |
| CPU time | 0.79 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:02 AM UTC 25 |
| Peak memory | 199180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147977586 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.1147977586 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3661986180 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 83705064 ps |
| CPU time | 1.79 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:03 AM UTC 25 |
| Peak memory | 199120 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661986180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_tes t +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3661986180 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2851260707 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 41305031 ps |
| CPU time | 1.23 seconds |
| Started | Feb 08 09:14:59 AM UTC 25 |
| Finished | Feb 08 09:15:03 AM UTC 25 |
| Peak memory | 198924 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851260707 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.2851260707 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.1123230552 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 386689075926 ps |
| CPU time | 286 seconds |
| Started | Feb 08 09:15:18 AM UTC 25 |
| Finished | Feb 08 09:20:09 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123230552 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.1123230552 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.2488306905 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 763813356581 ps |
| CPU time | 206.23 seconds |
| Started | Feb 08 09:15:18 AM UTC 25 |
| Finished | Feb 08 09:18:49 AM UTC 25 |
| Peak memory | 199204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488306905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.rv_timer_disabled.2488306905 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2889264825 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1765490103345 ps |
| CPU time | 377.31 seconds |
| Started | Feb 08 09:15:18 AM UTC 25 |
| Finished | Feb 08 09:21:42 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889264825 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2889264825 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.2715355744 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 76970545 ps |
| CPU time | 0.81 seconds |
| Started | Feb 08 09:15:18 AM UTC 25 |
| Finished | Feb 08 09:15:22 AM UTC 25 |
| Peak memory | 198424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715355744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2715355744 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.3462699690 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 74587717 ps |
| CPU time | 1.07 seconds |
| Started | Feb 08 09:15:20 AM UTC 25 |
| Finished | Feb 08 09:15:23 AM UTC 25 |
| Peak memory | 230236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462699690 -assert nopostproc +UVM_TESTNAME=rv_timer_base _test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3462699690 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.820819933 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 278270861202 ps |
| CPU time | 180.63 seconds |
| Started | Feb 08 09:15:20 AM UTC 25 |
| Finished | Feb 08 09:18:24 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820819933 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.820819933 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.1878267049 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 838442051024 ps |
| CPU time | 218.62 seconds |
| Started | Feb 08 09:15:20 AM UTC 25 |
| Finished | Feb 08 09:19:02 AM UTC 25 |
| Peak memory | 199488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878267049 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.1878267049 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.4052734625 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 104343129109 ps |
| CPU time | 52.47 seconds |
| Started | Feb 08 09:15:20 AM UTC 25 |
| Finished | Feb 08 09:16:15 AM UTC 25 |
| Peak memory | 199048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052734625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.rv_timer_disabled.4052734625 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3851891359 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 410229048 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 09:15:20 AM UTC 25 |
| Finished | Feb 08 09:15:23 AM UTC 25 |
| Peak memory | 198160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851891359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3851891359 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.1092261619 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 64576127 ps |
| CPU time | 0.9 seconds |
| Started | Feb 08 09:15:21 AM UTC 25 |
| Finished | Feb 08 09:15:24 AM UTC 25 |
| Peak memory | 230236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092261619 -assert nopostproc +UVM_TESTNAME=rv_timer_base _test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1092261619 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3881734357 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 131143563516 ps |
| CPU time | 164.72 seconds |
| Started | Feb 08 09:15:21 AM UTC 25 |
| Finished | Feb 08 09:18:09 AM UTC 25 |
| Peak memory | 199240 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881734357 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.3881734357 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.166467064 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 217675820705 ps |
| CPU time | 291.99 seconds |
| Started | Feb 08 09:17:15 AM UTC 25 |
| Finished | Feb 08 09:22:12 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166467064 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.166467064 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.1033077290 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 184626895403 ps |
| CPU time | 371.89 seconds |
| Started | Feb 08 09:17:10 AM UTC 25 |
| Finished | Feb 08 09:23:27 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033077290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.rv_timer_disabled.1033077290 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.1590260069 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 13848330544 ps |
| CPU time | 12.81 seconds |
| Started | Feb 08 09:17:32 AM UTC 25 |
| Finished | Feb 08 09:17:47 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590260069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1590260069 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all_with_rand_reset.650276863 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 73695177024 ps |
| CPU time | 707.93 seconds |
| Started | Feb 08 09:17:39 AM UTC 25 |
| Finished | Feb 08 09:29:37 AM UTC 25 |
| Peak memory | 208280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=650276863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_al l_with_rand_reset.650276863 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.901749189 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1353897172111 ps |
| CPU time | 349.57 seconds |
| Started | Feb 08 09:49:07 AM UTC 25 |
| Finished | Feb 08 09:55:01 AM UTC 25 |
| Peak memory | 199476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901749189 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.901749189 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.2398919296 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 569353012606 ps |
| CPU time | 1725.35 seconds |
| Started | Feb 08 09:49:43 AM UTC 25 |
| Finished | Feb 08 10:18:48 AM UTC 25 |
| Peak memory | 202048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398919296 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2398919296 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.3050037072 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 275435354554 ps |
| CPU time | 345.85 seconds |
| Started | Feb 08 09:49:56 AM UTC 25 |
| Finished | Feb 08 09:55:48 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050037072 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3050037072 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.4036934721 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 278314571513 ps |
| CPU time | 681.61 seconds |
| Started | Feb 08 09:50:13 AM UTC 25 |
| Finished | Feb 08 10:01:42 AM UTC 25 |
| Peak memory | 199536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036934721 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.4036934721 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2065026049 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2120806844 ps |
| CPU time | 2.7 seconds |
| Started | Feb 08 09:50:14 AM UTC 25 |
| Finished | Feb 08 09:50:18 AM UTC 25 |
| Peak memory | 199016 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065026049 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2065026049 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.213123313 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 426293424349 ps |
| CPU time | 595.88 seconds |
| Started | Feb 08 09:50:19 AM UTC 25 |
| Finished | Feb 08 10:00:21 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213123313 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.213123313 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.1501648694 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 37398556520 ps |
| CPU time | 116.01 seconds |
| Started | Feb 08 09:17:47 AM UTC 25 |
| Finished | Feb 08 09:19:46 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501648694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.rv_timer_disabled.1501648694 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.2303687891 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 328503703155 ps |
| CPU time | 951.55 seconds |
| Started | Feb 08 09:17:43 AM UTC 25 |
| Finished | Feb 08 09:33:46 AM UTC 25 |
| Peak memory | 201976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303687891 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2303687891 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.3928376823 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 893692232 ps |
| CPU time | 2.07 seconds |
| Started | Feb 08 09:17:53 AM UTC 25 |
| Finished | Feb 08 09:17:57 AM UTC 25 |
| Peak memory | 199008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928376823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3928376823 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.3434109230 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 841999464734 ps |
| CPU time | 1385.68 seconds |
| Started | Feb 08 09:50:23 AM UTC 25 |
| Finished | Feb 08 10:13:44 AM UTC 25 |
| Peak memory | 201976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434109230 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3434109230 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.674892065 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 807068099319 ps |
| CPU time | 1317.23 seconds |
| Started | Feb 08 09:50:23 AM UTC 25 |
| Finished | Feb 08 10:12:36 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674892065 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.674892065 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.710022837 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 269646024405 ps |
| CPU time | 152.93 seconds |
| Started | Feb 08 09:50:38 AM UTC 25 |
| Finished | Feb 08 09:53:14 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710022837 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.710022837 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.3252895823 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 53416800413 ps |
| CPU time | 97 seconds |
| Started | Feb 08 09:50:44 AM UTC 25 |
| Finished | Feb 08 09:52:24 AM UTC 25 |
| Peak memory | 199080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252895823 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3252895823 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1747810120 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 677727191550 ps |
| CPU time | 656.58 seconds |
| Started | Feb 08 09:51:00 AM UTC 25 |
| Finished | Feb 08 10:02:05 AM UTC 25 |
| Peak memory | 199236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747810120 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1747810120 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1677990882 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 118682661096 ps |
| CPU time | 225.05 seconds |
| Started | Feb 08 09:18:08 AM UTC 25 |
| Finished | Feb 08 09:21:56 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677990882 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1677990882 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.1180848510 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 180824883142 ps |
| CPU time | 282.24 seconds |
| Started | Feb 08 09:18:04 AM UTC 25 |
| Finished | Feb 08 09:22:50 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180848510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.rv_timer_disabled.1180848510 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.2848069591 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 89506603590 ps |
| CPU time | 193.94 seconds |
| Started | Feb 08 09:18:00 AM UTC 25 |
| Finished | Feb 08 09:21:17 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848069591 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2848069591 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.2905056362 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 47565561918 ps |
| CPU time | 94.52 seconds |
| Started | Feb 08 09:18:10 AM UTC 25 |
| Finished | Feb 08 09:19:47 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905056362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2905056362 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.565313747 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 167339916766 ps |
| CPU time | 800.02 seconds |
| Started | Feb 08 09:18:19 AM UTC 25 |
| Finished | Feb 08 09:31:49 AM UTC 25 |
| Peak memory | 199332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565313747 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.565313747 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.2652541058 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 119876515261 ps |
| CPU time | 1270.07 seconds |
| Started | Feb 08 09:51:35 AM UTC 25 |
| Finished | Feb 08 10:12:59 AM UTC 25 |
| Peak memory | 202176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652541058 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2652541058 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3636056027 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 316062073546 ps |
| CPU time | 155.89 seconds |
| Started | Feb 08 09:51:49 AM UTC 25 |
| Finished | Feb 08 09:54:28 AM UTC 25 |
| Peak memory | 199300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636056027 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3636056027 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.1993673872 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 167305174792 ps |
| CPU time | 213 seconds |
| Started | Feb 08 09:52:07 AM UTC 25 |
| Finished | Feb 08 09:55:43 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993673872 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1993673872 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.1385717105 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 193447928957 ps |
| CPU time | 1174.68 seconds |
| Started | Feb 08 09:52:12 AM UTC 25 |
| Finished | Feb 08 10:12:00 AM UTC 25 |
| Peak memory | 201976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385717105 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1385717105 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.2056640050 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 79855500917 ps |
| CPU time | 170.06 seconds |
| Started | Feb 08 09:52:12 AM UTC 25 |
| Finished | Feb 08 09:55:05 AM UTC 25 |
| Peak memory | 199300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056640050 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2056640050 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.3104806906 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 736999059060 ps |
| CPU time | 255.07 seconds |
| Started | Feb 08 09:52:25 AM UTC 25 |
| Finished | Feb 08 09:56:44 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104806906 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3104806906 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.1928677589 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 899699517046 ps |
| CPU time | 470.83 seconds |
| Started | Feb 08 09:52:32 AM UTC 25 |
| Finished | Feb 08 10:00:28 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928677589 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1928677589 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1487097021 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 333589719352 ps |
| CPU time | 351.19 seconds |
| Started | Feb 08 09:52:39 AM UTC 25 |
| Finished | Feb 08 09:58:35 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487097021 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1487097021 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.1335223696 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 86446381691 ps |
| CPU time | 82.07 seconds |
| Started | Feb 08 09:18:25 AM UTC 25 |
| Finished | Feb 08 09:19:50 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335223696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.rv_timer_disabled.1335223696 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.3322177601 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 478864561663 ps |
| CPU time | 416.93 seconds |
| Started | Feb 08 09:18:24 AM UTC 25 |
| Finished | Feb 08 09:25:28 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322177601 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3322177601 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.675673595 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 102651467596 ps |
| CPU time | 304.11 seconds |
| Started | Feb 08 09:18:43 AM UTC 25 |
| Finished | Feb 08 09:23:52 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675673595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.675673595 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.3281140066 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 620226036850 ps |
| CPU time | 333.79 seconds |
| Started | Feb 08 09:18:49 AM UTC 25 |
| Finished | Feb 08 09:24:28 AM UTC 25 |
| Peak memory | 199388 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281140066 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.3281140066 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1078721381 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 133115706214 ps |
| CPU time | 450.79 seconds |
| Started | Feb 08 09:53:09 AM UTC 25 |
| Finished | Feb 08 10:00:45 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078721381 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1078721381 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.1036933588 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 372094822478 ps |
| CPU time | 1217.68 seconds |
| Started | Feb 08 09:53:15 AM UTC 25 |
| Finished | Feb 08 10:13:46 AM UTC 25 |
| Peak memory | 202176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036933588 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1036933588 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.2116169473 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 206413747394 ps |
| CPU time | 823.22 seconds |
| Started | Feb 08 09:53:26 AM UTC 25 |
| Finished | Feb 08 10:07:19 AM UTC 25 |
| Peak memory | 201856 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116169473 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2116169473 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.2325750207 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 372346202471 ps |
| CPU time | 1152.52 seconds |
| Started | Feb 08 09:53:26 AM UTC 25 |
| Finished | Feb 08 10:12:51 AM UTC 25 |
| Peak memory | 202012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325750207 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2325750207 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.2902086404 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 145782434955 ps |
| CPU time | 138.98 seconds |
| Started | Feb 08 09:53:34 AM UTC 25 |
| Finished | Feb 08 09:55:56 AM UTC 25 |
| Peak memory | 199428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902086404 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2902086404 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1370530624 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 163396384407 ps |
| CPU time | 270.48 seconds |
| Started | Feb 08 09:53:39 AM UTC 25 |
| Finished | Feb 08 09:58:13 AM UTC 25 |
| Peak memory | 199232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370530624 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1370530624 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.2760275110 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 220359120115 ps |
| CPU time | 204.78 seconds |
| Started | Feb 08 09:53:48 AM UTC 25 |
| Finished | Feb 08 09:57:16 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760275110 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2760275110 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.1695840463 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 76036608278 ps |
| CPU time | 652.96 seconds |
| Started | Feb 08 09:53:53 AM UTC 25 |
| Finished | Feb 08 10:04:54 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695840463 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1695840463 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.2054812086 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 418966691022 ps |
| CPU time | 349.87 seconds |
| Started | Feb 08 09:19:04 AM UTC 25 |
| Finished | Feb 08 09:24:59 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054812086 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.2054812086 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.2863654824 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 150909942364 ps |
| CPU time | 218 seconds |
| Started | Feb 08 09:19:03 AM UTC 25 |
| Finished | Feb 08 09:22:45 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863654824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.rv_timer_disabled.2863654824 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.240059000 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 40130152399 ps |
| CPU time | 125.73 seconds |
| Started | Feb 08 09:18:50 AM UTC 25 |
| Finished | Feb 08 09:20:59 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240059000 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.240059000 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.2361838259 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 178268802041 ps |
| CPU time | 124.74 seconds |
| Started | Feb 08 09:19:12 AM UTC 25 |
| Finished | Feb 08 09:21:20 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361838259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2361838259 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1526436575 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 147471818678 ps |
| CPU time | 264.18 seconds |
| Started | Feb 08 09:19:29 AM UTC 25 |
| Finished | Feb 08 09:23:57 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526436575 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.1526436575 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.3788108297 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 63414647475 ps |
| CPU time | 246.95 seconds |
| Started | Feb 08 09:54:20 AM UTC 25 |
| Finished | Feb 08 09:58:32 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788108297 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3788108297 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2391387263 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 92050315189 ps |
| CPU time | 279.43 seconds |
| Started | Feb 08 09:55:11 AM UTC 25 |
| Finished | Feb 08 09:59:54 AM UTC 25 |
| Peak memory | 199428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391387263 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2391387263 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.2707414159 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 85374141261 ps |
| CPU time | 577.67 seconds |
| Started | Feb 08 09:55:31 AM UTC 25 |
| Finished | Feb 08 10:05:16 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707414159 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2707414159 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.568992140 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 103789998337 ps |
| CPU time | 213.25 seconds |
| Started | Feb 08 09:55:44 AM UTC 25 |
| Finished | Feb 08 09:59:21 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568992140 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.568992140 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.141536761 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 13563214124 ps |
| CPU time | 26.08 seconds |
| Started | Feb 08 09:19:31 AM UTC 25 |
| Finished | Feb 08 09:19:59 AM UTC 25 |
| Peak memory | 199196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141536761 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.141536761 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.2952821855 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 54462564450 ps |
| CPU time | 129.51 seconds |
| Started | Feb 08 09:19:29 AM UTC 25 |
| Finished | Feb 08 09:21:41 AM UTC 25 |
| Peak memory | 199360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952821855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.rv_timer_disabled.2952821855 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.1511266929 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 31339905174 ps |
| CPU time | 61.93 seconds |
| Started | Feb 08 09:19:38 AM UTC 25 |
| Finished | Feb 08 09:20:42 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511266929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1511266929 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.3704010315 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 266469041087 ps |
| CPU time | 291.8 seconds |
| Started | Feb 08 09:19:47 AM UTC 25 |
| Finished | Feb 08 09:24:44 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704010315 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.3704010315 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.147498207 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 65220348333 ps |
| CPU time | 50.88 seconds |
| Started | Feb 08 09:55:46 AM UTC 25 |
| Finished | Feb 08 09:56:39 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147498207 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.147498207 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.3257085603 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 117081898054 ps |
| CPU time | 307.14 seconds |
| Started | Feb 08 09:55:47 AM UTC 25 |
| Finished | Feb 08 10:00:59 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257085603 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3257085603 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.578204895 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 264556934929 ps |
| CPU time | 462.96 seconds |
| Started | Feb 08 09:55:57 AM UTC 25 |
| Finished | Feb 08 10:03:47 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578204895 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.578204895 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.678432118 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 22508868582 ps |
| CPU time | 504.82 seconds |
| Started | Feb 08 09:56:40 AM UTC 25 |
| Finished | Feb 08 10:05:11 AM UTC 25 |
| Peak memory | 199412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678432118 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.678432118 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.1104771614 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 92308363790 ps |
| CPU time | 988.81 seconds |
| Started | Feb 08 09:56:44 AM UTC 25 |
| Finished | Feb 08 10:13:24 AM UTC 25 |
| Peak memory | 201976 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104771614 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1104771614 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.2585061498 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 169236647244 ps |
| CPU time | 165.02 seconds |
| Started | Feb 08 09:56:45 AM UTC 25 |
| Finished | Feb 08 09:59:33 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585061498 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2585061498 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3072575131 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 570299778367 ps |
| CPU time | 548.17 seconds |
| Started | Feb 08 09:57:16 AM UTC 25 |
| Finished | Feb 08 10:06:31 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072575131 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3072575131 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.2665490053 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 362649088686 ps |
| CPU time | 647.94 seconds |
| Started | Feb 08 09:19:54 AM UTC 25 |
| Finished | Feb 08 09:30:50 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665490053 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.2665490053 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.3859128613 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 414988270949 ps |
| CPU time | 173.35 seconds |
| Started | Feb 08 09:19:50 AM UTC 25 |
| Finished | Feb 08 09:22:47 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859128613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.rv_timer_disabled.3859128613 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.2360574871 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 318968602034 ps |
| CPU time | 309.51 seconds |
| Started | Feb 08 09:19:47 AM UTC 25 |
| Finished | Feb 08 09:25:02 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360574871 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2360574871 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.1957949844 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 77591117331 ps |
| CPU time | 192.25 seconds |
| Started | Feb 08 09:20:00 AM UTC 25 |
| Finished | Feb 08 09:23:16 AM UTC 25 |
| Peak memory | 199324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957949844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1957949844 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.700177082 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 830674568506 ps |
| CPU time | 519.85 seconds |
| Started | Feb 08 09:20:10 AM UTC 25 |
| Finished | Feb 08 09:28:57 AM UTC 25 |
| Peak memory | 199480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700177082 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.700177082 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.184650193 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 167861266408 ps |
| CPU time | 344.85 seconds |
| Started | Feb 08 09:57:29 AM UTC 25 |
| Finished | Feb 08 10:03:19 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184650193 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.184650193 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.4002623286 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 22854381117 ps |
| CPU time | 70.48 seconds |
| Started | Feb 08 09:57:31 AM UTC 25 |
| Finished | Feb 08 09:58:43 AM UTC 25 |
| Peak memory | 199300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002623286 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4002623286 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.3342661826 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 21643476475 ps |
| CPU time | 44.4 seconds |
| Started | Feb 08 09:57:35 AM UTC 25 |
| Finished | Feb 08 09:58:21 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342661826 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3342661826 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.401307163 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 71575332611 ps |
| CPU time | 205.37 seconds |
| Started | Feb 08 09:58:03 AM UTC 25 |
| Finished | Feb 08 10:01:32 AM UTC 25 |
| Peak memory | 199484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401307163 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.401307163 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3737885853 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 102857246189 ps |
| CPU time | 537.89 seconds |
| Started | Feb 08 09:58:14 AM UTC 25 |
| Finished | Feb 08 10:07:19 AM UTC 25 |
| Peak memory | 199428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737885853 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3737885853 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.1648240360 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 204229196779 ps |
| CPU time | 316.48 seconds |
| Started | Feb 08 09:58:25 AM UTC 25 |
| Finished | Feb 08 10:03:46 AM UTC 25 |
| Peak memory | 199556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648240360 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1648240360 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.1593229485 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 245472067048 ps |
| CPU time | 216.68 seconds |
| Started | Feb 08 09:58:36 AM UTC 25 |
| Finished | Feb 08 10:02:16 AM UTC 25 |
| Peak memory | 199232 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593229485 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1593229485 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.841936508 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 717795878625 ps |
| CPU time | 514.07 seconds |
| Started | Feb 08 09:20:28 AM UTC 25 |
| Finished | Feb 08 09:29:09 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841936508 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.841936508 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3000659021 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 764625864146 ps |
| CPU time | 149.6 seconds |
| Started | Feb 08 09:20:18 AM UTC 25 |
| Finished | Feb 08 09:22:50 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000659021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.rv_timer_disabled.3000659021 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.3965123582 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 83403892220 ps |
| CPU time | 43.86 seconds |
| Started | Feb 08 09:20:13 AM UTC 25 |
| Finished | Feb 08 09:20:58 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965123582 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3965123582 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.3405886828 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 313993426445 ps |
| CPU time | 258.87 seconds |
| Started | Feb 08 09:20:43 AM UTC 25 |
| Finished | Feb 08 09:25:06 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405886828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3405886828 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.1769979196 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 221267204605 ps |
| CPU time | 357.64 seconds |
| Started | Feb 08 09:58:44 AM UTC 25 |
| Finished | Feb 08 10:04:47 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769979196 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1769979196 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.3288363081 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 188750291635 ps |
| CPU time | 106.06 seconds |
| Started | Feb 08 09:58:46 AM UTC 25 |
| Finished | Feb 08 10:00:35 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288363081 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3288363081 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.1999220453 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 391505213375 ps |
| CPU time | 856.57 seconds |
| Started | Feb 08 09:59:08 AM UTC 25 |
| Finished | Feb 08 10:13:35 AM UTC 25 |
| Peak memory | 202184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999220453 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1999220453 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1375839368 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 220355535543 ps |
| CPU time | 179.54 seconds |
| Started | Feb 08 09:59:22 AM UTC 25 |
| Finished | Feb 08 10:02:25 AM UTC 25 |
| Peak memory | 199492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375839368 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1375839368 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.252723642 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 51080737342 ps |
| CPU time | 524.88 seconds |
| Started | Feb 08 09:59:34 AM UTC 25 |
| Finished | Feb 08 10:08:26 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252723642 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.252723642 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.2564446253 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12943665566 ps |
| CPU time | 45.44 seconds |
| Started | Feb 08 09:59:56 AM UTC 25 |
| Finished | Feb 08 10:00:43 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564446253 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2564446253 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.1916894550 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1879677080398 ps |
| CPU time | 1030.4 seconds |
| Started | Feb 08 09:21:02 AM UTC 25 |
| Finished | Feb 08 09:38:24 AM UTC 25 |
| Peak memory | 201980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916894550 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.1916894550 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.2851708237 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 569148749498 ps |
| CPU time | 183.69 seconds |
| Started | Feb 08 09:21:18 AM UTC 25 |
| Finished | Feb 08 09:24:25 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851708237 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.2851708237 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.4201125752 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 52582487539 ps |
| CPU time | 148.44 seconds |
| Started | Feb 08 10:00:29 AM UTC 25 |
| Finished | Feb 08 10:03:03 AM UTC 25 |
| Peak memory | 198984 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201125752 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4201125752 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3540862958 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 380907352465 ps |
| CPU time | 423.74 seconds |
| Started | Feb 08 10:00:29 AM UTC 25 |
| Finished | Feb 08 10:07:41 AM UTC 25 |
| Peak memory | 199300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540862958 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3540862958 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.1339799127 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 161595519385 ps |
| CPU time | 238.07 seconds |
| Started | Feb 08 10:00:29 AM UTC 25 |
| Finished | Feb 08 10:04:33 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339799127 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1339799127 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.593174457 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 27219907999 ps |
| CPU time | 80.89 seconds |
| Started | Feb 08 10:00:31 AM UTC 25 |
| Finished | Feb 08 10:01:55 AM UTC 25 |
| Peak memory | 199412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593174457 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.593174457 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.360431844 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 61267261892 ps |
| CPU time | 102.42 seconds |
| Started | Feb 08 10:00:36 AM UTC 25 |
| Finished | Feb 08 10:02:20 AM UTC 25 |
| Peak memory | 198996 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360431844 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.360431844 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.4290884419 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 98638023891 ps |
| CPU time | 186.02 seconds |
| Started | Feb 08 10:00:44 AM UTC 25 |
| Finished | Feb 08 10:03:53 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290884419 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4290884419 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.4251734093 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 375936250452 ps |
| CPU time | 289.57 seconds |
| Started | Feb 08 10:00:46 AM UTC 25 |
| Finished | Feb 08 10:05:40 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251734093 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4251734093 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.3988442413 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 627156184372 ps |
| CPU time | 336.06 seconds |
| Started | Feb 08 10:00:50 AM UTC 25 |
| Finished | Feb 08 10:06:31 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988442413 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3988442413 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.942155816 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 509181473044 ps |
| CPU time | 473.09 seconds |
| Started | Feb 08 09:21:43 AM UTC 25 |
| Finished | Feb 08 09:29:42 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942155816 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.942155816 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.1600071881 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 334407932630 ps |
| CPU time | 211.51 seconds |
| Started | Feb 08 09:21:43 AM UTC 25 |
| Finished | Feb 08 09:25:18 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600071881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.rv_timer_disabled.1600071881 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.1171425895 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 329148834799 ps |
| CPU time | 1212.57 seconds |
| Started | Feb 08 09:21:20 AM UTC 25 |
| Finished | Feb 08 09:41:47 AM UTC 25 |
| Peak memory | 202296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171425895 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1171425895 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.4135829808 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 79255735806 ps |
| CPU time | 60.56 seconds |
| Started | Feb 08 09:21:45 AM UTC 25 |
| Finished | Feb 08 09:22:48 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135829808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4135829808 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.2515728840 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 223982566891 ps |
| CPU time | 365.58 seconds |
| Started | Feb 08 09:22:07 AM UTC 25 |
| Finished | Feb 08 09:28:17 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515728840 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.2515728840 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1729277406 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 222046325582 ps |
| CPU time | 347.44 seconds |
| Started | Feb 08 10:01:21 AM UTC 25 |
| Finished | Feb 08 10:07:13 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729277406 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1729277406 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.2968374444 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 25399794737 ps |
| CPU time | 96.34 seconds |
| Started | Feb 08 10:01:55 AM UTC 25 |
| Finished | Feb 08 10:03:35 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968374444 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2968374444 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.43764325 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 154366561666 ps |
| CPU time | 503.35 seconds |
| Started | Feb 08 10:01:59 AM UTC 25 |
| Finished | Feb 08 10:10:29 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43764325 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.43764325 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.1316458081 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 88542011078 ps |
| CPU time | 332.39 seconds |
| Started | Feb 08 10:02:06 AM UTC 25 |
| Finished | Feb 08 10:07:43 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316458081 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1316458081 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.3382400247 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 736439151874 ps |
| CPU time | 409.95 seconds |
| Started | Feb 08 10:02:14 AM UTC 25 |
| Finished | Feb 08 10:09:11 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382400247 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3382400247 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1481561670 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 149594689955 ps |
| CPU time | 84.9 seconds |
| Started | Feb 08 10:02:15 AM UTC 25 |
| Finished | Feb 08 10:03:43 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481561670 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1481561670 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2216162335 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 417674517577 ps |
| CPU time | 177.91 seconds |
| Started | Feb 08 10:02:16 AM UTC 25 |
| Finished | Feb 08 10:05:18 AM UTC 25 |
| Peak memory | 199356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216162335 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2216162335 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.3603993191 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 617479152906 ps |
| CPU time | 435.05 seconds |
| Started | Feb 08 09:15:21 AM UTC 25 |
| Finished | Feb 08 09:22:42 AM UTC 25 |
| Peak memory | 199300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603993191 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.3603993191 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.261465740 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 380464908823 ps |
| CPU time | 148.56 seconds |
| Started | Feb 08 09:15:21 AM UTC 25 |
| Finished | Feb 08 09:17:53 AM UTC 25 |
| Peak memory | 198672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261465740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.rv_timer_disabled.261465740 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.1265688867 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 68603892591 ps |
| CPU time | 2184.09 seconds |
| Started | Feb 08 09:15:21 AM UTC 25 |
| Finished | Feb 08 09:52:11 AM UTC 25 |
| Peak memory | 202040 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265688867 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1265688867 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.3568326990 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 57586702393 ps |
| CPU time | 146.41 seconds |
| Started | Feb 08 09:15:21 AM UTC 25 |
| Finished | Feb 08 09:17:51 AM UTC 25 |
| Peak memory | 198516 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568326990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3568326990 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.3141310933 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 416535772621 ps |
| CPU time | 182.37 seconds |
| Started | Feb 08 09:22:34 AM UTC 25 |
| Finished | Feb 08 09:25:39 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141310933 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.3141310933 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.1574770200 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 511651925573 ps |
| CPU time | 275.69 seconds |
| Started | Feb 08 09:22:21 AM UTC 25 |
| Finished | Feb 08 09:27:01 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574770200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.rv_timer_disabled.1574770200 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.4075200490 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 18415413687 ps |
| CPU time | 91.53 seconds |
| Started | Feb 08 09:22:43 AM UTC 25 |
| Finished | Feb 08 09:24:17 AM UTC 25 |
| Peak memory | 199412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075200490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4075200490 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.3847516939 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 182365563525 ps |
| CPU time | 372.3 seconds |
| Started | Feb 08 09:22:48 AM UTC 25 |
| Finished | Feb 08 09:29:05 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847516939 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.3847516939 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.2633285369 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 58035687323 ps |
| CPU time | 79.9 seconds |
| Started | Feb 08 09:22:51 AM UTC 25 |
| Finished | Feb 08 09:24:14 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633285369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.rv_timer_disabled.2633285369 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3971360299 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 82056390212 ps |
| CPU time | 198.13 seconds |
| Started | Feb 08 09:22:49 AM UTC 25 |
| Finished | Feb 08 09:26:10 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971360299 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3971360299 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.713732425 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 76662695867 ps |
| CPU time | 301.31 seconds |
| Started | Feb 08 09:22:53 AM UTC 25 |
| Finished | Feb 08 09:27:59 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713732425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.713732425 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.2550293809 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 15350168707 ps |
| CPU time | 19.99 seconds |
| Started | Feb 08 09:23:02 AM UTC 25 |
| Finished | Feb 08 09:23:24 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550293809 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.2550293809 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.518252265 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 18032315909 ps |
| CPU time | 166.29 seconds |
| Started | Feb 08 09:23:00 AM UTC 25 |
| Finished | Feb 08 09:25:49 AM UTC 25 |
| Peak memory | 203656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=518252265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_al l_with_rand_reset.518252265 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.1269276409 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 389430611137 ps |
| CPU time | 277.61 seconds |
| Started | Feb 08 09:23:06 AM UTC 25 |
| Finished | Feb 08 09:27:48 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269276409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.rv_timer_disabled.1269276409 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.3431898039 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 26564868458 ps |
| CPU time | 312.53 seconds |
| Started | Feb 08 09:23:04 AM UTC 25 |
| Finished | Feb 08 09:28:21 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431898039 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3431898039 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.1199897948 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 164161261357 ps |
| CPU time | 79.53 seconds |
| Started | Feb 08 09:23:17 AM UTC 25 |
| Finished | Feb 08 09:24:39 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199897948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1199897948 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.2454402966 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 886900880296 ps |
| CPU time | 554 seconds |
| Started | Feb 08 09:23:48 AM UTC 25 |
| Finished | Feb 08 09:33:09 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454402966 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.2454402966 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.1981251902 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 44755935012 ps |
| CPU time | 121.81 seconds |
| Started | Feb 08 09:23:37 AM UTC 25 |
| Finished | Feb 08 09:25:41 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981251902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 23.rv_timer_disabled.1981251902 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.1041594290 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 314346326992 ps |
| CPU time | 427.66 seconds |
| Started | Feb 08 09:23:28 AM UTC 25 |
| Finished | Feb 08 09:30:41 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041594290 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1041594290 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.2060268757 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 108121737 ps |
| CPU time | 1.12 seconds |
| Started | Feb 08 09:23:53 AM UTC 25 |
| Finished | Feb 08 09:23:55 AM UTC 25 |
| Peak memory | 198216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060268757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2060268757 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.55332271 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 290366130760 ps |
| CPU time | 499.16 seconds |
| Started | Feb 08 09:24:19 AM UTC 25 |
| Finished | Feb 08 09:32:45 AM UTC 25 |
| Peak memory | 199192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55332271 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.55332271 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.2071948671 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 23343036093 ps |
| CPU time | 38.48 seconds |
| Started | Feb 08 09:24:18 AM UTC 25 |
| Finished | Feb 08 09:24:59 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071948671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.rv_timer_disabled.2071948671 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.55316633 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1130265903 ps |
| CPU time | 1.36 seconds |
| Started | Feb 08 09:24:25 AM UTC 25 |
| Finished | Feb 08 09:24:28 AM UTC 25 |
| Peak memory | 198220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55316633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_time r_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.55316633 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.2393873840 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 85378008416 ps |
| CPU time | 146.52 seconds |
| Started | Feb 08 09:24:31 AM UTC 25 |
| Finished | Feb 08 09:27:00 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393873840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.rv_timer_disabled.2393873840 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.3694511725 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 213597596505 ps |
| CPU time | 96.06 seconds |
| Started | Feb 08 09:24:40 AM UTC 25 |
| Finished | Feb 08 09:26:18 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694511725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3694511725 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.3351755061 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 15322265928 ps |
| CPU time | 124.67 seconds |
| Started | Feb 08 09:24:45 AM UTC 25 |
| Finished | Feb 08 09:26:53 AM UTC 25 |
| Peak memory | 205532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3351755061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_a ll_with_rand_reset.3351755061 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.3049957435 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 57254437651 ps |
| CPU time | 59.95 seconds |
| Started | Feb 08 09:25:02 AM UTC 25 |
| Finished | Feb 08 09:26:04 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049957435 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3049957435 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.3026933831 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 40757612596 ps |
| CPU time | 47.45 seconds |
| Started | Feb 08 09:25:00 AM UTC 25 |
| Finished | Feb 08 09:25:50 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026933831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.rv_timer_disabled.3026933831 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.3043688204 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 587667611836 ps |
| CPU time | 576.51 seconds |
| Started | Feb 08 09:24:59 AM UTC 25 |
| Finished | Feb 08 09:34:42 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043688204 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3043688204 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1553544560 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 440546303758 ps |
| CPU time | 220.85 seconds |
| Started | Feb 08 09:25:03 AM UTC 25 |
| Finished | Feb 08 09:28:48 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553544560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1553544560 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.417098105 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 118999150076 ps |
| CPU time | 266.68 seconds |
| Started | Feb 08 09:25:40 AM UTC 25 |
| Finished | Feb 08 09:30:11 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417098105 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.417098105 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.3977101704 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 506230024050 ps |
| CPU time | 281.03 seconds |
| Started | Feb 08 09:25:28 AM UTC 25 |
| Finished | Feb 08 09:30:14 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977101704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.rv_timer_disabled.3977101704 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1255345652 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 86750392614 ps |
| CPU time | 232.64 seconds |
| Started | Feb 08 09:25:20 AM UTC 25 |
| Finished | Feb 08 09:29:17 AM UTC 25 |
| Peak memory | 199196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255345652 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1255345652 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.2192869895 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 33976079108 ps |
| CPU time | 164.77 seconds |
| Started | Feb 08 09:25:42 AM UTC 25 |
| Finished | Feb 08 09:28:30 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192869895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2192869895 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.23349687 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 140915087889 ps |
| CPU time | 311.19 seconds |
| Started | Feb 08 09:25:51 AM UTC 25 |
| Finished | Feb 08 09:31:07 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23349687 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_tim er-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.23349687 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all_with_rand_reset.94934972 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 25129381160 ps |
| CPU time | 285.43 seconds |
| Started | Feb 08 09:25:51 AM UTC 25 |
| Finished | Feb 08 09:30:41 AM UTC 25 |
| Peak memory | 215932 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=94934972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all _with_rand_reset.94934972 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.3539227364 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 40653555429 ps |
| CPU time | 75.48 seconds |
| Started | Feb 08 09:26:13 AM UTC 25 |
| Finished | Feb 08 09:27:31 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539227364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 28.rv_timer_disabled.3539227364 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.784129672 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 255784203893 ps |
| CPU time | 1474.18 seconds |
| Started | Feb 08 09:26:07 AM UTC 25 |
| Finished | Feb 08 09:50:59 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784129672 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.784129672 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.2781474288 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 89425951388 ps |
| CPU time | 229.76 seconds |
| Started | Feb 08 09:26:31 AM UTC 25 |
| Finished | Feb 08 09:30:25 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781474288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2781474288 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1348761381 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 606746174904 ps |
| CPU time | 292.38 seconds |
| Started | Feb 08 09:26:44 AM UTC 25 |
| Finished | Feb 08 09:31:41 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348761381 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.1348761381 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.3887372639 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 446010851892 ps |
| CPU time | 222.29 seconds |
| Started | Feb 08 09:26:55 AM UTC 25 |
| Finished | Feb 08 09:30:41 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887372639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.rv_timer_disabled.3887372639 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1405585440 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 458303175670 ps |
| CPU time | 580.03 seconds |
| Started | Feb 08 09:27:03 AM UTC 25 |
| Finished | Feb 08 09:36:50 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405585440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1405585440 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.3742811683 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 413199776494 ps |
| CPU time | 133.86 seconds |
| Started | Feb 08 09:15:24 AM UTC 25 |
| Finished | Feb 08 09:17:41 AM UTC 25 |
| Peak memory | 199428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742811683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.rv_timer_disabled.3742811683 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3846385907 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 45244330956 ps |
| CPU time | 84.82 seconds |
| Started | Feb 08 09:15:22 AM UTC 25 |
| Finished | Feb 08 09:16:50 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846385907 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3846385907 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.3525595679 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1091543160 ps |
| CPU time | 1.72 seconds |
| Started | Feb 08 09:15:24 AM UTC 25 |
| Finished | Feb 08 09:15:27 AM UTC 25 |
| Peak memory | 198160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525595679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3525595679 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.1623843731 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 31770259 ps |
| CPU time | 1.13 seconds |
| Started | Feb 08 09:15:25 AM UTC 25 |
| Finished | Feb 08 09:15:28 AM UTC 25 |
| Peak memory | 230236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623843731 -assert nopostproc +UVM_TESTNAME=rv_timer_base _test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1623843731 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3029083709 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 378340245368 ps |
| CPU time | 407.37 seconds |
| Started | Feb 08 09:27:32 AM UTC 25 |
| Finished | Feb 08 09:34:25 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029083709 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3029083709 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2990751401 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 198913191858 ps |
| CPU time | 88.04 seconds |
| Started | Feb 08 09:27:32 AM UTC 25 |
| Finished | Feb 08 09:29:02 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990751401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.rv_timer_disabled.2990751401 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3316647230 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 288297883402 ps |
| CPU time | 104.35 seconds |
| Started | Feb 08 09:27:14 AM UTC 25 |
| Finished | Feb 08 09:29:01 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316647230 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3316647230 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.798834060 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 581382766212 ps |
| CPU time | 987.42 seconds |
| Started | Feb 08 09:28:18 AM UTC 25 |
| Finished | Feb 08 09:44:56 AM UTC 25 |
| Peak memory | 202108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798834060 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.798834060 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.3795516888 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 100863386260 ps |
| CPU time | 854.98 seconds |
| Started | Feb 08 09:27:59 AM UTC 25 |
| Finished | Feb 08 09:42:25 AM UTC 25 |
| Peak memory | 224640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3795516888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_a ll_with_rand_reset.3795516888 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.1093579025 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 108708684545 ps |
| CPU time | 178.15 seconds |
| Started | Feb 08 09:28:26 AM UTC 25 |
| Finished | Feb 08 09:31:28 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093579025 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.1093579025 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.3678774601 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 134286327230 ps |
| CPU time | 154.29 seconds |
| Started | Feb 08 09:28:22 AM UTC 25 |
| Finished | Feb 08 09:31:00 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678774601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.rv_timer_disabled.3678774601 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2101089669 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 114227611247 ps |
| CPU time | 940.81 seconds |
| Started | Feb 08 09:28:18 AM UTC 25 |
| Finished | Feb 08 09:44:10 AM UTC 25 |
| Peak memory | 202168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101089669 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2101089669 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all_with_rand_reset.1211482596 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 148981386760 ps |
| CPU time | 974.88 seconds |
| Started | Feb 08 09:28:38 AM UTC 25 |
| Finished | Feb 08 09:45:04 AM UTC 25 |
| Peak memory | 220648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1211482596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_a ll_with_rand_reset.1211482596 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.2607363580 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1550778435234 ps |
| CPU time | 463.05 seconds |
| Started | Feb 08 09:29:02 AM UTC 25 |
| Finished | Feb 08 09:36:51 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607363580 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.2607363580 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.698890411 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 130020516971 ps |
| CPU time | 238.46 seconds |
| Started | Feb 08 09:28:58 AM UTC 25 |
| Finished | Feb 08 09:33:00 AM UTC 25 |
| Peak memory | 199396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698890411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 32.rv_timer_disabled.698890411 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.4016689879 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 126888543511 ps |
| CPU time | 1998.51 seconds |
| Started | Feb 08 09:28:49 AM UTC 25 |
| Finished | Feb 08 10:02:29 AM UTC 25 |
| Peak memory | 201968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016689879 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4016689879 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.3243830356 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 7365693554 ps |
| CPU time | 13.39 seconds |
| Started | Feb 08 09:29:03 AM UTC 25 |
| Finished | Feb 08 09:29:18 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243830356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3243830356 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.3052513617 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 51503095811 ps |
| CPU time | 584.09 seconds |
| Started | Feb 08 09:29:06 AM UTC 25 |
| Finished | Feb 08 09:38:57 AM UTC 25 |
| Peak memory | 218012 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3052513617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_a ll_with_rand_reset.3052513617 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1446096664 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 55253121261 ps |
| CPU time | 53.23 seconds |
| Started | Feb 08 09:29:17 AM UTC 25 |
| Finished | Feb 08 09:30:13 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446096664 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1446096664 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.4034480098 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 97448801103 ps |
| CPU time | 162.4 seconds |
| Started | Feb 08 09:29:11 AM UTC 25 |
| Finished | Feb 08 09:31:57 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034480098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.rv_timer_disabled.4034480098 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.1268475736 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 112594156915 ps |
| CPU time | 210.21 seconds |
| Started | Feb 08 09:29:50 AM UTC 25 |
| Finished | Feb 08 09:33:23 AM UTC 25 |
| Peak memory | 199300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268475736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.rv_timer_disabled.1268475736 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.508215625 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 263651008010 ps |
| CPU time | 691.91 seconds |
| Started | Feb 08 09:30:13 AM UTC 25 |
| Finished | Feb 08 09:41:53 AM UTC 25 |
| Peak memory | 199548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508215625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.508215625 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.794601621 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 183750834702 ps |
| CPU time | 241.01 seconds |
| Started | Feb 08 09:30:25 AM UTC 25 |
| Finished | Feb 08 09:34:30 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794601621 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.794601621 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.3377757138 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 84033025795 ps |
| CPU time | 227.41 seconds |
| Started | Feb 08 09:30:14 AM UTC 25 |
| Finished | Feb 08 09:34:06 AM UTC 25 |
| Peak memory | 219916 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3377757138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_a ll_with_rand_reset.3377757138 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.3115497652 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 172742151355 ps |
| CPU time | 479.25 seconds |
| Started | Feb 08 09:30:29 AM UTC 25 |
| Finished | Feb 08 09:38:35 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115497652 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.3115497652 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.4158595036 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 150238343099 ps |
| CPU time | 426.07 seconds |
| Started | Feb 08 09:30:28 AM UTC 25 |
| Finished | Feb 08 09:37:40 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158595036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.rv_timer_disabled.4158595036 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.2742820982 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 109345230806 ps |
| CPU time | 273.85 seconds |
| Started | Feb 08 09:30:27 AM UTC 25 |
| Finished | Feb 08 09:35:05 AM UTC 25 |
| Peak memory | 199412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742820982 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2742820982 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.1879011561 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 158213462190 ps |
| CPU time | 367.04 seconds |
| Started | Feb 08 09:30:42 AM UTC 25 |
| Finished | Feb 08 09:36:54 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879011561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1879011561 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.776028477 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1117233416720 ps |
| CPU time | 488.51 seconds |
| Started | Feb 08 09:31:01 AM UTC 25 |
| Finished | Feb 08 09:39:16 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776028477 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.776028477 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.560567079 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 155366492985 ps |
| CPU time | 260.25 seconds |
| Started | Feb 08 09:30:55 AM UTC 25 |
| Finished | Feb 08 09:35:19 AM UTC 25 |
| Peak memory | 199192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560567079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 36.rv_timer_disabled.560567079 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.2103862628 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 129283912465 ps |
| CPU time | 611.69 seconds |
| Started | Feb 08 09:30:51 AM UTC 25 |
| Finished | Feb 08 09:41:10 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103862628 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2103862628 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.1752194762 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 126654435737 ps |
| CPU time | 119.47 seconds |
| Started | Feb 08 09:31:08 AM UTC 25 |
| Finished | Feb 08 09:33:10 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752194762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1752194762 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.1153252989 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 172399829956 ps |
| CPU time | 158.15 seconds |
| Started | Feb 08 09:31:41 AM UTC 25 |
| Finished | Feb 08 09:34:23 AM UTC 25 |
| Peak memory | 199280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153252989 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.1153252989 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.3494761676 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 171198748027 ps |
| CPU time | 327.98 seconds |
| Started | Feb 08 09:32:12 AM UTC 25 |
| Finished | Feb 08 09:37:45 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494761676 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.3494761676 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.933365891 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 107879442058 ps |
| CPU time | 142.45 seconds |
| Started | Feb 08 09:31:57 AM UTC 25 |
| Finished | Feb 08 09:34:23 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933365891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 37.rv_timer_disabled.933365891 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.1818098300 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 265475248139 ps |
| CPU time | 367.5 seconds |
| Started | Feb 08 09:31:50 AM UTC 25 |
| Finished | Feb 08 09:38:03 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818098300 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1818098300 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2512050981 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 10049479016 ps |
| CPU time | 7.08 seconds |
| Started | Feb 08 09:32:36 AM UTC 25 |
| Finished | Feb 08 09:32:44 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512050981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2512050981 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.2762375844 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 628683796783 ps |
| CPU time | 427.87 seconds |
| Started | Feb 08 09:33:11 AM UTC 25 |
| Finished | Feb 08 09:40:25 AM UTC 25 |
| Peak memory | 199488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762375844 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.2762375844 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2454835644 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 177517877801 ps |
| CPU time | 156.21 seconds |
| Started | Feb 08 09:33:10 AM UTC 25 |
| Finished | Feb 08 09:35:49 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454835644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.rv_timer_disabled.2454835644 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.2617061763 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 39229997614 ps |
| CPU time | 202.4 seconds |
| Started | Feb 08 09:33:01 AM UTC 25 |
| Finished | Feb 08 09:36:27 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617061763 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2617061763 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.496169970 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 607653045 ps |
| CPU time | 1.63 seconds |
| Started | Feb 08 09:33:24 AM UTC 25 |
| Finished | Feb 08 09:33:27 AM UTC 25 |
| Peak memory | 198280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496169970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.496169970 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1705922041 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 169388896216 ps |
| CPU time | 286.36 seconds |
| Started | Feb 08 09:33:49 AM UTC 25 |
| Finished | Feb 08 09:38:40 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705922041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.rv_timer_disabled.1705922041 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.1435727729 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 47066296388 ps |
| CPU time | 109.72 seconds |
| Started | Feb 08 09:33:47 AM UTC 25 |
| Finished | Feb 08 09:35:40 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435727729 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1435727729 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.3836692030 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 118824891389 ps |
| CPU time | 149.87 seconds |
| Started | Feb 08 09:34:24 AM UTC 25 |
| Finished | Feb 08 09:36:57 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836692030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3836692030 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.531377911 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 306481371001 ps |
| CPU time | 122.84 seconds |
| Started | Feb 08 09:15:26 AM UTC 25 |
| Finished | Feb 08 09:17:31 AM UTC 25 |
| Peak memory | 199228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531377911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.rv_timer_disabled.531377911 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.1165134102 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 174568620537 ps |
| CPU time | 525.5 seconds |
| Started | Feb 08 09:15:26 AM UTC 25 |
| Finished | Feb 08 09:24:18 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165134102 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1165134102 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.2350121497 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 37054660 ps |
| CPU time | 1.16 seconds |
| Started | Feb 08 09:15:36 AM UTC 25 |
| Finished | Feb 08 09:15:38 AM UTC 25 |
| Peak memory | 230236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350121497 -assert nopostproc +UVM_TESTNAME=rv_timer_base _test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2350121497 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.3504261347 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5820937814 ps |
| CPU time | 6.78 seconds |
| Started | Feb 08 09:34:43 AM UTC 25 |
| Finished | Feb 08 09:34:51 AM UTC 25 |
| Peak memory | 199196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504261347 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3504261347 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.3669417931 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 64451372183 ps |
| CPU time | 144.79 seconds |
| Started | Feb 08 09:34:31 AM UTC 25 |
| Finished | Feb 08 09:36:59 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669417931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.rv_timer_disabled.3669417931 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.36044113 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 108750558472 ps |
| CPU time | 73.32 seconds |
| Started | Feb 08 09:34:26 AM UTC 25 |
| Finished | Feb 08 09:35:41 AM UTC 25 |
| Peak memory | 199080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36044113 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.36044113 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1580280037 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 87358377633 ps |
| CPU time | 374.48 seconds |
| Started | Feb 08 09:34:52 AM UTC 25 |
| Finished | Feb 08 09:41:12 AM UTC 25 |
| Peak memory | 199484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580280037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1580280037 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.660446029 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 21397353 ps |
| CPU time | 0.84 seconds |
| Started | Feb 08 09:35:20 AM UTC 25 |
| Finished | Feb 08 09:35:22 AM UTC 25 |
| Peak memory | 198216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660446029 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.660446029 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.1839648169 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1075676944519 ps |
| CPU time | 722.77 seconds |
| Started | Feb 08 09:35:41 AM UTC 25 |
| Finished | Feb 08 09:47:52 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839648169 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.1839648169 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.701933858 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 231725495617 ps |
| CPU time | 161.46 seconds |
| Started | Feb 08 09:35:40 AM UTC 25 |
| Finished | Feb 08 09:38:25 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701933858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 41.rv_timer_disabled.701933858 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.950736489 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 466431409967 ps |
| CPU time | 1158.95 seconds |
| Started | Feb 08 09:36:14 AM UTC 25 |
| Finished | Feb 08 09:55:46 AM UTC 25 |
| Peak memory | 202164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950736489 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.950736489 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.3630077233 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1544078031424 ps |
| CPU time | 1338.53 seconds |
| Started | Feb 08 09:36:49 AM UTC 25 |
| Finished | Feb 08 09:59:22 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630077233 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3630077233 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.3485653437 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 95303553742 ps |
| CPU time | 71.14 seconds |
| Started | Feb 08 09:36:28 AM UTC 25 |
| Finished | Feb 08 09:37:41 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485653437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.rv_timer_disabled.3485653437 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.25189563 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 351726260912 ps |
| CPU time | 1292.91 seconds |
| Started | Feb 08 09:36:15 AM UTC 25 |
| Finished | Feb 08 09:58:02 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25189563 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.25189563 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1471902809 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 960352027110 ps |
| CPU time | 390.05 seconds |
| Started | Feb 08 09:36:51 AM UTC 25 |
| Finished | Feb 08 09:43:27 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471902809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1471902809 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.3674564325 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 70327610460 ps |
| CPU time | 138.29 seconds |
| Started | Feb 08 09:36:55 AM UTC 25 |
| Finished | Feb 08 09:39:16 AM UTC 25 |
| Peak memory | 199352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674564325 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.3674564325 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.117722070 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 65183449591 ps |
| CPU time | 36.08 seconds |
| Started | Feb 08 09:36:59 AM UTC 25 |
| Finished | Feb 08 09:37:37 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117722070 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.117722070 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.3769060912 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 315676850400 ps |
| CPU time | 144.25 seconds |
| Started | Feb 08 09:36:58 AM UTC 25 |
| Finished | Feb 08 09:39:25 AM UTC 25 |
| Peak memory | 199492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769060912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.rv_timer_disabled.3769060912 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.2181397192 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 47213525842 ps |
| CPU time | 398.99 seconds |
| Started | Feb 08 09:37:12 AM UTC 25 |
| Finished | Feb 08 09:43:57 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181397192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2181397192 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.2365334875 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 203497779065 ps |
| CPU time | 167.25 seconds |
| Started | Feb 08 09:37:42 AM UTC 25 |
| Finished | Feb 08 09:40:32 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365334875 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.2365334875 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3399966695 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 700085518402 ps |
| CPU time | 842.76 seconds |
| Started | Feb 08 09:37:59 AM UTC 25 |
| Finished | Feb 08 09:52:11 AM UTC 25 |
| Peak memory | 199340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399966695 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.3399966695 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.3051958191 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 301948730839 ps |
| CPU time | 261.18 seconds |
| Started | Feb 08 09:37:46 AM UTC 25 |
| Finished | Feb 08 09:42:11 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051958191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.rv_timer_disabled.3051958191 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.4052077189 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 111585790654 ps |
| CPU time | 168.01 seconds |
| Started | Feb 08 09:37:42 AM UTC 25 |
| Finished | Feb 08 09:40:32 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052077189 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4052077189 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2804543168 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 91105235970 ps |
| CPU time | 137.2 seconds |
| Started | Feb 08 09:38:04 AM UTC 25 |
| Finished | Feb 08 09:40:24 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804543168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2804543168 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.2111160214 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 529272787126 ps |
| CPU time | 620.64 seconds |
| Started | Feb 08 09:38:26 AM UTC 25 |
| Finished | Feb 08 09:48:54 AM UTC 25 |
| Peak memory | 199408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111160214 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.2111160214 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.2931806860 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 286609512233 ps |
| CPU time | 338.25 seconds |
| Started | Feb 08 09:38:25 AM UTC 25 |
| Finished | Feb 08 09:44:08 AM UTC 25 |
| Peak memory | 215700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer _stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2931806860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_a ll_with_rand_reset.2931806860 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2239040815 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 90857435043 ps |
| CPU time | 88.63 seconds |
| Started | Feb 08 09:38:37 AM UTC 25 |
| Finished | Feb 08 09:40:08 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239040815 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2239040815 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.3558020319 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4265213799 ps |
| CPU time | 13.3 seconds |
| Started | Feb 08 09:38:36 AM UTC 25 |
| Finished | Feb 08 09:38:51 AM UTC 25 |
| Peak memory | 199004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558020319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.rv_timer_disabled.3558020319 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.12192896 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 33652945555 ps |
| CPU time | 65.67 seconds |
| Started | Feb 08 09:38:36 AM UTC 25 |
| Finished | Feb 08 09:39:44 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12192896 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.12192896 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.2889438690 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 46416197592 ps |
| CPU time | 138.57 seconds |
| Started | Feb 08 09:38:41 AM UTC 25 |
| Finished | Feb 08 09:41:03 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889438690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2889438690 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.1981895176 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 61846361297 ps |
| CPU time | 18.57 seconds |
| Started | Feb 08 09:38:57 AM UTC 25 |
| Finished | Feb 08 09:39:17 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981895176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.rv_timer_disabled.1981895176 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.127404069 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 18568737867 ps |
| CPU time | 29.07 seconds |
| Started | Feb 08 09:38:59 AM UTC 25 |
| Finished | Feb 08 09:39:30 AM UTC 25 |
| Peak memory | 199264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127404069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.127404069 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.2001863014 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2604899236900 ps |
| CPU time | 2603.25 seconds |
| Started | Feb 08 09:39:17 AM UTC 25 |
| Finished | Feb 08 10:23:07 AM UTC 25 |
| Peak memory | 201872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001863014 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.2001863014 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.980468314 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 186902143546 ps |
| CPU time | 161.97 seconds |
| Started | Feb 08 09:39:18 AM UTC 25 |
| Finished | Feb 08 09:42:03 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980468314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 47.rv_timer_disabled.980468314 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.4001963842 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 91290224812 ps |
| CPU time | 155.18 seconds |
| Started | Feb 08 09:39:17 AM UTC 25 |
| Finished | Feb 08 09:41:55 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001963842 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4001963842 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.2331075588 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 7717631193 ps |
| CPU time | 285.8 seconds |
| Started | Feb 08 09:39:26 AM UTC 25 |
| Finished | Feb 08 09:44:17 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331075588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2331075588 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.2756744185 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1550904299672 ps |
| CPU time | 822.8 seconds |
| Started | Feb 08 09:39:33 AM UTC 25 |
| Finished | Feb 08 09:53:26 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756744185 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.2756744185 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1839413126 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 94767780319 ps |
| CPU time | 88.54 seconds |
| Started | Feb 08 09:40:01 AM UTC 25 |
| Finished | Feb 08 09:41:31 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839413126 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1839413126 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.1596372809 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 128331504975 ps |
| CPU time | 327.99 seconds |
| Started | Feb 08 09:39:53 AM UTC 25 |
| Finished | Feb 08 09:45:25 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596372809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.rv_timer_disabled.1596372809 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.2209813519 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 86141427321 ps |
| CPU time | 146.42 seconds |
| Started | Feb 08 09:40:05 AM UTC 25 |
| Finished | Feb 08 09:42:34 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209813519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2209813519 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3947060079 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1224441953557 ps |
| CPU time | 684.8 seconds |
| Started | Feb 08 09:40:33 AM UTC 25 |
| Finished | Feb 08 09:52:06 AM UTC 25 |
| Peak memory | 199480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947060079 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3947060079 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.891776368 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 17857765537 ps |
| CPU time | 33.8 seconds |
| Started | Feb 08 09:40:32 AM UTC 25 |
| Finished | Feb 08 09:41:08 AM UTC 25 |
| Peak memory | 199416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891776368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 49.rv_timer_disabled.891776368 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2215134291 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 64575176437 ps |
| CPU time | 188.73 seconds |
| Started | Feb 08 09:40:26 AM UTC 25 |
| Finished | Feb 08 09:43:38 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215134291 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2215134291 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.2622122044 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 10873579745 ps |
| CPU time | 17.95 seconds |
| Started | Feb 08 09:40:37 AM UTC 25 |
| Finished | Feb 08 09:40:57 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622122044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2622122044 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.2292062139 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 40535549555 ps |
| CPU time | 299.08 seconds |
| Started | Feb 08 09:40:57 AM UTC 25 |
| Finished | Feb 08 09:46:01 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292062139 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.2292062139 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.1722517712 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 165570773291 ps |
| CPU time | 373.81 seconds |
| Started | Feb 08 09:15:47 AM UTC 25 |
| Finished | Feb 08 09:22:06 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722517712 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.1722517712 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.791132965 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 166844916093 ps |
| CPU time | 77.45 seconds |
| Started | Feb 08 09:15:44 AM UTC 25 |
| Finished | Feb 08 09:17:04 AM UTC 25 |
| Peak memory | 199488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791132965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.rv_timer_disabled.791132965 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.688670569 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 775618944 ps |
| CPU time | 1.81 seconds |
| Started | Feb 08 09:15:58 AM UTC 25 |
| Finished | Feb 08 09:16:02 AM UTC 25 |
| Peak memory | 198216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688670569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.688670569 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.152300836 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 534893112159 ps |
| CPU time | 534.58 seconds |
| Started | Feb 08 09:16:01 AM UTC 25 |
| Finished | Feb 08 09:25:02 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152300836 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.152300836 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.1829710086 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 784882845041 ps |
| CPU time | 462.31 seconds |
| Started | Feb 08 09:41:03 AM UTC 25 |
| Finished | Feb 08 09:48:52 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829710086 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1829710086 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2121655695 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 483098875042 ps |
| CPU time | 307.94 seconds |
| Started | Feb 08 09:41:09 AM UTC 25 |
| Finished | Feb 08 09:46:21 AM UTC 25 |
| Peak memory | 199484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121655695 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2121655695 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.2280589484 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1426014044232 ps |
| CPU time | 456.76 seconds |
| Started | Feb 08 09:41:11 AM UTC 25 |
| Finished | Feb 08 09:48:53 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280589484 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2280589484 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.3195937467 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 593077282180 ps |
| CPU time | 298.02 seconds |
| Started | Feb 08 09:41:13 AM UTC 25 |
| Finished | Feb 08 09:46:15 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195937467 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3195937467 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.3450652848 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 111605400648 ps |
| CPU time | 414.04 seconds |
| Started | Feb 08 09:41:33 AM UTC 25 |
| Finished | Feb 08 09:48:33 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450652848 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3450652848 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.3420924839 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 86089669735 ps |
| CPU time | 415.82 seconds |
| Started | Feb 08 09:41:48 AM UTC 25 |
| Finished | Feb 08 09:48:49 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420924839 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3420924839 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.433088195 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 320641597955 ps |
| CPU time | 333.4 seconds |
| Started | Feb 08 09:41:54 AM UTC 25 |
| Finished | Feb 08 09:47:32 AM UTC 25 |
| Peak memory | 199488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433088195 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.433088195 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.1372247435 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 284136616047 ps |
| CPU time | 231.44 seconds |
| Started | Feb 08 09:41:56 AM UTC 25 |
| Finished | Feb 08 09:45:51 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372247435 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1372247435 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3266175172 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 215035228167 ps |
| CPU time | 333.39 seconds |
| Started | Feb 08 09:42:04 AM UTC 25 |
| Finished | Feb 08 09:47:42 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266175172 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3266175172 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.403513622 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 645721781140 ps |
| CPU time | 871.08 seconds |
| Started | Feb 08 09:42:11 AM UTC 25 |
| Finished | Feb 08 09:56:53 AM UTC 25 |
| Peak memory | 201972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403513622 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.403513622 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.59614233 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 106750566502 ps |
| CPU time | 247.79 seconds |
| Started | Feb 08 09:16:05 AM UTC 25 |
| Finished | Feb 08 09:20:17 AM UTC 25 |
| Peak memory | 199392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59614233 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.59614233 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.1414675099 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 139598363272 ps |
| CPU time | 113.11 seconds |
| Started | Feb 08 09:16:03 AM UTC 25 |
| Finished | Feb 08 09:17:59 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414675099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.rv_timer_disabled.1414675099 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.2382346647 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 63154605317 ps |
| CPU time | 137.41 seconds |
| Started | Feb 08 09:16:03 AM UTC 25 |
| Finished | Feb 08 09:18:23 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382346647 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2382346647 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.2590988925 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 48684988834 ps |
| CPU time | 196.95 seconds |
| Started | Feb 08 09:16:07 AM UTC 25 |
| Finished | Feb 08 09:19:27 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590988925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2590988925 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2879732539 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2370888350690 ps |
| CPU time | 652.47 seconds |
| Started | Feb 08 09:42:25 AM UTC 25 |
| Finished | Feb 08 09:53:26 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879732539 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2879732539 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.2892767678 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 125672658572 ps |
| CPU time | 456.67 seconds |
| Started | Feb 08 09:42:28 AM UTC 25 |
| Finished | Feb 08 09:50:12 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892767678 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2892767678 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.937300530 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 395485685547 ps |
| CPU time | 640.6 seconds |
| Started | Feb 08 09:42:50 AM UTC 25 |
| Finished | Feb 08 09:53:38 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937300530 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.937300530 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.2005823250 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 609267779663 ps |
| CPU time | 423.65 seconds |
| Started | Feb 08 09:43:13 AM UTC 25 |
| Finished | Feb 08 09:50:22 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005823250 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2005823250 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2587043185 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 58453082494 ps |
| CPU time | 180.89 seconds |
| Started | Feb 08 09:43:19 AM UTC 25 |
| Finished | Feb 08 09:46:23 AM UTC 25 |
| Peak memory | 199412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587043185 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2587043185 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.2172840884 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 21969290187 ps |
| CPU time | 21.57 seconds |
| Started | Feb 08 09:43:28 AM UTC 25 |
| Finished | Feb 08 09:43:51 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172840884 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2172840884 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.4190467838 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1323985677315 ps |
| CPU time | 389.71 seconds |
| Started | Feb 08 09:43:52 AM UTC 25 |
| Finished | Feb 08 09:50:27 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190467838 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4190467838 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.17831543 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 537672518085 ps |
| CPU time | 605.45 seconds |
| Started | Feb 08 09:43:57 AM UTC 25 |
| Finished | Feb 08 09:54:10 AM UTC 25 |
| Peak memory | 199428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17831543 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.17831543 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.4078376778 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 126905819372 ps |
| CPU time | 190.68 seconds |
| Started | Feb 08 09:16:16 AM UTC 25 |
| Finished | Feb 08 09:19:30 AM UTC 25 |
| Peak memory | 199196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078376778 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.4078376778 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.3337780693 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 427128926573 ps |
| CPU time | 167.6 seconds |
| Started | Feb 08 09:16:13 AM UTC 25 |
| Finished | Feb 08 09:19:04 AM UTC 25 |
| Peak memory | 199300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337780693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.rv_timer_disabled.3337780693 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1167604792 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 59286690939 ps |
| CPU time | 716.11 seconds |
| Started | Feb 08 09:16:13 AM UTC 25 |
| Finished | Feb 08 09:28:18 AM UTC 25 |
| Peak memory | 202168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167604792 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1167604792 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.3139828455 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 81871802 ps |
| CPU time | 1.01 seconds |
| Started | Feb 08 09:16:19 AM UTC 25 |
| Finished | Feb 08 09:16:21 AM UTC 25 |
| Peak memory | 198220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139828455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3139828455 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.4026498874 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 121818701667 ps |
| CPU time | 228.52 seconds |
| Started | Feb 08 09:44:04 AM UTC 25 |
| Finished | Feb 08 09:47:56 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026498874 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4026498874 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.3517092147 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 524150385462 ps |
| CPU time | 820.07 seconds |
| Started | Feb 08 09:44:11 AM UTC 25 |
| Finished | Feb 08 09:58:01 AM UTC 25 |
| Peak memory | 202048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517092147 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3517092147 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3782440230 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 57704075140 ps |
| CPU time | 333.32 seconds |
| Started | Feb 08 09:44:17 AM UTC 25 |
| Finished | Feb 08 09:49:56 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782440230 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3782440230 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.1672222995 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 14431101684 ps |
| CPU time | 49.26 seconds |
| Started | Feb 08 09:44:46 AM UTC 25 |
| Finished | Feb 08 09:45:37 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672222995 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1672222995 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.2506398275 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 39703631961 ps |
| CPU time | 489.08 seconds |
| Started | Feb 08 09:44:58 AM UTC 25 |
| Finished | Feb 08 09:53:13 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506398275 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2506398275 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.647213846 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 361280707827 ps |
| CPU time | 419.28 seconds |
| Started | Feb 08 09:45:26 AM UTC 25 |
| Finished | Feb 08 09:52:31 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647213846 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.647213846 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.1148596412 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 359612938650 ps |
| CPU time | 351.05 seconds |
| Started | Feb 08 09:45:38 AM UTC 25 |
| Finished | Feb 08 09:51:34 AM UTC 25 |
| Peak memory | 199208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148596412 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1148596412 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.1265272231 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10666030447 ps |
| CPU time | 19.83 seconds |
| Started | Feb 08 09:16:28 AM UTC 25 |
| Finished | Feb 08 09:16:50 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265272231 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.1265272231 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.2114856638 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 365144248113 ps |
| CPU time | 177.41 seconds |
| Started | Feb 08 09:16:26 AM UTC 25 |
| Finished | Feb 08 09:19:27 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114856638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.rv_timer_disabled.2114856638 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2148547401 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 563690733009 ps |
| CPU time | 392.35 seconds |
| Started | Feb 08 09:16:23 AM UTC 25 |
| Finished | Feb 08 09:23:01 AM UTC 25 |
| Peak memory | 199292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148547401 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2148547401 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.3504611819 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 55766400084 ps |
| CPU time | 66.53 seconds |
| Started | Feb 08 09:16:50 AM UTC 25 |
| Finished | Feb 08 09:17:59 AM UTC 25 |
| Peak memory | 199480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504611819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3504611819 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.2658792308 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 512800091718 ps |
| CPU time | 1147.69 seconds |
| Started | Feb 08 09:16:52 AM UTC 25 |
| Finished | Feb 08 09:36:12 AM UTC 25 |
| Peak memory | 201964 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658792308 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_t imer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.2658792308 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.1908812144 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 180909850745 ps |
| CPU time | 190.19 seconds |
| Started | Feb 08 09:45:53 AM UTC 25 |
| Finished | Feb 08 09:49:07 AM UTC 25 |
| Peak memory | 199220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908812144 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1908812144 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.279572280 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 27579121157 ps |
| CPU time | 25.74 seconds |
| Started | Feb 08 09:46:01 AM UTC 25 |
| Finished | Feb 08 09:46:29 AM UTC 25 |
| Peak memory | 199296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279572280 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.279572280 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.429072654 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 55333549350 ps |
| CPU time | 150.13 seconds |
| Started | Feb 08 09:46:15 AM UTC 25 |
| Finished | Feb 08 09:48:48 AM UTC 25 |
| Peak memory | 199360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429072654 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.429072654 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.545885873 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 689329300987 ps |
| CPU time | 2245.22 seconds |
| Started | Feb 08 09:46:18 AM UTC 25 |
| Finished | Feb 08 10:24:07 AM UTC 25 |
| Peak memory | 202052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545885873 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.545885873 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1884701703 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 92904576027 ps |
| CPU time | 424.4 seconds |
| Started | Feb 08 09:46:24 AM UTC 25 |
| Finished | Feb 08 09:53:33 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884701703 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1884701703 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.2911590636 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 205581914603 ps |
| CPU time | 298.92 seconds |
| Started | Feb 08 09:46:30 AM UTC 25 |
| Finished | Feb 08 09:51:33 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911590636 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2911590636 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.3780707220 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 723634926995 ps |
| CPU time | 226.6 seconds |
| Started | Feb 08 09:46:47 AM UTC 25 |
| Finished | Feb 08 09:50:37 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780707220 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3780707220 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.914100445 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 320608408398 ps |
| CPU time | 216.92 seconds |
| Started | Feb 08 09:47:11 AM UTC 25 |
| Finished | Feb 08 09:50:51 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914100445 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.914100445 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.4090026370 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 429640266475 ps |
| CPU time | 566.03 seconds |
| Started | Feb 08 09:16:55 AM UTC 25 |
| Finished | Feb 08 09:26:29 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090026370 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.4090026370 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.3849550854 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 326763714642 ps |
| CPU time | 133.21 seconds |
| Started | Feb 08 09:16:55 AM UTC 25 |
| Finished | Feb 08 09:19:11 AM UTC 25 |
| Peak memory | 198792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849550854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ti mer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.rv_timer_disabled.3849550854 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2582933723 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 103366199204 ps |
| CPU time | 160.85 seconds |
| Started | Feb 08 09:16:52 AM UTC 25 |
| Finished | Feb 08 09:19:37 AM UTC 25 |
| Peak memory | 199476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582933723 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2582933723 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.350309166 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 154917711 ps |
| CPU time | 1.03 seconds |
| Started | Feb 08 09:16:55 AM UTC 25 |
| Finished | Feb 08 09:16:58 AM UTC 25 |
| Peak memory | 197416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350309166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_tim er_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.350309166 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.581685547 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1014443899267 ps |
| CPU time | 570.42 seconds |
| Started | Feb 08 09:17:05 AM UTC 25 |
| Finished | Feb 08 09:26:43 AM UTC 25 |
| Peak memory | 199284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581685547 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_ti mer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.581685547 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.1193984822 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 54332058463 ps |
| CPU time | 306.45 seconds |
| Started | Feb 08 09:47:33 AM UTC 25 |
| Finished | Feb 08 09:52:44 AM UTC 25 |
| Peak memory | 199216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193984822 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1193984822 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2310305784 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 158757088508 ps |
| CPU time | 431.21 seconds |
| Started | Feb 08 09:47:35 AM UTC 25 |
| Finished | Feb 08 09:54:52 AM UTC 25 |
| Peak memory | 199280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310305784 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2310305784 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.1435666993 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 163112598063 ps |
| CPU time | 264.76 seconds |
| Started | Feb 08 09:47:42 AM UTC 25 |
| Finished | Feb 08 09:52:11 AM UTC 25 |
| Peak memory | 199212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435666993 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1435666993 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.145196029 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 38513054660 ps |
| CPU time | 122.72 seconds |
| Started | Feb 08 09:47:53 AM UTC 25 |
| Finished | Feb 08 09:49:59 AM UTC 25 |
| Peak memory | 199424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145196029 -assert nopostproc +UVM_TESTNAME=rv_timer_b ase_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.145196029 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.2461731450 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 813097782863 ps |
| CPU time | 764.66 seconds |
| Started | Feb 08 09:47:56 AM UTC 25 |
| Finished | Feb 08 10:00:49 AM UTC 25 |
| Peak memory | 202048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461731450 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2461731450 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.2836603984 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 57969587255 ps |
| CPU time | 241.03 seconds |
| Started | Feb 08 09:48:34 AM UTC 25 |
| Finished | Feb 08 09:52:38 AM UTC 25 |
| Peak memory | 199420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836603984 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2836603984 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.83027052 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 32974181754 ps |
| CPU time | 38.78 seconds |
| Started | Feb 08 09:48:49 AM UTC 25 |
| Finished | Feb 08 09:49:29 AM UTC 25 |
| Peak memory | 199224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83027052 -assert nopostproc +UVM_TESTNAME=rv_timer_ba se_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.83027052 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2248847016 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 289713836873 ps |
| CPU time | 622.27 seconds |
| Started | Feb 08 09:48:50 AM UTC 25 |
| Finished | Feb 08 09:59:20 AM UTC 25 |
| Peak memory | 201968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248847016 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2248847016 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.1355961521 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 83932970485 ps |
| CPU time | 614.28 seconds |
| Started | Feb 08 09:48:53 AM UTC 25 |
| Finished | Feb 08 09:59:14 AM UTC 25 |
| Peak memory | 199288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355961521 -assert nopostproc +UVM_TESTNAME=rv_timer_ base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1355961521 |
| Directory | /workspaces/repo/scratch/os_regression/rv_timer-sim-vcs/98.rv_timer_random/latest |
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