Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 585
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1336170137 Apr 18 12:23:49 PM PDT 24 Apr 18 12:23:50 PM PDT 24 46623857 ps
T509 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2255038149 Apr 18 12:23:08 PM PDT 24 Apr 18 12:23:09 PM PDT 24 57174183 ps
T73 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2066402588 Apr 18 12:20:54 PM PDT 24 Apr 18 12:20:55 PM PDT 24 15421473 ps
T510 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.826120084 Apr 18 12:22:45 PM PDT 24 Apr 18 12:22:47 PM PDT 24 143338818 ps
T511 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.758046066 Apr 18 12:17:56 PM PDT 24 Apr 18 12:17:58 PM PDT 24 29963773 ps
T512 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1341499559 Apr 18 12:22:58 PM PDT 24 Apr 18 12:23:00 PM PDT 24 41890024 ps
T513 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2243748957 Apr 18 12:19:26 PM PDT 24 Apr 18 12:19:28 PM PDT 24 123443744 ps
T514 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.874954105 Apr 18 12:19:43 PM PDT 24 Apr 18 12:19:45 PM PDT 24 147599410 ps
T515 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1844781692 Apr 18 12:23:02 PM PDT 24 Apr 18 12:23:05 PM PDT 24 157103630 ps
T516 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.306083465 Apr 18 12:23:31 PM PDT 24 Apr 18 12:23:33 PM PDT 24 54330842 ps
T74 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1862935932 Apr 18 12:23:31 PM PDT 24 Apr 18 12:23:33 PM PDT 24 45488429 ps
T517 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3373443218 Apr 18 12:18:45 PM PDT 24 Apr 18 12:18:46 PM PDT 24 16669272 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3731246884 Apr 18 12:19:42 PM PDT 24 Apr 18 12:19:44 PM PDT 24 442771751 ps
T519 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.591710235 Apr 18 12:21:16 PM PDT 24 Apr 18 12:21:17 PM PDT 24 15641207 ps
T520 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3818786081 Apr 18 12:21:34 PM PDT 24 Apr 18 12:21:36 PM PDT 24 31373819 ps
T76 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3354867959 Apr 18 12:23:50 PM PDT 24 Apr 18 12:23:53 PM PDT 24 21737435 ps
T521 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3503364943 Apr 18 12:23:44 PM PDT 24 Apr 18 12:23:46 PM PDT 24 38668161 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.988947820 Apr 18 12:22:39 PM PDT 24 Apr 18 12:22:40 PM PDT 24 64632959 ps
T523 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2543917286 Apr 18 12:19:48 PM PDT 24 Apr 18 12:19:49 PM PDT 24 27327482 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.402570569 Apr 18 12:21:40 PM PDT 24 Apr 18 12:21:41 PM PDT 24 140944381 ps
T525 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2732301346 Apr 18 12:21:22 PM PDT 24 Apr 18 12:21:23 PM PDT 24 275330606 ps
T526 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2268163668 Apr 18 12:20:13 PM PDT 24 Apr 18 12:20:16 PM PDT 24 40097623 ps
T527 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3105302749 Apr 18 12:17:56 PM PDT 24 Apr 18 12:17:58 PM PDT 24 39158647 ps
T528 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.345985662 Apr 18 12:19:59 PM PDT 24 Apr 18 12:20:02 PM PDT 24 72685671 ps
T529 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3729935657 Apr 18 12:22:18 PM PDT 24 Apr 18 12:22:19 PM PDT 24 34671517 ps
T530 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3587130238 Apr 18 12:20:47 PM PDT 24 Apr 18 12:20:48 PM PDT 24 58691655 ps
T531 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2572822680 Apr 18 12:21:49 PM PDT 24 Apr 18 12:21:51 PM PDT 24 20783923 ps
T532 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.829307111 Apr 18 12:20:12 PM PDT 24 Apr 18 12:20:14 PM PDT 24 49842527 ps
T533 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1669173642 Apr 18 12:20:08 PM PDT 24 Apr 18 12:20:11 PM PDT 24 284288866 ps
T534 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3614715392 Apr 18 12:23:43 PM PDT 24 Apr 18 12:23:45 PM PDT 24 1394291918 ps
T535 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1187347405 Apr 18 12:23:08 PM PDT 24 Apr 18 12:23:09 PM PDT 24 49933315 ps
T536 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3985833118 Apr 18 12:20:49 PM PDT 24 Apr 18 12:20:50 PM PDT 24 22931013 ps
T537 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.621802858 Apr 18 12:23:44 PM PDT 24 Apr 18 12:23:46 PM PDT 24 85276473 ps
T538 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1201988867 Apr 18 12:23:44 PM PDT 24 Apr 18 12:23:46 PM PDT 24 28140886 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2706130120 Apr 18 12:20:03 PM PDT 24 Apr 18 12:20:05 PM PDT 24 93776843 ps
T75 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.932507104 Apr 18 12:20:13 PM PDT 24 Apr 18 12:20:15 PM PDT 24 22605962 ps
T540 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3902717257 Apr 18 12:23:13 PM PDT 24 Apr 18 12:23:14 PM PDT 24 14558850 ps
T541 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.544823441 Apr 18 12:20:10 PM PDT 24 Apr 18 12:20:12 PM PDT 24 46446748 ps
T542 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.63233623 Apr 18 12:23:08 PM PDT 24 Apr 18 12:23:12 PM PDT 24 197576626 ps
T543 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.957837670 Apr 18 12:22:54 PM PDT 24 Apr 18 12:22:57 PM PDT 24 35249955 ps
T544 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1237448624 Apr 18 12:22:54 PM PDT 24 Apr 18 12:22:57 PM PDT 24 60887169 ps
T545 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3769487450 Apr 18 12:22:58 PM PDT 24 Apr 18 12:23:00 PM PDT 24 71513637 ps
T546 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3457259602 Apr 18 12:23:12 PM PDT 24 Apr 18 12:23:13 PM PDT 24 14133847 ps
T547 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.362243859 Apr 18 12:24:38 PM PDT 24 Apr 18 12:24:40 PM PDT 24 11559960 ps
T548 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1645400292 Apr 18 12:20:03 PM PDT 24 Apr 18 12:20:04 PM PDT 24 14939959 ps
T549 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1625560782 Apr 18 12:20:49 PM PDT 24 Apr 18 12:20:54 PM PDT 24 245124685 ps
T550 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1848218224 Apr 18 12:19:07 PM PDT 24 Apr 18 12:19:08 PM PDT 24 156309684 ps
T551 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1183967318 Apr 18 12:19:55 PM PDT 24 Apr 18 12:19:57 PM PDT 24 81579599 ps
T552 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.674465721 Apr 18 12:19:09 PM PDT 24 Apr 18 12:19:11 PM PDT 24 187855166 ps
T553 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.516510135 Apr 18 12:19:27 PM PDT 24 Apr 18 12:19:29 PM PDT 24 24448897 ps
T554 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2493022008 Apr 18 12:23:11 PM PDT 24 Apr 18 12:23:12 PM PDT 24 38494075 ps
T555 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.362598508 Apr 18 12:23:45 PM PDT 24 Apr 18 12:23:47 PM PDT 24 27891447 ps
T556 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2325226726 Apr 18 12:22:43 PM PDT 24 Apr 18 12:22:45 PM PDT 24 27895536 ps
T557 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.828308815 Apr 18 12:17:53 PM PDT 24 Apr 18 12:17:54 PM PDT 24 92893724 ps
T558 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2193145956 Apr 18 12:18:50 PM PDT 24 Apr 18 12:18:51 PM PDT 24 16397537 ps
T97 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.157026484 Apr 18 12:20:13 PM PDT 24 Apr 18 12:20:16 PM PDT 24 80910204 ps
T559 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2700752462 Apr 18 12:24:29 PM PDT 24 Apr 18 12:24:31 PM PDT 24 22587572 ps
T77 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1243667172 Apr 18 12:23:07 PM PDT 24 Apr 18 12:23:08 PM PDT 24 135516450 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3546263772 Apr 18 12:19:01 PM PDT 24 Apr 18 12:19:03 PM PDT 24 32689950 ps
T561 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4213767949 Apr 18 12:22:40 PM PDT 24 Apr 18 12:22:41 PM PDT 24 15043746 ps
T562 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.698054852 Apr 18 12:23:31 PM PDT 24 Apr 18 12:23:34 PM PDT 24 180854588 ps
T563 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1032594132 Apr 18 12:23:44 PM PDT 24 Apr 18 12:23:46 PM PDT 24 49822152 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.856819284 Apr 18 12:18:51 PM PDT 24 Apr 18 12:18:53 PM PDT 24 63496977 ps
T565 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2570133975 Apr 18 12:22:54 PM PDT 24 Apr 18 12:22:57 PM PDT 24 52685838 ps
T566 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2642417426 Apr 18 12:23:44 PM PDT 24 Apr 18 12:23:46 PM PDT 24 28826662 ps
T567 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3313072332 Apr 18 12:19:58 PM PDT 24 Apr 18 12:20:00 PM PDT 24 117160403 ps
T568 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2941375829 Apr 18 12:22:53 PM PDT 24 Apr 18 12:22:55 PM PDT 24 23360646 ps
T569 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4085594980 Apr 18 12:22:17 PM PDT 24 Apr 18 12:22:19 PM PDT 24 247476077 ps
T570 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.201780874 Apr 18 12:19:19 PM PDT 24 Apr 18 12:19:21 PM PDT 24 34828609 ps
T571 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1707183015 Apr 18 12:22:39 PM PDT 24 Apr 18 12:22:40 PM PDT 24 24661062 ps
T572 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1735172481 Apr 18 12:20:23 PM PDT 24 Apr 18 12:20:24 PM PDT 24 32903986 ps
T573 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.371925411 Apr 18 12:23:16 PM PDT 24 Apr 18 12:23:18 PM PDT 24 166140981 ps
T574 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2055545163 Apr 18 12:23:07 PM PDT 24 Apr 18 12:23:08 PM PDT 24 46307164 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1471169852 Apr 18 12:17:55 PM PDT 24 Apr 18 12:17:58 PM PDT 24 358444838 ps
T576 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2833427877 Apr 18 12:21:04 PM PDT 24 Apr 18 12:21:05 PM PDT 24 32628816 ps
T577 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2984370124 Apr 18 12:20:28 PM PDT 24 Apr 18 12:20:29 PM PDT 24 36783537 ps
T578 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.635057861 Apr 18 12:22:40 PM PDT 24 Apr 18 12:22:41 PM PDT 24 14057483 ps
T579 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1920676449 Apr 18 12:23:55 PM PDT 24 Apr 18 12:23:56 PM PDT 24 27243810 ps
T580 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.657989355 Apr 18 12:21:53 PM PDT 24 Apr 18 12:21:54 PM PDT 24 744224942 ps
T581 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2001433181 Apr 18 12:20:12 PM PDT 24 Apr 18 12:20:13 PM PDT 24 13716766 ps
T78 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1738379798 Apr 18 12:23:50 PM PDT 24 Apr 18 12:23:54 PM PDT 24 66147675 ps
T582 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.317535574 Apr 18 12:19:48 PM PDT 24 Apr 18 12:19:50 PM PDT 24 37782557 ps
T583 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.489615697 Apr 18 12:20:28 PM PDT 24 Apr 18 12:20:29 PM PDT 24 12818701 ps
T584 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2487234595 Apr 18 12:23:12 PM PDT 24 Apr 18 12:23:14 PM PDT 24 31563720 ps
T585 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.655177261 Apr 18 12:22:39 PM PDT 24 Apr 18 12:22:40 PM PDT 24 57701311 ps

Test location /workspace/coverage/default/166.rv_timer_random.1432881864
Short name T1
Test name
Test status
Simulation time 48750259939 ps
CPU time 263.95 seconds
Started Apr 18 12:23:46 PM PDT 24
Finished Apr 18 12:28:11 PM PDT 24
Peak memory 190616 kb
Host smart-dd4fc881-0085-4801-8397-0edbb6f2bf95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432881864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1432881864
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2990494220
Short name T14
Test name
Test status
Simulation time 102855314097 ps
CPU time 722.68 seconds
Started Apr 18 12:21:27 PM PDT 24
Finished Apr 18 12:33:31 PM PDT 24
Peak memory 207660 kb
Host smart-b5b63e25-d207-432b-bbe1-0c778b4f0d70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990494220 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2990494220
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_timer_random.390859002
Short name T20
Test name
Test status
Simulation time 132465288187 ps
CPU time 431.32 seconds
Started Apr 18 12:22:42 PM PDT 24
Finished Apr 18 12:29:54 PM PDT 24
Peak memory 190212 kb
Host smart-7cfecc52-f298-4ade-9261-84a15e3c7ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390859002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.390859002
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3957655674
Short name T30
Test name
Test status
Simulation time 861660306752 ps
CPU time 1106.72 seconds
Started Apr 18 12:23:43 PM PDT 24
Finished Apr 18 12:42:11 PM PDT 24
Peak memory 188920 kb
Host smart-770b7510-b45f-464b-ba84-7e52238fa895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957655674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3957655674
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3091797309
Short name T26
Test name
Test status
Simulation time 382115333 ps
CPU time 1.08 seconds
Started Apr 18 12:23:57 PM PDT 24
Finished Apr 18 12:23:59 PM PDT 24
Peak memory 194484 kb
Host smart-cfa4ab3d-84b4-4556-869d-6492f3ab1378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091797309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3091797309
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3658349603
Short name T135
Test name
Test status
Simulation time 1150668448042 ps
CPU time 1817.19 seconds
Started Apr 18 12:22:49 PM PDT 24
Finished Apr 18 12:53:07 PM PDT 24
Peak memory 190124 kb
Host smart-d3eb3c66-e653-45be-bcbc-61dd34ad7cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658349603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3658349603
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2405238288
Short name T177
Test name
Test status
Simulation time 647984414494 ps
CPU time 1583.21 seconds
Started Apr 18 12:21:42 PM PDT 24
Finished Apr 18 12:48:06 PM PDT 24
Peak memory 190808 kb
Host smart-f22ec4b1-cdda-4e51-a00a-ecb49ff0c251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405238288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2405238288
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2870512272
Short name T148
Test name
Test status
Simulation time 725050602885 ps
CPU time 1291.37 seconds
Started Apr 18 12:22:57 PM PDT 24
Finished Apr 18 12:44:29 PM PDT 24
Peak memory 190804 kb
Host smart-c1a497cc-eaef-488c-bbdf-8b7eca315a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870512272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2870512272
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3928316156
Short name T218
Test name
Test status
Simulation time 729368708793 ps
CPU time 1132.4 seconds
Started Apr 18 12:22:38 PM PDT 24
Finished Apr 18 12:41:31 PM PDT 24
Peak memory 191884 kb
Host smart-704f166b-db7d-422f-b40d-44470d97dba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928316156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3928316156
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3569188050
Short name T106
Test name
Test status
Simulation time 4120273633200 ps
CPU time 2115.24 seconds
Started Apr 18 12:21:25 PM PDT 24
Finished Apr 18 12:56:41 PM PDT 24
Peak memory 190616 kb
Host smart-13c24b17-2cff-4c2f-b8b7-12a88ab44786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569188050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3569188050
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.1147761464
Short name T21
Test name
Test status
Simulation time 471676387666 ps
CPU time 202.89 seconds
Started Apr 18 12:23:32 PM PDT 24
Finished Apr 18 12:26:56 PM PDT 24
Peak memory 194120 kb
Host smart-e932e54d-ebe9-4222-b5f0-79c23a7a7cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147761464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1147761464
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.61140333
Short name T197
Test name
Test status
Simulation time 934236665929 ps
CPU time 589.22 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 190388 kb
Host smart-cc6d331c-dbb0-4dac-aac1-2a7c4381e1b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61140333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.61140333
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.936161684
Short name T222
Test name
Test status
Simulation time 257020653417 ps
CPU time 662.72 seconds
Started Apr 18 12:24:28 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 194096 kb
Host smart-6b67adf4-c615-4ecf-9d76-7789d86def2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936161684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
936161684
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2567925684
Short name T16
Test name
Test status
Simulation time 63245450 ps
CPU time 0.87 seconds
Started Apr 18 12:21:38 PM PDT 24
Finished Apr 18 12:21:40 PM PDT 24
Peak memory 212872 kb
Host smart-d49d5c50-04f5-4eee-92c0-5a1f30a46a2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567925684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2567925684
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4101207063
Short name T213
Test name
Test status
Simulation time 548784009344 ps
CPU time 708.94 seconds
Started Apr 18 12:22:49 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 190140 kb
Host smart-5e88c21c-a70a-44d1-be1d-47cb8f918612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101207063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4101207063
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.3857471436
Short name T158
Test name
Test status
Simulation time 146769490913 ps
CPU time 241.86 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:27:32 PM PDT 24
Peak memory 190384 kb
Host smart-163e9a1b-de4d-429f-a133-a22ac1baae08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857471436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3857471436
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.1545137082
Short name T210
Test name
Test status
Simulation time 157306306787 ps
CPU time 285.33 seconds
Started Apr 18 12:23:24 PM PDT 24
Finished Apr 18 12:28:10 PM PDT 24
Peak memory 190360 kb
Host smart-98110af3-8716-49c3-84c3-7dc0c607739b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545137082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1545137082
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2753887132
Short name T57
Test name
Test status
Simulation time 893759037578 ps
CPU time 1299.86 seconds
Started Apr 18 12:23:37 PM PDT 24
Finished Apr 18 12:45:18 PM PDT 24
Peak memory 189836 kb
Host smart-487e877c-e701-4077-aa45-a7fdd2f4f41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753887132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2753887132
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3564104914
Short name T298
Test name
Test status
Simulation time 217731921522 ps
CPU time 430.18 seconds
Started Apr 18 12:20:22 PM PDT 24
Finished Apr 18 12:27:33 PM PDT 24
Peak memory 190740 kb
Host smart-ab849286-659f-4ce6-a6c6-b2daea13ddd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564104914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3564104914
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.3736141704
Short name T248
Test name
Test status
Simulation time 198074563520 ps
CPU time 460.68 seconds
Started Apr 18 12:23:40 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 190560 kb
Host smart-a7c461cf-92a7-405d-932d-a27ef08dc078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736141704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3736141704
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3696503844
Short name T182
Test name
Test status
Simulation time 381381422177 ps
CPU time 620.65 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 194440 kb
Host smart-b19c7051-24ed-42c3-8209-c8383940d0ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696503844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3696503844
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/93.rv_timer_random.530056354
Short name T169
Test name
Test status
Simulation time 104747073323 ps
CPU time 370.72 seconds
Started Apr 18 12:23:22 PM PDT 24
Finished Apr 18 12:29:33 PM PDT 24
Peak memory 190556 kb
Host smart-31849cce-f196-4734-87f4-826de7300a1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530056354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.530056354
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3565602092
Short name T140
Test name
Test status
Simulation time 2399828710229 ps
CPU time 1144.02 seconds
Started Apr 18 12:24:38 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 194756 kb
Host smart-ff4f570c-bdb7-461f-ae9e-d9e79e1e8b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565602092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3565602092
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2440341741
Short name T256
Test name
Test status
Simulation time 634998129769 ps
CPU time 290.59 seconds
Started Apr 18 12:23:32 PM PDT 24
Finished Apr 18 12:28:23 PM PDT 24
Peak memory 190632 kb
Host smart-209884c0-5612-4260-8305-a90d7cb4b86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440341741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2440341741
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3083029362
Short name T242
Test name
Test status
Simulation time 346619056231 ps
CPU time 1433.17 seconds
Started Apr 18 12:24:28 PM PDT 24
Finished Apr 18 12:48:22 PM PDT 24
Peak memory 190428 kb
Host smart-390d29a4-a3c5-4c70-a1fc-95c83ed3192f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083029362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3083029362
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.2406294125
Short name T23
Test name
Test status
Simulation time 194649553927 ps
CPU time 165.04 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:26:36 PM PDT 24
Peak memory 190636 kb
Host smart-e4fb68c5-3108-4651-80ae-aa4665d1f798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406294125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2406294125
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.4042450961
Short name T285
Test name
Test status
Simulation time 108174094958 ps
CPU time 591.38 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 190636 kb
Host smart-1b568663-059b-4369-bce0-d008b1a33edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042450961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4042450961
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3632890436
Short name T250
Test name
Test status
Simulation time 111153210355 ps
CPU time 184.47 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:26:53 PM PDT 24
Peak memory 190564 kb
Host smart-061cce13-b7bf-4f39-9425-6ee9f8ca7d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632890436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3632890436
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2783655113
Short name T262
Test name
Test status
Simulation time 734217234212 ps
CPU time 601.92 seconds
Started Apr 18 12:21:12 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 192036 kb
Host smart-f1155c3b-fd2c-48a4-947a-47d2ac19d087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783655113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2783655113
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2909513267
Short name T183
Test name
Test status
Simulation time 449639399207 ps
CPU time 1756.81 seconds
Started Apr 18 12:23:48 PM PDT 24
Finished Apr 18 12:53:06 PM PDT 24
Peak memory 190636 kb
Host smart-b3a54edb-6930-450c-bd32-9321831e625c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909513267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2909513267
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/79.rv_timer_random.3394856324
Short name T224
Test name
Test status
Simulation time 99359619629 ps
CPU time 963.26 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:39:32 PM PDT 24
Peak memory 190484 kb
Host smart-a316a0ae-c357-4783-9b9c-2983e79f6203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394856324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3394856324
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3619697364
Short name T234
Test name
Test status
Simulation time 179681744848 ps
CPU time 486.59 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 190624 kb
Host smart-d325ad35-faac-4288-882c-59bf1166e597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619697364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3619697364
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.609514295
Short name T174
Test name
Test status
Simulation time 140854979682 ps
CPU time 450.35 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 190596 kb
Host smart-3aa3b6a6-979b-46d7-ab65-8574ff2d4e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609514295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.609514295
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1243667172
Short name T77
Test name
Test status
Simulation time 135516450 ps
CPU time 0.59 seconds
Started Apr 18 12:23:07 PM PDT 24
Finished Apr 18 12:23:08 PM PDT 24
Peak memory 181412 kb
Host smart-16000d04-800f-4a08-8991-ba50927eba68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243667172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1243667172
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/129.rv_timer_random.4233316888
Short name T324
Test name
Test status
Simulation time 419507524896 ps
CPU time 1154.4 seconds
Started Apr 18 12:23:27 PM PDT 24
Finished Apr 18 12:42:42 PM PDT 24
Peak memory 190676 kb
Host smart-7ddd8aa6-a070-42ca-816b-9795380079cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233316888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4233316888
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4272439382
Short name T215
Test name
Test status
Simulation time 670884657612 ps
CPU time 1227.53 seconds
Started Apr 18 12:22:48 PM PDT 24
Finished Apr 18 12:43:17 PM PDT 24
Peak memory 187796 kb
Host smart-a5d6f636-239b-455f-a346-3948cc5aad19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272439382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4272439382
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/156.rv_timer_random.2156828085
Short name T208
Test name
Test status
Simulation time 1500813270896 ps
CPU time 564.45 seconds
Started Apr 18 12:23:35 PM PDT 24
Finished Apr 18 12:33:01 PM PDT 24
Peak memory 190552 kb
Host smart-01c471b4-aa2b-4f23-99a4-b2bce39e1a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156828085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2156828085
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.912415347
Short name T143
Test name
Test status
Simulation time 163887167392 ps
CPU time 745.31 seconds
Started Apr 18 12:22:56 PM PDT 24
Finished Apr 18 12:35:23 PM PDT 24
Peak memory 189828 kb
Host smart-d174f4aa-3ac7-4a26-8721-d320e3dea3ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912415347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.912415347
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1049709396
Short name T134
Test name
Test status
Simulation time 167778517868 ps
CPU time 384.6 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:29:53 PM PDT 24
Peak memory 190460 kb
Host smart-0a295f1c-91dc-411a-bd7e-8ed3b94f35cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049709396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1049709396
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.741390427
Short name T34
Test name
Test status
Simulation time 165645698163 ps
CPU time 694.94 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:35:29 PM PDT 24
Peak memory 212072 kb
Host smart-25021459-8e49-474c-a23f-5f359288a25c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741390427 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.741390427
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.2750483570
Short name T112
Test name
Test status
Simulation time 188704093483 ps
CPU time 171.79 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:26:21 PM PDT 24
Peak memory 192956 kb
Host smart-971dc62a-51d5-46e8-ba2a-a997c88d6b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750483570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2750483570
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.2131333179
Short name T192
Test name
Test status
Simulation time 165239168368 ps
CPU time 597.37 seconds
Started Apr 18 12:23:32 PM PDT 24
Finished Apr 18 12:33:30 PM PDT 24
Peak memory 190632 kb
Host smart-928fec63-b8e3-4911-a2db-2cedf66ed900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131333179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2131333179
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.874410745
Short name T104
Test name
Test status
Simulation time 599630813673 ps
CPU time 877.13 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 190564 kb
Host smart-29ee6940-568d-4cae-b014-46a8ecbb3340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874410745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.874410745
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4073998461
Short name T114
Test name
Test status
Simulation time 214334887426 ps
CPU time 745.75 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:36:11 PM PDT 24
Peak memory 190548 kb
Host smart-82783de1-676b-4ccd-b571-bbbcc84351c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073998461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4073998461
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3224762048
Short name T101
Test name
Test status
Simulation time 688875196647 ps
CPU time 561.15 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:33:15 PM PDT 24
Peak memory 190368 kb
Host smart-6ab739f4-9bd5-44dd-ae15-555a507a3b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224762048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3224762048
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.2227650260
Short name T252
Test name
Test status
Simulation time 1015059621320 ps
CPU time 1344.21 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:46:17 PM PDT 24
Peak memory 190592 kb
Host smart-46a3a75c-60bb-4fc6-be72-d831de8de736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227650260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2227650260
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2071120406
Short name T287
Test name
Test status
Simulation time 593906678847 ps
CPU time 1080.89 seconds
Started Apr 18 12:18:41 PM PDT 24
Finished Apr 18 12:36:44 PM PDT 24
Peak memory 181948 kb
Host smart-75b62876-7d9d-434e-b440-add355a3d9d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071120406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2071120406
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.602721965
Short name T176
Test name
Test status
Simulation time 2347112773174 ps
CPU time 997.12 seconds
Started Apr 18 12:22:38 PM PDT 24
Finished Apr 18 12:39:16 PM PDT 24
Peak memory 193184 kb
Host smart-57345f67-e1ff-454d-8bca-b2b1b2ca2e40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602721965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
602721965
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_random.2437179548
Short name T211
Test name
Test status
Simulation time 543980608631 ps
CPU time 250.33 seconds
Started Apr 18 12:22:52 PM PDT 24
Finished Apr 18 12:27:04 PM PDT 24
Peak memory 182428 kb
Host smart-93b96e0a-6570-445a-b04d-b9aab6ad1b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437179548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2437179548
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1426446572
Short name T3
Test name
Test status
Simulation time 186178453782 ps
CPU time 609.83 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:33:39 PM PDT 24
Peak memory 190632 kb
Host smart-a310c70c-40f6-4b93-83b8-83368b11d07e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426446572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1426446572
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3087540459
Short name T261
Test name
Test status
Simulation time 233284083026 ps
CPU time 337.34 seconds
Started Apr 18 12:17:55 PM PDT 24
Finished Apr 18 12:23:33 PM PDT 24
Peak memory 189584 kb
Host smart-b9c46a95-2482-4d3a-84b5-cbd2888ceebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087540459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3087540459
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1077163959
Short name T180
Test name
Test status
Simulation time 161161034515 ps
CPU time 382.49 seconds
Started Apr 18 12:23:33 PM PDT 24
Finished Apr 18 12:29:56 PM PDT 24
Peak memory 190612 kb
Host smart-366db420-1c36-4777-b2fc-deb1babeaa2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077163959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1077163959
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3127466435
Short name T58
Test name
Test status
Simulation time 73724381606 ps
CPU time 176.09 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:26:38 PM PDT 24
Peak memory 190804 kb
Host smart-bd09a87c-8a8f-43e9-b9ab-dcebfe49e591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127466435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3127466435
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.275314841
Short name T199
Test name
Test status
Simulation time 772265597231 ps
CPU time 364.24 seconds
Started Apr 18 12:23:51 PM PDT 24
Finished Apr 18 12:29:57 PM PDT 24
Peak memory 182172 kb
Host smart-cf46c670-b886-4b9c-bbb2-0583a1cfdb98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275314841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.275314841
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2925527654
Short name T233
Test name
Test status
Simulation time 1006482103641 ps
CPU time 528.37 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:31:40 PM PDT 24
Peak memory 190444 kb
Host smart-232073c6-7f01-4c81-a2f7-c7b639fb9220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925527654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2925527654
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1020726369
Short name T168
Test name
Test status
Simulation time 710979504845 ps
CPU time 2461.63 seconds
Started Apr 18 12:22:51 PM PDT 24
Finished Apr 18 01:03:54 PM PDT 24
Peak memory 190736 kb
Host smart-0f4562dd-5844-439e-a7d0-091aec15f40e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020726369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1020726369
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2354369129
Short name T153
Test name
Test status
Simulation time 118373466520 ps
CPU time 175.56 seconds
Started Apr 18 12:23:19 PM PDT 24
Finished Apr 18 12:26:15 PM PDT 24
Peak memory 190736 kb
Host smart-c7ea2c17-1cc5-49af-a9cb-d769988f7a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354369129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2354369129
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1410934436
Short name T204
Test name
Test status
Simulation time 122763081196 ps
CPU time 185.99 seconds
Started Apr 18 12:24:32 PM PDT 24
Finished Apr 18 12:27:38 PM PDT 24
Peak memory 190324 kb
Host smart-f81a4ec1-8737-4cd0-9a80-e1d9b60e0983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410934436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1410934436
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3304765729
Short name T145
Test name
Test status
Simulation time 105960923251 ps
CPU time 176.71 seconds
Started Apr 18 12:24:31 PM PDT 24
Finished Apr 18 12:27:29 PM PDT 24
Peak memory 190324 kb
Host smart-b868a865-f2e8-45cd-97a0-8c18def4fd0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304765729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3304765729
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.376358464
Short name T128
Test name
Test status
Simulation time 372835909346 ps
CPU time 166.42 seconds
Started Apr 18 12:22:27 PM PDT 24
Finished Apr 18 12:25:14 PM PDT 24
Peak memory 190640 kb
Host smart-b8be395b-6ec2-4351-a372-e98e85523ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376358464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.376358464
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3402740079
Short name T87
Test name
Test status
Simulation time 29184493 ps
CPU time 0.69 seconds
Started Apr 18 12:23:18 PM PDT 24
Finished Apr 18 12:23:19 PM PDT 24
Peak memory 192900 kb
Host smart-00d41fbd-cc1c-46a8-b583-80ea2ca8db20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402740079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3402740079
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3404301757
Short name T259
Test name
Test status
Simulation time 461686527567 ps
CPU time 196.66 seconds
Started Apr 18 12:23:05 PM PDT 24
Finished Apr 18 12:26:23 PM PDT 24
Peak memory 192688 kb
Host smart-d6b51d79-9dc3-40b9-9fda-6614984689c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404301757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3404301757
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/117.rv_timer_random.3621111506
Short name T295
Test name
Test status
Simulation time 520625624317 ps
CPU time 565.24 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:32:54 PM PDT 24
Peak memory 190812 kb
Host smart-c1cfb65b-c49c-44b0-92db-73bb883643ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621111506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3621111506
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2957529126
Short name T320
Test name
Test status
Simulation time 1639700946986 ps
CPU time 690.75 seconds
Started Apr 18 12:23:27 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 191072 kb
Host smart-15620aaf-cfe5-4ea8-8f26-747a4d722563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957529126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2957529126
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.4095274159
Short name T59
Test name
Test status
Simulation time 63605120903 ps
CPU time 113.88 seconds
Started Apr 18 12:23:49 PM PDT 24
Finished Apr 18 12:25:43 PM PDT 24
Peak memory 192888 kb
Host smart-7901cc03-2426-48ae-864a-6763ac65ee48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095274159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.4095274159
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1463821448
Short name T227
Test name
Test status
Simulation time 106723129421 ps
CPU time 510.84 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 190664 kb
Host smart-33b06cd4-9896-4f8e-86f7-fa61af39f73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463821448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1463821448
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3887106510
Short name T165
Test name
Test status
Simulation time 254139846151 ps
CPU time 400.07 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:30:27 PM PDT 24
Peak memory 190604 kb
Host smart-f10c3cab-d955-478f-adcd-2a6c54868438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887106510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3887106510
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.359174863
Short name T162
Test name
Test status
Simulation time 606855049585 ps
CPU time 314.68 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:28:57 PM PDT 24
Peak memory 190688 kb
Host smart-8c52600b-64c4-4628-a201-3f5926f2c9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359174863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.359174863
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1345395583
Short name T81
Test name
Test status
Simulation time 160917389666 ps
CPU time 70.64 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:25:02 PM PDT 24
Peak memory 190596 kb
Host smart-9273b875-19e0-48a3-a53a-f98f3eb0d665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345395583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1345395583
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1779292489
Short name T38
Test name
Test status
Simulation time 1824661148253 ps
CPU time 3127.46 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 01:15:59 PM PDT 24
Peak memory 192960 kb
Host smart-33935efd-08b3-4578-83ea-ea2f8ccae93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779292489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1779292489
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1773015049
Short name T288
Test name
Test status
Simulation time 120134043581 ps
CPU time 474.93 seconds
Started Apr 18 12:23:46 PM PDT 24
Finished Apr 18 12:31:43 PM PDT 24
Peak memory 182448 kb
Host smart-d302857c-0744-40cc-bf9d-026818d093f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773015049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1773015049
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3248739294
Short name T306
Test name
Test status
Simulation time 5633736925 ps
CPU time 3.33 seconds
Started Apr 18 12:19:01 PM PDT 24
Finished Apr 18 12:19:05 PM PDT 24
Peak memory 190624 kb
Host smart-d19c9e26-5012-48b3-af92-c064653c356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248739294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3248739294
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_random.1651904768
Short name T115
Test name
Test status
Simulation time 72650406470 ps
CPU time 142.77 seconds
Started Apr 18 12:22:41 PM PDT 24
Finished Apr 18 12:25:06 PM PDT 24
Peak memory 189836 kb
Host smart-bc40dd29-499f-411a-86ca-14a34168f3ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651904768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1651904768
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1004065932
Short name T53
Test name
Test status
Simulation time 255144227725 ps
CPU time 532.24 seconds
Started Apr 18 12:23:16 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 194244 kb
Host smart-2ed1eab1-6809-4ee4-bb28-e270c4a121f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004065932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1004065932
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2453541345
Short name T42
Test name
Test status
Simulation time 759682160887 ps
CPU time 392.39 seconds
Started Apr 18 12:23:04 PM PDT 24
Finished Apr 18 12:29:37 PM PDT 24
Peak memory 182152 kb
Host smart-d3b7c582-620c-4617-a777-7415412c438e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453541345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2453541345
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1275062976
Short name T326
Test name
Test status
Simulation time 506653926433 ps
CPU time 426.02 seconds
Started Apr 18 12:23:24 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 193772 kb
Host smart-f0bc2d54-8bb8-4e11-808b-c5fe059f30ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275062976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1275062976
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_random.1286471170
Short name T240
Test name
Test status
Simulation time 107975940293 ps
CPU time 170.53 seconds
Started Apr 18 12:24:27 PM PDT 24
Finished Apr 18 12:27:18 PM PDT 24
Peak memory 190428 kb
Host smart-cca7e652-54d3-4957-96f2-39278604fa41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286471170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1286471170
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1476400609
Short name T55
Test name
Test status
Simulation time 1126340212233 ps
CPU time 1106.56 seconds
Started Apr 18 12:23:43 PM PDT 24
Finished Apr 18 12:42:11 PM PDT 24
Peak memory 189060 kb
Host smart-14327fc2-2e7f-4726-af74-6b2190fcb2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476400609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1476400609
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2959036171
Short name T190
Test name
Test status
Simulation time 505153480478 ps
CPU time 234.96 seconds
Started Apr 18 12:21:51 PM PDT 24
Finished Apr 18 12:25:46 PM PDT 24
Peak memory 193416 kb
Host smart-cbc5dde9-b7ec-4d07-a6c6-d86c791fb870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959036171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2959036171
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2038595550
Short name T43
Test name
Test status
Simulation time 154056174114 ps
CPU time 271.84 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:28:30 PM PDT 24
Peak memory 182004 kb
Host smart-c6774127-d3f6-4495-97a7-eb451954adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038595550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2038595550
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_random.3400370633
Short name T311
Test name
Test status
Simulation time 130992310129 ps
CPU time 205.96 seconds
Started Apr 18 12:22:58 PM PDT 24
Finished Apr 18 12:26:25 PM PDT 24
Peak memory 190668 kb
Host smart-25eacd6a-8e7c-46bc-865d-74ad9318fca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400370633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3400370633
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1865590881
Short name T336
Test name
Test status
Simulation time 677645745626 ps
CPU time 225.76 seconds
Started Apr 18 12:23:15 PM PDT 24
Finished Apr 18 12:27:01 PM PDT 24
Peak memory 194360 kb
Host smart-7fecd765-749c-44d5-8b3f-2669b7cf68d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865590881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1865590881
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.4011183131
Short name T270
Test name
Test status
Simulation time 615934094853 ps
CPU time 138.3 seconds
Started Apr 18 12:23:27 PM PDT 24
Finished Apr 18 12:25:47 PM PDT 24
Peak memory 190628 kb
Host smart-35512fa2-d354-4dc7-a4de-fb76016cff73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011183131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.4011183131
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.1376450641
Short name T236
Test name
Test status
Simulation time 512279473525 ps
CPU time 486.2 seconds
Started Apr 18 12:23:25 PM PDT 24
Finished Apr 18 12:31:32 PM PDT 24
Peak memory 190624 kb
Host smart-280e7a82-7271-4a93-a304-c38e546c730d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376450641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1376450641
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.371925411
Short name T573
Test name
Test status
Simulation time 166140981 ps
CPU time 0.93 seconds
Started Apr 18 12:23:16 PM PDT 24
Finished Apr 18 12:23:18 PM PDT 24
Peak memory 181936 kb
Host smart-ebaa29db-694d-4a1b-9c0c-c371ff665ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371925411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.371925411
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1125351497
Short name T173
Test name
Test status
Simulation time 252861562367 ps
CPU time 139.23 seconds
Started Apr 18 12:22:59 PM PDT 24
Finished Apr 18 12:25:19 PM PDT 24
Peak memory 182152 kb
Host smart-62ffc403-ed5b-488b-a1b7-c8db215b0d01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125351497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1125351497
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.2523171789
Short name T223
Test name
Test status
Simulation time 204365820797 ps
CPU time 83.91 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:24:53 PM PDT 24
Peak memory 182424 kb
Host smart-ad5704f1-24c2-4983-a56a-cd3304d7c28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523171789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2523171789
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3908674446
Short name T282
Test name
Test status
Simulation time 76077530781 ps
CPU time 44.26 seconds
Started Apr 18 12:24:39 PM PDT 24
Finished Apr 18 12:25:24 PM PDT 24
Peak memory 182144 kb
Host smart-ec118f78-cc28-41a3-9850-fde803c20c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908674446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3908674446
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3294381203
Short name T289
Test name
Test status
Simulation time 127444966340 ps
CPU time 193.42 seconds
Started Apr 18 12:24:37 PM PDT 24
Finished Apr 18 12:27:52 PM PDT 24
Peak memory 193684 kb
Host smart-02758dff-2b31-405d-bd2d-51ceda4104db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294381203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3294381203
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3801273681
Short name T229
Test name
Test status
Simulation time 185943536487 ps
CPU time 310.79 seconds
Started Apr 18 12:22:59 PM PDT 24
Finished Apr 18 12:28:10 PM PDT 24
Peak memory 182056 kb
Host smart-280354b3-abcc-4e3a-8137-406b691436c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801273681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3801273681
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2772374040
Short name T412
Test name
Test status
Simulation time 68087450781 ps
CPU time 44.7 seconds
Started Apr 18 12:23:09 PM PDT 24
Finished Apr 18 12:23:55 PM PDT 24
Peak memory 193796 kb
Host smart-4e62bb59-0637-4d99-b47a-2c0aeccefa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772374040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2772374040
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1030878633
Short name T246
Test name
Test status
Simulation time 329796011866 ps
CPU time 516.98 seconds
Started Apr 18 12:22:48 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 179600 kb
Host smart-972dd7cf-6845-49e9-bfe9-e7ee7e012c61
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030878633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1030878633
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/162.rv_timer_random.830026326
Short name T327
Test name
Test status
Simulation time 98943039228 ps
CPU time 46.85 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:24:35 PM PDT 24
Peak memory 182316 kb
Host smart-602f6abf-2c24-4e4d-a70c-cdd32b64a316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830026326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.830026326
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.571764098
Short name T279
Test name
Test status
Simulation time 360195531978 ps
CPU time 320.96 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:29:06 PM PDT 24
Peak memory 181300 kb
Host smart-3c4346bd-1da7-4e05-9499-30ee25e5fdc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571764098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.571764098
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/180.rv_timer_random.645376394
Short name T64
Test name
Test status
Simulation time 110888735527 ps
CPU time 3009.46 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 01:13:56 PM PDT 24
Peak memory 193864 kb
Host smart-28bb51fc-d68f-4888-bc14-930cf1d0d6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645376394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.645376394
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1021651938
Short name T263
Test name
Test status
Simulation time 119525060439 ps
CPU time 153.49 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:26:20 PM PDT 24
Peak memory 190532 kb
Host smart-6efe8928-6e35-429b-bf74-080245af0578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021651938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1021651938
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1091646867
Short name T84
Test name
Test status
Simulation time 614479264820 ps
CPU time 530.24 seconds
Started Apr 18 12:23:08 PM PDT 24
Finished Apr 18 12:31:59 PM PDT 24
Peak memory 190132 kb
Host smart-712a995b-ab96-4682-8b0e-dcb6b1738d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091646867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1091646867
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1843881145
Short name T187
Test name
Test status
Simulation time 3247861067 ps
CPU time 3.47 seconds
Started Apr 18 12:23:10 PM PDT 24
Finished Apr 18 12:23:14 PM PDT 24
Peak memory 182080 kb
Host smart-722ab756-2e03-46d4-9c7b-7cabf1eb25f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843881145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1843881145
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2088836743
Short name T54
Test name
Test status
Simulation time 2604171986178 ps
CPU time 1699.3 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:52:05 PM PDT 24
Peak memory 190240 kb
Host smart-7276bb04-f514-4c40-a9d5-ee1319fb9917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088836743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2088836743
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2967773458
Short name T284
Test name
Test status
Simulation time 914444965551 ps
CPU time 582.15 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 188824 kb
Host smart-e302e0ab-c763-41ce-8086-451c5024168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967773458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2967773458
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_random.1466367737
Short name T344
Test name
Test status
Simulation time 160419714956 ps
CPU time 425.18 seconds
Started Apr 18 12:22:46 PM PDT 24
Finished Apr 18 12:29:52 PM PDT 24
Peak memory 190620 kb
Host smart-5adcd801-abc4-4efd-9a41-1ce86662477e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466367737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1466367737
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random.1398324582
Short name T60
Test name
Test status
Simulation time 1789070137859 ps
CPU time 1022.23 seconds
Started Apr 18 12:23:03 PM PDT 24
Finished Apr 18 12:40:06 PM PDT 24
Peak memory 190648 kb
Host smart-076611eb-561b-4a24-995d-efdc30712f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398324582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1398324582
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3537929005
Short name T468
Test name
Test status
Simulation time 14879511 ps
CPU time 0.63 seconds
Started Apr 18 12:17:55 PM PDT 24
Finished Apr 18 12:17:57 PM PDT 24
Peak memory 191004 kb
Host smart-9128c431-f06a-42d6-b22a-50392c6b6369
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537929005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3537929005
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3105302749
Short name T527
Test name
Test status
Simulation time 39158647 ps
CPU time 1.49 seconds
Started Apr 18 12:17:56 PM PDT 24
Finished Apr 18 12:17:58 PM PDT 24
Peak memory 192368 kb
Host smart-5ded1b10-2747-4c1e-932e-4c7139002387
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105302749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3105302749
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3354867959
Short name T76
Test name
Test status
Simulation time 21737435 ps
CPU time 0.62 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:23:53 PM PDT 24
Peak memory 180868 kb
Host smart-778c0b61-2005-409d-811a-bb3c7ce81f19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354867959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3354867959
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.456526252
Short name T494
Test name
Test status
Simulation time 26638965 ps
CPU time 1.17 seconds
Started Apr 18 12:17:55 PM PDT 24
Finished Apr 18 12:17:57 PM PDT 24
Peak memory 196280 kb
Host smart-29270ad5-7099-418f-89fc-de96964c20ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456526252 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.456526252
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4098309130
Short name T68
Test name
Test status
Simulation time 14977557 ps
CPU time 0.54 seconds
Started Apr 18 12:17:55 PM PDT 24
Finished Apr 18 12:17:56 PM PDT 24
Peak memory 182460 kb
Host smart-123f6127-ca43-45d2-a44e-d122844eb68b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098309130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4098309130
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2325226726
Short name T556
Test name
Test status
Simulation time 27895536 ps
CPU time 0.61 seconds
Started Apr 18 12:22:43 PM PDT 24
Finished Apr 18 12:22:45 PM PDT 24
Peak memory 181588 kb
Host smart-d61cc863-d4fd-4eac-a71e-4b008db528a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325226726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2325226726
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.758046066
Short name T511
Test name
Test status
Simulation time 29963773 ps
CPU time 0.64 seconds
Started Apr 18 12:17:56 PM PDT 24
Finished Apr 18 12:17:58 PM PDT 24
Peak memory 190532 kb
Host smart-9c91b757-7869-48bf-9f6e-59d7d5b980fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758046066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.758046066
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.63233623
Short name T542
Test name
Test status
Simulation time 197576626 ps
CPU time 3.15 seconds
Started Apr 18 12:23:08 PM PDT 24
Finished Apr 18 12:23:12 PM PDT 24
Peak memory 197244 kb
Host smart-8ecd621f-654f-4d25-a745-befc7c7e4337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63233623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.63233623
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1690565764
Short name T488
Test name
Test status
Simulation time 158662587 ps
CPU time 1.13 seconds
Started Apr 18 12:22:49 PM PDT 24
Finished Apr 18 12:22:52 PM PDT 24
Peak memory 194016 kb
Host smart-e3ce6d48-c74d-4c1c-b98f-77499cd81417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690565764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1690565764
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2355109381
Short name T72
Test name
Test status
Simulation time 50765599 ps
CPU time 0.78 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:23:53 PM PDT 24
Peak memory 181164 kb
Host smart-b556c700-503f-411d-a777-4e31fcc578dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355109381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2355109381
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1738379798
Short name T78
Test name
Test status
Simulation time 66147675 ps
CPU time 1.39 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:23:54 PM PDT 24
Peak memory 191268 kb
Host smart-2d1d590a-84bf-4e73-9050-d811c0cc841f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738379798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1738379798
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2487234595
Short name T584
Test name
Test status
Simulation time 31563720 ps
CPU time 1.22 seconds
Started Apr 18 12:23:12 PM PDT 24
Finished Apr 18 12:23:14 PM PDT 24
Peak memory 197316 kb
Host smart-cc5e450e-17c0-4de6-ba81-efaf764a3b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487234595 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2487234595
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3747024933
Short name T71
Test name
Test status
Simulation time 58787195 ps
CPU time 0.63 seconds
Started Apr 18 12:22:59 PM PDT 24
Finished Apr 18 12:23:00 PM PDT 24
Peak memory 181592 kb
Host smart-408d2e57-1a8e-48a9-a4f0-3ea157afa4cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747024933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3747024933
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2055545163
Short name T574
Test name
Test status
Simulation time 46307164 ps
CPU time 0.59 seconds
Started Apr 18 12:23:07 PM PDT 24
Finished Apr 18 12:23:08 PM PDT 24
Peak memory 181100 kb
Host smart-6fb0cf5a-22b8-4e0a-b6db-bdc981f23f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055545163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2055545163
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2700752462
Short name T559
Test name
Test status
Simulation time 22587572 ps
CPU time 0.59 seconds
Started Apr 18 12:24:29 PM PDT 24
Finished Apr 18 12:24:31 PM PDT 24
Peak memory 190792 kb
Host smart-1370c0f9-3734-4aa2-aba6-100bb26d1486
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700752462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2700752462
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2154064507
Short name T454
Test name
Test status
Simulation time 57067065 ps
CPU time 1.35 seconds
Started Apr 18 12:17:56 PM PDT 24
Finished Apr 18 12:17:59 PM PDT 24
Peak memory 196884 kb
Host smart-020fde64-9b99-4e9c-a318-3ad53d43d147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154064507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2154064507
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1471169852
Short name T575
Test name
Test status
Simulation time 358444838 ps
CPU time 1.42 seconds
Started Apr 18 12:17:55 PM PDT 24
Finished Apr 18 12:17:58 PM PDT 24
Peak memory 195512 kb
Host smart-281b6485-f670-4e56-915c-6c1ffce0f717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471169852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1471169852
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.852770130
Short name T499
Test name
Test status
Simulation time 33218143 ps
CPU time 1.36 seconds
Started Apr 18 12:22:58 PM PDT 24
Finished Apr 18 12:23:00 PM PDT 24
Peak memory 196496 kb
Host smart-871006fd-36a7-4166-8314-9e004b47b140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852770130 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.852770130
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2066402588
Short name T73
Test name
Test status
Simulation time 15421473 ps
CPU time 0.59 seconds
Started Apr 18 12:20:54 PM PDT 24
Finished Apr 18 12:20:55 PM PDT 24
Peak memory 182604 kb
Host smart-5b8da3ab-e831-4732-b799-50dbe7ffa002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066402588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2066402588
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2132121993
Short name T478
Test name
Test status
Simulation time 47424293 ps
CPU time 0.6 seconds
Started Apr 18 12:20:49 PM PDT 24
Finished Apr 18 12:20:52 PM PDT 24
Peak memory 180584 kb
Host smart-70e2d746-19e3-4be4-a87a-1801edb5206f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132121993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2132121993
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3818786081
Short name T520
Test name
Test status
Simulation time 31373819 ps
CPU time 0.81 seconds
Started Apr 18 12:21:34 PM PDT 24
Finished Apr 18 12:21:36 PM PDT 24
Peak memory 193244 kb
Host smart-a8a53db0-871a-4693-9221-d58354c9c4ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818786081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3818786081
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1625560782
Short name T549
Test name
Test status
Simulation time 245124685 ps
CPU time 2.49 seconds
Started Apr 18 12:20:49 PM PDT 24
Finished Apr 18 12:20:54 PM PDT 24
Peak memory 195616 kb
Host smart-71707eda-b163-4d32-9ce1-c82b3eb930c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625560782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1625560782
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.157026484
Short name T97
Test name
Test status
Simulation time 80910204 ps
CPU time 1.12 seconds
Started Apr 18 12:20:13 PM PDT 24
Finished Apr 18 12:20:16 PM PDT 24
Peak memory 194580 kb
Host smart-f56fc909-3bf1-48c6-a6d5-6db2b36628bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157026484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.157026484
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.516510135
Short name T553
Test name
Test status
Simulation time 24448897 ps
CPU time 1.09 seconds
Started Apr 18 12:19:27 PM PDT 24
Finished Apr 18 12:19:29 PM PDT 24
Peak memory 197168 kb
Host smart-fc3ac45b-3d70-44a2-abcb-9efba5be64f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516510135 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.516510135
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1862935932
Short name T74
Test name
Test status
Simulation time 45488429 ps
CPU time 0.53 seconds
Started Apr 18 12:23:31 PM PDT 24
Finished Apr 18 12:23:33 PM PDT 24
Peak memory 182468 kb
Host smart-bb322280-6f39-48db-9eea-ab708b6ac436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862935932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1862935932
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2941375829
Short name T568
Test name
Test status
Simulation time 23360646 ps
CPU time 0.55 seconds
Started Apr 18 12:22:53 PM PDT 24
Finished Apr 18 12:22:55 PM PDT 24
Peak memory 182268 kb
Host smart-831512ad-85f1-4b0c-b522-32cb0aff6049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941375829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2941375829
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3373880746
Short name T472
Test name
Test status
Simulation time 465526314 ps
CPU time 2.17 seconds
Started Apr 18 12:23:15 PM PDT 24
Finished Apr 18 12:23:18 PM PDT 24
Peak memory 197392 kb
Host smart-729e1b15-1020-468c-a129-e52149f67e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373880746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3373880746
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1848218224
Short name T550
Test name
Test status
Simulation time 156309684 ps
CPU time 0.84 seconds
Started Apr 18 12:19:07 PM PDT 24
Finished Apr 18 12:19:08 PM PDT 24
Peak memory 193388 kb
Host smart-f086ac80-255c-4c45-9674-83e4646a2b05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848218224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1848218224
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.580698732
Short name T51
Test name
Test status
Simulation time 20215876 ps
CPU time 0.69 seconds
Started Apr 18 12:19:50 PM PDT 24
Finished Apr 18 12:19:51 PM PDT 24
Peak memory 194528 kb
Host smart-accfc73f-3d66-4d95-b2db-ce58fc8c576f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580698732 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.580698732
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.476915555
Short name T467
Test name
Test status
Simulation time 21180699 ps
CPU time 0.59 seconds
Started Apr 18 12:22:39 PM PDT 24
Finished Apr 18 12:22:40 PM PDT 24
Peak memory 180416 kb
Host smart-7b33e888-a4e5-4fc7-89a3-edecba1c99b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476915555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.476915555
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.988947820
Short name T522
Test name
Test status
Simulation time 64632959 ps
CPU time 0.58 seconds
Started Apr 18 12:22:39 PM PDT 24
Finished Apr 18 12:22:40 PM PDT 24
Peak memory 180044 kb
Host smart-ef48c79e-f41f-48e2-b086-34ee4bc454b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988947820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.988947820
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3599668264
Short name T50
Test name
Test status
Simulation time 515234908 ps
CPU time 0.84 seconds
Started Apr 18 12:22:16 PM PDT 24
Finished Apr 18 12:22:17 PM PDT 24
Peak memory 193380 kb
Host smart-42e0ce85-7b8d-44fd-8fbd-c65a94b76251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599668264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3599668264
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2243748957
Short name T513
Test name
Test status
Simulation time 123443744 ps
CPU time 1.72 seconds
Started Apr 18 12:19:26 PM PDT 24
Finished Apr 18 12:19:28 PM PDT 24
Peak memory 197500 kb
Host smart-49102046-8393-452d-ad4d-f8ac7717bb88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243748957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2243748957
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3336231938
Short name T470
Test name
Test status
Simulation time 61792996 ps
CPU time 1.41 seconds
Started Apr 18 12:20:32 PM PDT 24
Finished Apr 18 12:20:34 PM PDT 24
Peak memory 196892 kb
Host smart-7825ae6a-932f-4339-93ab-ea2efc5c08e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336231938 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3336231938
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4203049249
Short name T504
Test name
Test status
Simulation time 14530575 ps
CPU time 0.61 seconds
Started Apr 18 12:23:30 PM PDT 24
Finished Apr 18 12:23:32 PM PDT 24
Peak memory 182468 kb
Host smart-c0be9601-5a5e-462f-b3e8-11d74597c6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203049249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.4203049249
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.655177261
Short name T585
Test name
Test status
Simulation time 57701311 ps
CPU time 0.57 seconds
Started Apr 18 12:22:39 PM PDT 24
Finished Apr 18 12:22:40 PM PDT 24
Peak memory 180716 kb
Host smart-0cf945b8-1082-488b-9f88-0addabe1422f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655177261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.655177261
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1257916461
Short name T93
Test name
Test status
Simulation time 34948462 ps
CPU time 0.76 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:23:52 PM PDT 24
Peak memory 192624 kb
Host smart-5bdcdb4f-91f1-476b-a02a-15e3495a27aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257916461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1257916461
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.359093897
Short name T471
Test name
Test status
Simulation time 213205002 ps
CPU time 1.32 seconds
Started Apr 18 12:20:10 PM PDT 24
Finished Apr 18 12:20:12 PM PDT 24
Peak memory 197388 kb
Host smart-cef0d6b6-baf1-438a-b55a-7621e6666757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359093897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.359093897
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3875911173
Short name T484
Test name
Test status
Simulation time 304789482 ps
CPU time 1.58 seconds
Started Apr 18 12:19:29 PM PDT 24
Finished Apr 18 12:19:32 PM PDT 24
Peak memory 195316 kb
Host smart-f7153313-cc6e-49a8-9d71-282ca94d6237
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875911173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3875911173
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3534536192
Short name T452
Test name
Test status
Simulation time 214478798 ps
CPU time 1.46 seconds
Started Apr 18 12:23:24 PM PDT 24
Finished Apr 18 12:23:27 PM PDT 24
Peak memory 196464 kb
Host smart-df70e085-8a63-42af-8fa9-ac979ae781b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534536192 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3534536192
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4277550883
Short name T501
Test name
Test status
Simulation time 11572416 ps
CPU time 0.54 seconds
Started Apr 18 12:23:31 PM PDT 24
Finished Apr 18 12:23:33 PM PDT 24
Peak memory 182444 kb
Host smart-100c9d0d-e0c3-462b-9a42-28e0e5a6123a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277550883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4277550883
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3639090809
Short name T460
Test name
Test status
Simulation time 15826673 ps
CPU time 0.59 seconds
Started Apr 18 12:18:59 PM PDT 24
Finished Apr 18 12:19:00 PM PDT 24
Peak memory 182236 kb
Host smart-ec63e0f0-0621-45e4-826e-b355f9884bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639090809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3639090809
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3189362825
Short name T90
Test name
Test status
Simulation time 15851362 ps
CPU time 0.66 seconds
Started Apr 18 12:20:13 PM PDT 24
Finished Apr 18 12:20:15 PM PDT 24
Peak memory 192040 kb
Host smart-ff507d4d-b62a-4814-84e1-5db60a59309f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189362825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3189362825
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4085594980
Short name T569
Test name
Test status
Simulation time 247476077 ps
CPU time 1.16 seconds
Started Apr 18 12:22:17 PM PDT 24
Finished Apr 18 12:22:19 PM PDT 24
Peak memory 197364 kb
Host smart-b4a32441-69bc-433d-8c65-7c590d088b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085594980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.4085594980
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2509423669
Short name T490
Test name
Test status
Simulation time 518992983 ps
CPU time 1.34 seconds
Started Apr 18 12:22:43 PM PDT 24
Finished Apr 18 12:22:45 PM PDT 24
Peak memory 195508 kb
Host smart-a3cebbba-7acc-412b-b023-2a968a7a5cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509423669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2509423669
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3985833118
Short name T536
Test name
Test status
Simulation time 22931013 ps
CPU time 0.78 seconds
Started Apr 18 12:20:49 PM PDT 24
Finished Apr 18 12:20:50 PM PDT 24
Peak memory 194852 kb
Host smart-0fdc64ef-967c-4d09-8f3a-fff333453bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985833118 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3985833118
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2493022008
Short name T554
Test name
Test status
Simulation time 38494075 ps
CPU time 0.55 seconds
Started Apr 18 12:23:11 PM PDT 24
Finished Apr 18 12:23:12 PM PDT 24
Peak memory 182448 kb
Host smart-438be41e-9633-423a-b78e-e3242a77cdcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493022008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2493022008
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2334609081
Short name T458
Test name
Test status
Simulation time 14609494 ps
CPU time 0.56 seconds
Started Apr 18 12:22:40 PM PDT 24
Finished Apr 18 12:22:41 PM PDT 24
Peak memory 182196 kb
Host smart-634d55cf-ffd8-4a56-8b6f-b69f1ab0da85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334609081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2334609081
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.828308815
Short name T557
Test name
Test status
Simulation time 92893724 ps
CPU time 0.8 seconds
Started Apr 18 12:17:53 PM PDT 24
Finished Apr 18 12:17:54 PM PDT 24
Peak memory 192132 kb
Host smart-778378d6-4ea8-4b8a-a882-cbc9fe913dd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828308815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.828308815
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.698054852
Short name T562
Test name
Test status
Simulation time 180854588 ps
CPU time 1.72 seconds
Started Apr 18 12:23:31 PM PDT 24
Finished Apr 18 12:23:34 PM PDT 24
Peak memory 197324 kb
Host smart-575f75d0-d884-4ec9-82da-3abb255bb0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698054852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.698054852
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.766885026
Short name T505
Test name
Test status
Simulation time 452541278 ps
CPU time 1.39 seconds
Started Apr 18 12:18:56 PM PDT 24
Finished Apr 18 12:18:59 PM PDT 24
Peak memory 195300 kb
Host smart-ef4d1cb0-9eba-458d-a156-3d6f5c59a47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766885026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.766885026
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.957837670
Short name T543
Test name
Test status
Simulation time 35249955 ps
CPU time 0.72 seconds
Started Apr 18 12:22:54 PM PDT 24
Finished Apr 18 12:22:57 PM PDT 24
Peak memory 192800 kb
Host smart-02b0f58b-a78b-4848-b86b-5478af4319eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957837670 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.957837670
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.932507104
Short name T75
Test name
Test status
Simulation time 22605962 ps
CPU time 0.57 seconds
Started Apr 18 12:20:13 PM PDT 24
Finished Apr 18 12:20:15 PM PDT 24
Peak memory 182380 kb
Host smart-9ae74474-52e3-4db5-9a46-0399c7d183c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932507104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.932507104
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1163778303
Short name T463
Test name
Test status
Simulation time 44355850 ps
CPU time 0.56 seconds
Started Apr 18 12:21:35 PM PDT 24
Finished Apr 18 12:21:36 PM PDT 24
Peak memory 182492 kb
Host smart-30e97a3e-5c6a-4e6a-a156-aa018433a0a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163778303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1163778303
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2570133975
Short name T565
Test name
Test status
Simulation time 52685838 ps
CPU time 0.77 seconds
Started Apr 18 12:22:54 PM PDT 24
Finished Apr 18 12:22:57 PM PDT 24
Peak memory 189616 kb
Host smart-adef54d6-c242-4e91-b755-8bad8e3ca990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570133975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2570133975
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1464188275
Short name T456
Test name
Test status
Simulation time 529149286 ps
CPU time 2.79 seconds
Started Apr 18 12:19:22 PM PDT 24
Finished Apr 18 12:19:25 PM PDT 24
Peak memory 197356 kb
Host smart-ad001029-c3cb-4e7f-b539-e75dbc9263e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464188275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1464188275
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.657989355
Short name T580
Test name
Test status
Simulation time 744224942 ps
CPU time 1.17 seconds
Started Apr 18 12:21:53 PM PDT 24
Finished Apr 18 12:21:54 PM PDT 24
Peak memory 195208 kb
Host smart-3d33fcbd-29d5-43b4-a91f-bf10bf482d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657989355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.657989355
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.317535574
Short name T582
Test name
Test status
Simulation time 37782557 ps
CPU time 1.02 seconds
Started Apr 18 12:19:48 PM PDT 24
Finished Apr 18 12:19:50 PM PDT 24
Peak memory 197188 kb
Host smart-85e18dbf-3422-480f-86ae-611b518084e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317535574 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.317535574
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2543917286
Short name T523
Test name
Test status
Simulation time 27327482 ps
CPU time 0.62 seconds
Started Apr 18 12:19:48 PM PDT 24
Finished Apr 18 12:19:49 PM PDT 24
Peak memory 191716 kb
Host smart-a6c6c31d-5d23-41ab-a642-d0b208de3da4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543917286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2543917286
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3729935657
Short name T529
Test name
Test status
Simulation time 34671517 ps
CPU time 0.55 seconds
Started Apr 18 12:22:18 PM PDT 24
Finished Apr 18 12:22:19 PM PDT 24
Peak memory 182484 kb
Host smart-72759663-4d17-4791-a5bf-102e186d56e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729935657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3729935657
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2255038149
Short name T509
Test name
Test status
Simulation time 57174183 ps
CPU time 0.75 seconds
Started Apr 18 12:23:08 PM PDT 24
Finished Apr 18 12:23:09 PM PDT 24
Peak memory 192548 kb
Host smart-a652c1f5-0c62-4c93-b2d0-7f1791eae151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255038149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2255038149
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2638688564
Short name T491
Test name
Test status
Simulation time 131124614 ps
CPU time 2.15 seconds
Started Apr 18 12:18:01 PM PDT 24
Finished Apr 18 12:18:03 PM PDT 24
Peak memory 197268 kb
Host smart-10c0167e-5b4c-4b2b-a46e-b35ff0a215f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638688564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2638688564
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3993624094
Short name T27
Test name
Test status
Simulation time 340152203 ps
CPU time 1.42 seconds
Started Apr 18 12:22:32 PM PDT 24
Finished Apr 18 12:22:34 PM PDT 24
Peak memory 195340 kb
Host smart-e9b9758f-52c0-4e7c-a91f-35bffb3df222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993624094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3993624094
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1751502772
Short name T480
Test name
Test status
Simulation time 28283729 ps
CPU time 0.61 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:22:52 PM PDT 24
Peak memory 193372 kb
Host smart-98148ea3-5cbd-4042-a005-4d07f60f5918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751502772 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1751502772
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3864731026
Short name T29
Test name
Test status
Simulation time 17895790 ps
CPU time 0.66 seconds
Started Apr 18 12:20:00 PM PDT 24
Finished Apr 18 12:20:02 PM PDT 24
Peak memory 182536 kb
Host smart-0dc18327-ba42-4a17-8849-ef1093257896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864731026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3864731026
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1187347405
Short name T535
Test name
Test status
Simulation time 49933315 ps
CPU time 0.58 seconds
Started Apr 18 12:23:08 PM PDT 24
Finished Apr 18 12:23:09 PM PDT 24
Peak memory 181776 kb
Host smart-0520c5ba-1703-40a1-818f-446e9f305d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187347405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1187347405
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1237448624
Short name T544
Test name
Test status
Simulation time 60887169 ps
CPU time 0.81 seconds
Started Apr 18 12:22:54 PM PDT 24
Finished Apr 18 12:22:57 PM PDT 24
Peak memory 191344 kb
Host smart-fdf6cb66-6efd-46b6-9438-6a473f616621
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237448624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1237448624
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.874954105
Short name T514
Test name
Test status
Simulation time 147599410 ps
CPU time 1 seconds
Started Apr 18 12:19:43 PM PDT 24
Finished Apr 18 12:19:45 PM PDT 24
Peak memory 195296 kb
Host smart-7200c3fd-a294-48a0-9e4d-70d7055c99a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874954105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.874954105
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1183967318
Short name T551
Test name
Test status
Simulation time 81579599 ps
CPU time 1.1 seconds
Started Apr 18 12:19:55 PM PDT 24
Finished Apr 18 12:19:57 PM PDT 24
Peak memory 194848 kb
Host smart-2377006a-e4a8-40ed-9f23-ead811d82c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183967318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1183967318
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3313072332
Short name T567
Test name
Test status
Simulation time 117160403 ps
CPU time 0.85 seconds
Started Apr 18 12:19:58 PM PDT 24
Finished Apr 18 12:20:00 PM PDT 24
Peak memory 195092 kb
Host smart-4669b06d-9ede-4c3d-840a-5f1a15e803af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313072332 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3313072332
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.635057861
Short name T578
Test name
Test status
Simulation time 14057483 ps
CPU time 0.58 seconds
Started Apr 18 12:22:40 PM PDT 24
Finished Apr 18 12:22:41 PM PDT 24
Peak memory 182216 kb
Host smart-635878ab-eb4a-47f4-882a-3dab157796e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635057861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.635057861
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4050463568
Short name T476
Test name
Test status
Simulation time 17175745 ps
CPU time 0.6 seconds
Started Apr 18 12:20:01 PM PDT 24
Finished Apr 18 12:20:03 PM PDT 24
Peak memory 182364 kb
Host smart-03b8bea5-3ed4-41ac-ab89-d684f3db6793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050463568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4050463568
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2706130120
Short name T539
Test name
Test status
Simulation time 93776843 ps
CPU time 0.74 seconds
Started Apr 18 12:20:03 PM PDT 24
Finished Apr 18 12:20:05 PM PDT 24
Peak memory 192960 kb
Host smart-73f13476-859f-4797-aba0-a3dc2ea68de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706130120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2706130120
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3207146523
Short name T493
Test name
Test status
Simulation time 651235996 ps
CPU time 1.99 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:22:53 PM PDT 24
Peak memory 197148 kb
Host smart-10613a6e-b92f-445e-8e16-474bf3349c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207146523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3207146523
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.345985662
Short name T528
Test name
Test status
Simulation time 72685671 ps
CPU time 1.14 seconds
Started Apr 18 12:19:59 PM PDT 24
Finished Apr 18 12:20:02 PM PDT 24
Peak memory 194976 kb
Host smart-3d81afb8-eb72-4da7-a925-35c61cf470fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345985662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.345985662
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.287786756
Short name T482
Test name
Test status
Simulation time 21358334 ps
CPU time 0.64 seconds
Started Apr 18 12:18:58 PM PDT 24
Finished Apr 18 12:19:00 PM PDT 24
Peak memory 191812 kb
Host smart-5bfbc040-33a1-426b-956e-5020404f3f4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287786756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.287786756
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2715475457
Short name T473
Test name
Test status
Simulation time 37131320 ps
CPU time 1.39 seconds
Started Apr 18 12:22:51 PM PDT 24
Finished Apr 18 12:22:53 PM PDT 24
Peak memory 182228 kb
Host smart-63f8dd82-4af6-41a7-bde9-a05fbb9878bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715475457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2715475457
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4219302179
Short name T465
Test name
Test status
Simulation time 22834343 ps
CPU time 0.52 seconds
Started Apr 18 12:24:29 PM PDT 24
Finished Apr 18 12:24:31 PM PDT 24
Peak memory 182084 kb
Host smart-09a0230c-22c8-4b87-ae63-d4fe977cd4ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219302179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4219302179
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3071457668
Short name T461
Test name
Test status
Simulation time 62682697 ps
CPU time 0.95 seconds
Started Apr 18 12:22:51 PM PDT 24
Finished Apr 18 12:22:53 PM PDT 24
Peak memory 196744 kb
Host smart-a939552f-8fcd-47a0-a493-bb75437961af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071457668 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3071457668
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.475182063
Short name T52
Test name
Test status
Simulation time 19947082 ps
CPU time 0.58 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:22:52 PM PDT 24
Peak memory 181756 kb
Host smart-80124930-e0dc-44c6-a52f-f7855ff29109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475182063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.475182063
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3587130238
Short name T530
Test name
Test status
Simulation time 58691655 ps
CPU time 0.54 seconds
Started Apr 18 12:20:47 PM PDT 24
Finished Apr 18 12:20:48 PM PDT 24
Peak memory 182196 kb
Host smart-9ccafd74-22c7-497c-8137-4f322774f9af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587130238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3587130238
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.854736716
Short name T91
Test name
Test status
Simulation time 71000593 ps
CPU time 0.77 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:23:54 PM PDT 24
Peak memory 190768 kb
Host smart-0f0de548-ae6d-40da-a74f-92a0d0d282f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854736716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.854736716
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.674465721
Short name T552
Test name
Test status
Simulation time 187855166 ps
CPU time 1.02 seconds
Started Apr 18 12:19:09 PM PDT 24
Finished Apr 18 12:19:11 PM PDT 24
Peak memory 196472 kb
Host smart-ac977c2f-7ed1-49a6-bd4b-ca3be80486f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674465721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.674465721
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3731246884
Short name T518
Test name
Test status
Simulation time 442771751 ps
CPU time 1.42 seconds
Started Apr 18 12:19:42 PM PDT 24
Finished Apr 18 12:19:44 PM PDT 24
Peak memory 195048 kb
Host smart-ec4bb351-3da8-4ea4-87d0-4aaa31b50815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731246884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3731246884
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3768078603
Short name T500
Test name
Test status
Simulation time 31971583 ps
CPU time 0.58 seconds
Started Apr 18 12:20:57 PM PDT 24
Finished Apr 18 12:20:58 PM PDT 24
Peak memory 182580 kb
Host smart-8deca452-f4a6-44ef-83b8-b3f30123552d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768078603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3768078603
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2001433181
Short name T581
Test name
Test status
Simulation time 13716766 ps
CPU time 0.54 seconds
Started Apr 18 12:20:12 PM PDT 24
Finished Apr 18 12:20:13 PM PDT 24
Peak memory 181736 kb
Host smart-94ec6fbc-7c46-46d5-a489-0c06842b34ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001433181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2001433181
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.4290053520
Short name T464
Test name
Test status
Simulation time 14180828 ps
CPU time 0.53 seconds
Started Apr 18 12:23:11 PM PDT 24
Finished Apr 18 12:23:12 PM PDT 24
Peak memory 182404 kb
Host smart-858a0eaf-9c98-458a-9119-c9ffb42d88e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290053520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.4290053520
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1333329311
Short name T497
Test name
Test status
Simulation time 14095875 ps
CPU time 0.66 seconds
Started Apr 18 12:21:28 PM PDT 24
Finished Apr 18 12:21:30 PM PDT 24
Peak memory 182508 kb
Host smart-8a0b0f8a-4de2-41cd-bb0f-e009731544ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333329311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1333329311
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.289915069
Short name T479
Test name
Test status
Simulation time 21490984 ps
CPU time 0.55 seconds
Started Apr 18 12:20:08 PM PDT 24
Finished Apr 18 12:20:09 PM PDT 24
Peak memory 182776 kb
Host smart-4b418808-111a-48ec-9a85-7a38b1ab711d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289915069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.289915069
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2495137223
Short name T496
Test name
Test status
Simulation time 35916294 ps
CPU time 0.54 seconds
Started Apr 18 12:23:13 PM PDT 24
Finished Apr 18 12:23:14 PM PDT 24
Peak memory 182064 kb
Host smart-892669fb-d0f3-4ed8-9958-a0b5feba4f8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495137223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2495137223
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1983157813
Short name T459
Test name
Test status
Simulation time 18211035 ps
CPU time 0.55 seconds
Started Apr 18 12:23:13 PM PDT 24
Finished Apr 18 12:23:14 PM PDT 24
Peak memory 182044 kb
Host smart-438b8807-e1f4-499a-a5ff-524864ffea60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983157813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1983157813
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3457259602
Short name T546
Test name
Test status
Simulation time 14133847 ps
CPU time 0.55 seconds
Started Apr 18 12:23:12 PM PDT 24
Finished Apr 18 12:23:13 PM PDT 24
Peak memory 182008 kb
Host smart-bd9af55c-6dc0-49c3-bbdc-91e44991d28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457259602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3457259602
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3902717257
Short name T540
Test name
Test status
Simulation time 14558850 ps
CPU time 0.58 seconds
Started Apr 18 12:23:13 PM PDT 24
Finished Apr 18 12:23:14 PM PDT 24
Peak memory 182396 kb
Host smart-ed06fcda-47fe-46f8-be73-2a8edcdcd168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902717257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3902717257
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1201988867
Short name T538
Test name
Test status
Simulation time 28140886 ps
CPU time 0.57 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 180464 kb
Host smart-5da064cd-da59-4359-baa9-b1cc8fdc166f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201988867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1201988867
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2958942596
Short name T474
Test name
Test status
Simulation time 33970473 ps
CPU time 0.76 seconds
Started Apr 18 12:23:32 PM PDT 24
Finished Apr 18 12:23:34 PM PDT 24
Peak memory 182464 kb
Host smart-288ff6ec-636d-47a8-ac93-1bda0d518ae0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958942596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2958942596
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3770909323
Short name T481
Test name
Test status
Simulation time 137010693 ps
CPU time 1.33 seconds
Started Apr 18 12:23:43 PM PDT 24
Finished Apr 18 12:23:45 PM PDT 24
Peak memory 190160 kb
Host smart-629d6559-cb34-4bb4-a190-65af8d58b54f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770909323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3770909323
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2572822680
Short name T531
Test name
Test status
Simulation time 20783923 ps
CPU time 0.58 seconds
Started Apr 18 12:21:49 PM PDT 24
Finished Apr 18 12:21:51 PM PDT 24
Peak memory 182428 kb
Host smart-791937d4-2481-4845-9f4e-9e1ed2184f82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572822680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2572822680
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3546263772
Short name T560
Test name
Test status
Simulation time 32689950 ps
CPU time 0.95 seconds
Started Apr 18 12:19:01 PM PDT 24
Finished Apr 18 12:19:03 PM PDT 24
Peak memory 196912 kb
Host smart-3b12aafd-5c73-4abf-8305-b52cb6c23f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546263772 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3546263772
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.489615697
Short name T583
Test name
Test status
Simulation time 12818701 ps
CPU time 0.57 seconds
Started Apr 18 12:20:28 PM PDT 24
Finished Apr 18 12:20:29 PM PDT 24
Peak memory 182464 kb
Host smart-1cf30f90-fb49-4600-b225-74eefaad7974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489615697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.489615697
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1405816003
Short name T502
Test name
Test status
Simulation time 35724651 ps
CPU time 0.55 seconds
Started Apr 18 12:18:10 PM PDT 24
Finished Apr 18 12:18:11 PM PDT 24
Peak memory 181776 kb
Host smart-4bde8afa-e8c8-461d-a5d2-ad144c5f5e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405816003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1405816003
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3922419348
Short name T92
Test name
Test status
Simulation time 20990558 ps
CPU time 0.61 seconds
Started Apr 18 12:23:40 PM PDT 24
Finished Apr 18 12:23:41 PM PDT 24
Peak memory 191476 kb
Host smart-9651319f-5e6e-4802-acea-6f756ec8ce7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922419348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3922419348
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1844781692
Short name T515
Test name
Test status
Simulation time 157103630 ps
CPU time 2.37 seconds
Started Apr 18 12:23:02 PM PDT 24
Finished Apr 18 12:23:05 PM PDT 24
Peak memory 197336 kb
Host smart-c361b759-ddb5-4bed-af76-5b9baaf9f4be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844781692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1844781692
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.362243859
Short name T547
Test name
Test status
Simulation time 11559960 ps
CPU time 0.51 seconds
Started Apr 18 12:24:38 PM PDT 24
Finished Apr 18 12:24:40 PM PDT 24
Peak memory 180956 kb
Host smart-9c55ae67-088e-4a93-8ae1-b676c5a650c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362243859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.362243859
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.587199902
Short name T469
Test name
Test status
Simulation time 24448193 ps
CPU time 0.61 seconds
Started Apr 18 12:21:08 PM PDT 24
Finished Apr 18 12:21:09 PM PDT 24
Peak memory 182420 kb
Host smart-cf5da9bf-6b3e-4025-8718-3e19f82fe8dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587199902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.587199902
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2642417426
Short name T566
Test name
Test status
Simulation time 28826662 ps
CPU time 0.58 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 180232 kb
Host smart-1a611060-bab3-48ee-8f28-42484feae3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642417426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2642417426
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.362598508
Short name T555
Test name
Test status
Simulation time 27891447 ps
CPU time 0.53 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:23:47 PM PDT 24
Peak memory 182048 kb
Host smart-a4a109dd-f92b-40cb-8689-a2deaf900716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362598508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.362598508
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.591710235
Short name T519
Test name
Test status
Simulation time 15641207 ps
CPU time 0.57 seconds
Started Apr 18 12:21:16 PM PDT 24
Finished Apr 18 12:21:17 PM PDT 24
Peak memory 182520 kb
Host smart-b3938d3e-9bd3-4e8a-8e93-392445105763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591710235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.591710235
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.621802858
Short name T537
Test name
Test status
Simulation time 85276473 ps
CPU time 0.58 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 179644 kb
Host smart-69f79166-06ec-43d5-bc29-d159482d9e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621802858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.621802858
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3698598146
Short name T475
Test name
Test status
Simulation time 22480952 ps
CPU time 0.53 seconds
Started Apr 18 12:20:22 PM PDT 24
Finished Apr 18 12:20:23 PM PDT 24
Peak memory 181964 kb
Host smart-28f9a228-d7d0-4602-a387-53cc24164a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698598146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3698598146
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.826010489
Short name T495
Test name
Test status
Simulation time 64402535 ps
CPU time 0.54 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:23:47 PM PDT 24
Peak memory 182116 kb
Host smart-d8f90cf4-4fe1-4cd0-abe5-325c11160053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826010489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.826010489
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3503364943
Short name T521
Test name
Test status
Simulation time 38668161 ps
CPU time 0.61 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 180356 kb
Host smart-aac257d1-0978-4cc7-9f08-86895211e99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503364943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3503364943
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1032594132
Short name T563
Test name
Test status
Simulation time 49822152 ps
CPU time 0.58 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 180024 kb
Host smart-226d474f-708f-4373-8ebd-8598a71331d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032594132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1032594132
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3769487450
Short name T545
Test name
Test status
Simulation time 71513637 ps
CPU time 0.63 seconds
Started Apr 18 12:22:58 PM PDT 24
Finished Apr 18 12:23:00 PM PDT 24
Peak memory 181568 kb
Host smart-a2c10b58-ab02-4357-9397-9d0e40aa3824
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769487450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3769487450
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1669173642
Short name T533
Test name
Test status
Simulation time 284288866 ps
CPU time 2.27 seconds
Started Apr 18 12:20:08 PM PDT 24
Finished Apr 18 12:20:11 PM PDT 24
Peak memory 190920 kb
Host smart-c7f1d92e-2988-4396-aae2-003787a0f18f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669173642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1669173642
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1146092762
Short name T70
Test name
Test status
Simulation time 28131786 ps
CPU time 0.56 seconds
Started Apr 18 12:19:26 PM PDT 24
Finished Apr 18 12:19:27 PM PDT 24
Peak memory 182532 kb
Host smart-a3e23c4b-f93d-4ffb-9223-d7187f84aa16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146092762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1146092762
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.856819284
Short name T564
Test name
Test status
Simulation time 63496977 ps
CPU time 0.91 seconds
Started Apr 18 12:18:51 PM PDT 24
Finished Apr 18 12:18:53 PM PDT 24
Peak memory 195864 kb
Host smart-33ced6ac-3cb0-4a24-ac68-0a5c2cc829ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856819284 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.856819284
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2341016219
Short name T492
Test name
Test status
Simulation time 43800568 ps
CPU time 0.6 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:23:41 PM PDT 24
Peak memory 180812 kb
Host smart-cdeabd19-cd25-455a-a3ec-387ee3d2ba7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341016219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2341016219
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3373443218
Short name T517
Test name
Test status
Simulation time 16669272 ps
CPU time 0.58 seconds
Started Apr 18 12:18:45 PM PDT 24
Finished Apr 18 12:18:46 PM PDT 24
Peak memory 182592 kb
Host smart-0840c016-10af-40e4-ab59-528b42ac5c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373443218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3373443218
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.829307111
Short name T532
Test name
Test status
Simulation time 49842527 ps
CPU time 0.78 seconds
Started Apr 18 12:20:12 PM PDT 24
Finished Apr 18 12:20:14 PM PDT 24
Peak memory 191612 kb
Host smart-91534ea3-1eaf-48ed-bdde-e8302cea8154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829307111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.829307111
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1702365942
Short name T453
Test name
Test status
Simulation time 60052723 ps
CPU time 1.35 seconds
Started Apr 18 12:23:30 PM PDT 24
Finished Apr 18 12:23:32 PM PDT 24
Peak memory 191136 kb
Host smart-360e18ec-7d1b-4417-b70d-42e09a8deca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702365942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1702365942
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2912074003
Short name T96
Test name
Test status
Simulation time 264803176 ps
CPU time 1.41 seconds
Started Apr 18 12:22:00 PM PDT 24
Finished Apr 18 12:22:03 PM PDT 24
Peak memory 183200 kb
Host smart-99045693-bfd2-4277-a43e-ab5b8ace1282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912074003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2912074003
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1707183015
Short name T571
Test name
Test status
Simulation time 24661062 ps
CPU time 0.55 seconds
Started Apr 18 12:22:39 PM PDT 24
Finished Apr 18 12:22:40 PM PDT 24
Peak memory 182420 kb
Host smart-2d61e794-04d3-4574-8116-b9123ad118af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707183015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1707183015
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2532221209
Short name T503
Test name
Test status
Simulation time 21524764 ps
CPU time 0.52 seconds
Started Apr 18 12:22:42 PM PDT 24
Finished Apr 18 12:22:43 PM PDT 24
Peak memory 181124 kb
Host smart-02aa5a75-3708-42ee-a9ac-456ce1413f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532221209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2532221209
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1492374599
Short name T498
Test name
Test status
Simulation time 18858935 ps
CPU time 0.56 seconds
Started Apr 18 12:20:17 PM PDT 24
Finished Apr 18 12:20:18 PM PDT 24
Peak memory 182448 kb
Host smart-34329ea3-dcbe-4733-b82d-40aafd6b31af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492374599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1492374599
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2897237462
Short name T466
Test name
Test status
Simulation time 37313659 ps
CPU time 0.53 seconds
Started Apr 18 12:22:46 PM PDT 24
Finished Apr 18 12:22:48 PM PDT 24
Peak memory 181740 kb
Host smart-9742c56f-822b-4656-8d0f-99014ed2cfc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897237462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2897237462
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2481415887
Short name T506
Test name
Test status
Simulation time 16609921 ps
CPU time 0.6 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 179952 kb
Host smart-80aae586-d4fc-4d1c-86fe-fc69ebe2cbf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481415887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2481415887
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1744996381
Short name T487
Test name
Test status
Simulation time 15875795 ps
CPU time 0.58 seconds
Started Apr 18 12:20:28 PM PDT 24
Finished Apr 18 12:20:29 PM PDT 24
Peak memory 182644 kb
Host smart-8761db8e-da5b-4500-83d7-02989def5071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744996381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1744996381
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2833427877
Short name T576
Test name
Test status
Simulation time 32628816 ps
CPU time 0.63 seconds
Started Apr 18 12:21:04 PM PDT 24
Finished Apr 18 12:21:05 PM PDT 24
Peak memory 182328 kb
Host smart-342d1032-193f-4d17-9214-867500dec2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833427877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2833427877
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3413999203
Short name T485
Test name
Test status
Simulation time 31404824 ps
CPU time 0.6 seconds
Started Apr 18 12:23:51 PM PDT 24
Finished Apr 18 12:23:54 PM PDT 24
Peak memory 181340 kb
Host smart-4adb9c1e-ab0a-4426-9489-d0000d41da28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413999203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3413999203
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2984370124
Short name T577
Test name
Test status
Simulation time 36783537 ps
CPU time 0.56 seconds
Started Apr 18 12:20:28 PM PDT 24
Finished Apr 18 12:20:29 PM PDT 24
Peak memory 182048 kb
Host smart-0dbd8770-eacc-44eb-8c5f-91b92b9beb1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984370124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2984370124
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3635939686
Short name T507
Test name
Test status
Simulation time 11049841 ps
CPU time 0.53 seconds
Started Apr 18 12:23:51 PM PDT 24
Finished Apr 18 12:23:54 PM PDT 24
Peak memory 180680 kb
Host smart-6ce7e8bc-80a9-4721-8e10-67de2003b9c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635939686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3635939686
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2732301346
Short name T525
Test name
Test status
Simulation time 275330606 ps
CPU time 0.9 seconds
Started Apr 18 12:21:22 PM PDT 24
Finished Apr 18 12:21:23 PM PDT 24
Peak memory 197048 kb
Host smart-0a2ebb5a-6059-467f-9aee-b84786f656d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732301346 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2732301346
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1645400292
Short name T548
Test name
Test status
Simulation time 14939959 ps
CPU time 0.57 seconds
Started Apr 18 12:20:03 PM PDT 24
Finished Apr 18 12:20:04 PM PDT 24
Peak memory 182540 kb
Host smart-0ec757d3-0490-4188-9b2c-29d0af0eaec7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645400292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1645400292
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2193145956
Short name T558
Test name
Test status
Simulation time 16397537 ps
CPU time 0.55 seconds
Started Apr 18 12:18:50 PM PDT 24
Finished Apr 18 12:18:51 PM PDT 24
Peak memory 182304 kb
Host smart-35d75f0c-d050-4416-8297-07a7f548c51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193145956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2193145956
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1735172481
Short name T572
Test name
Test status
Simulation time 32903986 ps
CPU time 0.78 seconds
Started Apr 18 12:20:23 PM PDT 24
Finished Apr 18 12:20:24 PM PDT 24
Peak memory 193116 kb
Host smart-216ee091-27bd-4697-889d-f4036979f702
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735172481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1735172481
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2831766143
Short name T477
Test name
Test status
Simulation time 98788168 ps
CPU time 1.72 seconds
Started Apr 18 12:23:42 PM PDT 24
Finished Apr 18 12:23:45 PM PDT 24
Peak memory 196352 kb
Host smart-68808d5b-64bf-415b-a9d8-e13d8de43e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831766143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2831766143
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3614715392
Short name T534
Test name
Test status
Simulation time 1394291918 ps
CPU time 1.24 seconds
Started Apr 18 12:23:43 PM PDT 24
Finished Apr 18 12:23:45 PM PDT 24
Peak memory 182236 kb
Host smart-c63504ca-9621-4c7e-8d0b-1fd0581f2c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614715392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3614715392
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.201780874
Short name T570
Test name
Test status
Simulation time 34828609 ps
CPU time 0.99 seconds
Started Apr 18 12:19:19 PM PDT 24
Finished Apr 18 12:19:21 PM PDT 24
Peak memory 196184 kb
Host smart-942e3725-5cbd-4868-8791-9222854adb16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201780874 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.201780874
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.544823441
Short name T541
Test name
Test status
Simulation time 46446748 ps
CPU time 0.58 seconds
Started Apr 18 12:20:10 PM PDT 24
Finished Apr 18 12:20:12 PM PDT 24
Peak memory 182692 kb
Host smart-2d6de52b-d422-4957-99a9-fde063453547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544823441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.544823441
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4213767949
Short name T561
Test name
Test status
Simulation time 15043746 ps
CPU time 0.55 seconds
Started Apr 18 12:22:40 PM PDT 24
Finished Apr 18 12:22:41 PM PDT 24
Peak memory 181964 kb
Host smart-521a22d1-03f4-4e0f-a127-9096ae90f9a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213767949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4213767949
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3325526512
Short name T89
Test name
Test status
Simulation time 24113617 ps
CPU time 0.83 seconds
Started Apr 18 12:18:50 PM PDT 24
Finished Apr 18 12:18:52 PM PDT 24
Peak memory 193464 kb
Host smart-ab37e266-5670-4ee4-b267-a9bdaf4f9509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325526512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3325526512
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2813347326
Short name T486
Test name
Test status
Simulation time 215645552 ps
CPU time 2.37 seconds
Started Apr 18 12:20:10 PM PDT 24
Finished Apr 18 12:20:13 PM PDT 24
Peak memory 197348 kb
Host smart-cbcbef25-7437-4027-b0ec-a571a8c84395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813347326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2813347326
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2828246847
Short name T28
Test name
Test status
Simulation time 140179658 ps
CPU time 0.81 seconds
Started Apr 18 12:20:12 PM PDT 24
Finished Apr 18 12:20:15 PM PDT 24
Peak memory 193224 kb
Host smart-dceb2b0b-36ad-4092-8867-b860d57c6c86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828246847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2828246847
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1341499559
Short name T512
Test name
Test status
Simulation time 41890024 ps
CPU time 0.74 seconds
Started Apr 18 12:22:58 PM PDT 24
Finished Apr 18 12:23:00 PM PDT 24
Peak memory 194088 kb
Host smart-bf8ce60e-5b8b-4930-a932-6049352e2f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341499559 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1341499559
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1920676449
Short name T579
Test name
Test status
Simulation time 27243810 ps
CPU time 0.57 seconds
Started Apr 18 12:23:55 PM PDT 24
Finished Apr 18 12:23:56 PM PDT 24
Peak memory 180496 kb
Host smart-39853c1c-4eee-4bb7-8045-46e83cc21728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920676449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1920676449
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3114947042
Short name T483
Test name
Test status
Simulation time 27424719 ps
CPU time 0.57 seconds
Started Apr 18 12:20:53 PM PDT 24
Finished Apr 18 12:20:54 PM PDT 24
Peak memory 182196 kb
Host smart-2a20f449-2117-452f-8db2-04221f49721a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114947042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3114947042
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1650958440
Short name T95
Test name
Test status
Simulation time 74542177 ps
CPU time 0.64 seconds
Started Apr 18 12:22:29 PM PDT 24
Finished Apr 18 12:22:31 PM PDT 24
Peak memory 191500 kb
Host smart-19b10fc3-9dcb-4b26-9fca-03a8a35dd448
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650958440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1650958440
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2268163668
Short name T526
Test name
Test status
Simulation time 40097623 ps
CPU time 1.88 seconds
Started Apr 18 12:20:13 PM PDT 24
Finished Apr 18 12:20:16 PM PDT 24
Peak memory 197536 kb
Host smart-a4000e9d-9f5e-4572-9445-b5079f974a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268163668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2268163668
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1336170137
Short name T508
Test name
Test status
Simulation time 46623857 ps
CPU time 0.77 seconds
Started Apr 18 12:23:49 PM PDT 24
Finished Apr 18 12:23:50 PM PDT 24
Peak memory 193524 kb
Host smart-8ac9ecc2-979e-4445-b775-2a4f79f01e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336170137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1336170137
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.402570569
Short name T524
Test name
Test status
Simulation time 140944381 ps
CPU time 0.87 seconds
Started Apr 18 12:21:40 PM PDT 24
Finished Apr 18 12:21:41 PM PDT 24
Peak memory 196332 kb
Host smart-3a0a46e6-42b2-47ea-9ad6-f7091017ecc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402570569 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.402570569
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.954884786
Short name T69
Test name
Test status
Simulation time 13802948 ps
CPU time 0.59 seconds
Started Apr 18 12:19:07 PM PDT 24
Finished Apr 18 12:19:08 PM PDT 24
Peak memory 182492 kb
Host smart-26ea99a7-9d92-4d51-96e7-b15209eac9ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954884786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.954884786
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.75515475
Short name T462
Test name
Test status
Simulation time 48153962 ps
CPU time 0.54 seconds
Started Apr 18 12:21:52 PM PDT 24
Finished Apr 18 12:21:53 PM PDT 24
Peak memory 181960 kb
Host smart-ab6d184d-7369-4048-ace4-339c6ce5a1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75515475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.75515475
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.516207644
Short name T94
Test name
Test status
Simulation time 115722425 ps
CPU time 0.75 seconds
Started Apr 18 12:22:45 PM PDT 24
Finished Apr 18 12:22:47 PM PDT 24
Peak memory 192480 kb
Host smart-7e491a40-2c2a-43d3-907f-33acedc98a6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516207644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.516207644
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3545124383
Short name T457
Test name
Test status
Simulation time 181356284 ps
CPU time 1.77 seconds
Started Apr 18 12:23:04 PM PDT 24
Finished Apr 18 12:23:06 PM PDT 24
Peak memory 197056 kb
Host smart-2689e3f6-9fdf-41a2-b579-3fcee1ceb241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545124383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3545124383
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.864721296
Short name T99
Test name
Test status
Simulation time 168112169 ps
CPU time 1.14 seconds
Started Apr 18 12:23:33 PM PDT 24
Finished Apr 18 12:23:36 PM PDT 24
Peak memory 194136 kb
Host smart-325cfb59-fd7b-47e0-9b08-8805f590a945
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864721296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.864721296
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3409346510
Short name T455
Test name
Test status
Simulation time 44438440 ps
CPU time 0.73 seconds
Started Apr 18 12:22:42 PM PDT 24
Finished Apr 18 12:22:44 PM PDT 24
Peak memory 194344 kb
Host smart-721b2834-3644-41e2-95f2-b715bc2ad6c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409346510 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3409346510
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.306083465
Short name T516
Test name
Test status
Simulation time 54330842 ps
CPU time 0.61 seconds
Started Apr 18 12:23:31 PM PDT 24
Finished Apr 18 12:23:33 PM PDT 24
Peak memory 181048 kb
Host smart-5fe9194b-0531-4162-995f-e060d6b0184b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306083465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.306083465
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2148263719
Short name T489
Test name
Test status
Simulation time 52661220 ps
CPU time 0.51 seconds
Started Apr 18 12:23:55 PM PDT 24
Finished Apr 18 12:23:57 PM PDT 24
Peak memory 181708 kb
Host smart-9e2c6df6-2661-47c9-b89d-576992529d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148263719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2148263719
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1435293864
Short name T88
Test name
Test status
Simulation time 118953818 ps
CPU time 0.67 seconds
Started Apr 18 12:20:49 PM PDT 24
Finished Apr 18 12:20:52 PM PDT 24
Peak memory 189744 kb
Host smart-4b9c7cbd-4875-4692-a1ce-749fdd0e36a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435293864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1435293864
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.826120084
Short name T510
Test name
Test status
Simulation time 143338818 ps
CPU time 0.96 seconds
Started Apr 18 12:22:45 PM PDT 24
Finished Apr 18 12:22:47 PM PDT 24
Peak memory 194872 kb
Host smart-d7adc0e1-1dd7-4521-a41e-3f53c54b5d61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826120084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.826120084
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.588988425
Short name T98
Test name
Test status
Simulation time 49799527 ps
CPU time 0.8 seconds
Started Apr 18 12:22:46 PM PDT 24
Finished Apr 18 12:22:48 PM PDT 24
Peak memory 192948 kb
Host smart-0de1f159-6f35-4ab4-a1a7-00135a0fba5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588988425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.588988425
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2855839877
Short name T413
Test name
Test status
Simulation time 316180237718 ps
CPU time 103.92 seconds
Started Apr 18 12:17:55 PM PDT 24
Finished Apr 18 12:19:40 PM PDT 24
Peak memory 182520 kb
Host smart-fe385aea-e803-4adc-ad50-9d987cffa13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855839877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2855839877
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1086404407
Short name T4
Test name
Test status
Simulation time 30088665623 ps
CPU time 16.59 seconds
Started Apr 18 12:18:03 PM PDT 24
Finished Apr 18 12:18:21 PM PDT 24
Peak memory 181680 kb
Host smart-1b302d2d-7ad8-4940-a6ee-ee3e66a419a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086404407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1086404407
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1237829445
Short name T7
Test name
Test status
Simulation time 402856073322 ps
CPU time 686.61 seconds
Started Apr 18 12:23:23 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 190388 kb
Host smart-5f1135d4-bcf1-40cc-89ab-2dcea3c05695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237829445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1237829445
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1942388780
Short name T299
Test name
Test status
Simulation time 668154330312 ps
CPU time 563 seconds
Started Apr 18 12:24:28 PM PDT 24
Finished Apr 18 12:33:52 PM PDT 24
Peak memory 182228 kb
Host smart-9073aa4e-2138-43d1-8053-0f97e994552f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942388780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1942388780
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.879034343
Short name T351
Test name
Test status
Simulation time 241456922546 ps
CPU time 67.76 seconds
Started Apr 18 12:18:38 PM PDT 24
Finished Apr 18 12:19:47 PM PDT 24
Peak memory 182432 kb
Host smart-36b01e70-e953-473a-abb8-1c015ae88fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879034343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.879034343
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3136555853
Short name T406
Test name
Test status
Simulation time 40037289214 ps
CPU time 326.45 seconds
Started Apr 18 12:20:54 PM PDT 24
Finished Apr 18 12:26:21 PM PDT 24
Peak memory 182536 kb
Host smart-a87ea1ff-42ce-4f28-8667-f3da596d1259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136555853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3136555853
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3519019334
Short name T2
Test name
Test status
Simulation time 120921553 ps
CPU time 0.93 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:22:53 PM PDT 24
Peak memory 190216 kb
Host smart-a97557e1-a312-4073-9a32-fb53a85c3a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519019334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3519019334
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1200135162
Short name T15
Test name
Test status
Simulation time 140291214 ps
CPU time 0.85 seconds
Started Apr 18 12:18:48 PM PDT 24
Finished Apr 18 12:18:49 PM PDT 24
Peak memory 213584 kb
Host smart-86f9ba63-5128-45fe-b06b-8386bd137593
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200135162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1200135162
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.612281708
Short name T275
Test name
Test status
Simulation time 513709314607 ps
CPU time 1548.84 seconds
Started Apr 18 12:20:23 PM PDT 24
Finished Apr 18 12:46:12 PM PDT 24
Peak memory 190612 kb
Host smart-b639cf47-f37f-4274-b6cd-9d8e80421125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612281708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.612281708
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3736262404
Short name T33
Test name
Test status
Simulation time 12376413279 ps
CPU time 60.67 seconds
Started Apr 18 12:19:51 PM PDT 24
Finished Apr 18 12:20:52 PM PDT 24
Peak memory 197176 kb
Host smart-0071b288-04fa-441e-a48b-490cb6fad3cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736262404 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3736262404
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2056229902
Short name T249
Test name
Test status
Simulation time 326394900909 ps
CPU time 162.5 seconds
Started Apr 18 12:23:05 PM PDT 24
Finished Apr 18 12:25:48 PM PDT 24
Peak memory 182228 kb
Host smart-083b89b9-8d49-49e9-833f-baf798bc48ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056229902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2056229902
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3368147433
Short name T61
Test name
Test status
Simulation time 92438410145 ps
CPU time 142.33 seconds
Started Apr 18 12:22:12 PM PDT 24
Finished Apr 18 12:24:35 PM PDT 24
Peak memory 182484 kb
Host smart-2aec352b-1a53-4885-8374-ff98948bb81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368147433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3368147433
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.4259866404
Short name T435
Test name
Test status
Simulation time 134384619043 ps
CPU time 142.07 seconds
Started Apr 18 12:23:30 PM PDT 24
Finished Apr 18 12:25:52 PM PDT 24
Peak memory 190384 kb
Host smart-cbe4dd81-73a1-44f3-9bb7-411f69ba6a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259866404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4259866404
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1264549371
Short name T301
Test name
Test status
Simulation time 1884173540410 ps
CPU time 721.02 seconds
Started Apr 18 12:23:04 PM PDT 24
Finished Apr 18 12:35:06 PM PDT 24
Peak memory 190420 kb
Host smart-990c00e4-1da9-4e31-b1c0-cad560e9ccb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264549371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1264549371
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2534362571
Short name T47
Test name
Test status
Simulation time 19707371115 ps
CPU time 142.45 seconds
Started Apr 18 12:20:40 PM PDT 24
Finished Apr 18 12:23:03 PM PDT 24
Peak memory 197140 kb
Host smart-6a5b22ca-e5e1-4feb-8c52-3763ed576b6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534362571 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2534362571
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.rv_timer_random.1679326346
Short name T44
Test name
Test status
Simulation time 26874049295 ps
CPU time 14.73 seconds
Started Apr 18 12:24:52 PM PDT 24
Finished Apr 18 12:25:07 PM PDT 24
Peak memory 182392 kb
Host smart-1469ec80-ed13-4899-ae89-b37b4e61db59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679326346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1679326346
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1986218783
Short name T139
Test name
Test status
Simulation time 353613441027 ps
CPU time 224.75 seconds
Started Apr 18 12:23:22 PM PDT 24
Finished Apr 18 12:27:07 PM PDT 24
Peak memory 190676 kb
Host smart-e92b638e-d9e1-4d01-8161-ec3492ba86cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986218783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1986218783
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1173117203
Short name T103
Test name
Test status
Simulation time 612082226091 ps
CPU time 372.18 seconds
Started Apr 18 12:23:21 PM PDT 24
Finished Apr 18 12:29:34 PM PDT 24
Peak memory 190684 kb
Host smart-35151af7-2c04-4583-89d6-3f8ac698d2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173117203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1173117203
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1934231194
Short name T269
Test name
Test status
Simulation time 69641657807 ps
CPU time 58.14 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:24:27 PM PDT 24
Peak memory 182432 kb
Host smart-c6d655e9-ec10-4b4f-a535-7bc06558cbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934231194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1934231194
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1407968968
Short name T276
Test name
Test status
Simulation time 39770092456 ps
CPU time 68.77 seconds
Started Apr 18 12:23:36 PM PDT 24
Finished Apr 18 12:24:46 PM PDT 24
Peak memory 190672 kb
Host smart-9f321f04-5d4f-4ace-a9ce-530b57db4d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407968968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1407968968
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1396328000
Short name T258
Test name
Test status
Simulation time 129410464754 ps
CPU time 63.7 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:24:42 PM PDT 24
Peak memory 182360 kb
Host smart-97056834-224e-4b22-9f16-c237a07c90b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396328000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1396328000
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1128388104
Short name T370
Test name
Test status
Simulation time 78213564160 ps
CPU time 70.91 seconds
Started Apr 18 12:23:05 PM PDT 24
Finished Apr 18 12:24:17 PM PDT 24
Peak memory 182216 kb
Host smart-fb8c333f-0be8-483d-996c-87f700971c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128388104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1128388104
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2194142749
Short name T175
Test name
Test status
Simulation time 68972082156 ps
CPU time 48.44 seconds
Started Apr 18 12:23:04 PM PDT 24
Finished Apr 18 12:23:53 PM PDT 24
Peak memory 190388 kb
Host smart-97981f5b-d3e0-4e8b-8c48-cda718506c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194142749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2194142749
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2734336365
Short name T290
Test name
Test status
Simulation time 151383711315 ps
CPU time 135.11 seconds
Started Apr 18 12:22:38 PM PDT 24
Finished Apr 18 12:24:54 PM PDT 24
Peak memory 188448 kb
Host smart-9e95f03e-baf6-4c21-824e-cf3b9f6bc087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734336365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2734336365
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3329901170
Short name T335
Test name
Test status
Simulation time 341798294721 ps
CPU time 785.55 seconds
Started Apr 18 12:21:33 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 190796 kb
Host smart-962595d8-de04-4adb-8903-6426a29da809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329901170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3329901170
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.4253861796
Short name T67
Test name
Test status
Simulation time 43222465361 ps
CPU time 425.3 seconds
Started Apr 18 12:23:00 PM PDT 24
Finished Apr 18 12:30:07 PM PDT 24
Peak memory 204788 kb
Host smart-50ed17d6-137c-4ed0-9bd1-10a45151e502
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253861796 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.4253861796
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2305244271
Short name T319
Test name
Test status
Simulation time 105815743362 ps
CPU time 463.62 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 190632 kb
Host smart-8efe3a6a-ad46-46e6-b497-47a54c2dacab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305244271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2305244271
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.727226113
Short name T328
Test name
Test status
Simulation time 185632602347 ps
CPU time 83.24 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:25:02 PM PDT 24
Peak memory 182364 kb
Host smart-eaea22af-4e65-4839-9510-4cad663dfc1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727226113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.727226113
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2065900577
Short name T163
Test name
Test status
Simulation time 631372648784 ps
CPU time 1459.18 seconds
Started Apr 18 12:23:36 PM PDT 24
Finished Apr 18 12:47:56 PM PDT 24
Peak memory 190672 kb
Host smart-406922ef-50bb-4983-bc7c-61a20ab158c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065900577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2065900577
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.90177605
Short name T251
Test name
Test status
Simulation time 80772191662 ps
CPU time 2772.08 seconds
Started Apr 18 12:23:32 PM PDT 24
Finished Apr 18 01:09:45 PM PDT 24
Peak memory 190560 kb
Host smart-89648e29-522b-443b-be25-b022fe165eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90177605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.90177605
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.988088308
Short name T62
Test name
Test status
Simulation time 1772865325929 ps
CPU time 405.52 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 190564 kb
Host smart-3c145fe0-af18-4918-9a3d-76af6cb88657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988088308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.988088308
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.750482176
Short name T419
Test name
Test status
Simulation time 23836276834 ps
CPU time 17.62 seconds
Started Apr 18 12:23:33 PM PDT 24
Finished Apr 18 12:23:52 PM PDT 24
Peak memory 182432 kb
Host smart-c904f956-e793-47cb-95cb-4e96088f3d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750482176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.750482176
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1770069915
Short name T65
Test name
Test status
Simulation time 18060452522 ps
CPU time 20.08 seconds
Started Apr 18 12:24:40 PM PDT 24
Finished Apr 18 12:25:01 PM PDT 24
Peak memory 182184 kb
Host smart-269ccdaf-6f0b-4ff3-9641-164aba838f6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770069915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1770069915
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.416743401
Short name T126
Test name
Test status
Simulation time 219947623886 ps
CPU time 96.56 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:25:06 PM PDT 24
Peak memory 182180 kb
Host smart-43aa8eac-e2e6-4039-87aa-701826317991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416743401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.416743401
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.4188752588
Short name T137
Test name
Test status
Simulation time 14642503669 ps
CPU time 25.17 seconds
Started Apr 18 12:23:10 PM PDT 24
Finished Apr 18 12:23:36 PM PDT 24
Peak memory 182180 kb
Host smart-a2b0f044-f127-4417-806c-451062eff678
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188752588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.4188752588
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1567494100
Short name T437
Test name
Test status
Simulation time 24732911251 ps
CPU time 36.08 seconds
Started Apr 18 12:23:10 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 182176 kb
Host smart-a32cd548-49e3-4dcb-a07b-279c8158c8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567494100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1567494100
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.224415749
Short name T159
Test name
Test status
Simulation time 225765893354 ps
CPU time 650.02 seconds
Started Apr 18 12:23:10 PM PDT 24
Finished Apr 18 12:34:00 PM PDT 24
Peak memory 192696 kb
Host smart-39ff82a8-977e-4bd7-98fc-489f4fa0c006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224415749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.224415749
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1623969064
Short name T154
Test name
Test status
Simulation time 285480198876 ps
CPU time 147.54 seconds
Started Apr 18 12:23:37 PM PDT 24
Finished Apr 18 12:26:05 PM PDT 24
Peak memory 190672 kb
Host smart-aa7d0f90-c206-4cef-b465-2f1c03fea8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623969064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1623969064
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.477101757
Short name T308
Test name
Test status
Simulation time 1492166001 ps
CPU time 2.98 seconds
Started Apr 18 12:24:40 PM PDT 24
Finished Apr 18 12:24:44 PM PDT 24
Peak memory 181884 kb
Host smart-9d84d6de-aeb1-4f32-9edf-6201f00f3d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477101757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.477101757
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2406287644
Short name T374
Test name
Test status
Simulation time 111261084247 ps
CPU time 51.83 seconds
Started Apr 18 12:23:33 PM PDT 24
Finished Apr 18 12:24:25 PM PDT 24
Peak memory 182424 kb
Host smart-ef06b5fc-5696-402c-8948-174a9243db52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406287644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2406287644
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.323607180
Short name T41
Test name
Test status
Simulation time 215259208049 ps
CPU time 413.33 seconds
Started Apr 18 12:24:41 PM PDT 24
Finished Apr 18 12:31:35 PM PDT 24
Peak memory 190344 kb
Host smart-0511e183-9dca-44c2-b283-9bc809f1762a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323607180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.323607180
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1282022167
Short name T294
Test name
Test status
Simulation time 15683170173 ps
CPU time 28.11 seconds
Started Apr 18 12:23:39 PM PDT 24
Finished Apr 18 12:24:08 PM PDT 24
Peak memory 182360 kb
Host smart-1ea8cabd-eec7-44c5-acc4-c91912b10f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282022167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1282022167
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3416067690
Short name T193
Test name
Test status
Simulation time 2112933961873 ps
CPU time 1044.48 seconds
Started Apr 18 12:23:37 PM PDT 24
Finished Apr 18 12:41:02 PM PDT 24
Peak memory 193220 kb
Host smart-60014444-8d2f-40f2-a4a0-e7298350ff10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416067690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3416067690
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2534507845
Short name T120
Test name
Test status
Simulation time 161669596929 ps
CPU time 149.8 seconds
Started Apr 18 12:23:37 PM PDT 24
Finished Apr 18 12:26:07 PM PDT 24
Peak memory 190672 kb
Host smart-cf0d9143-96b7-49c3-be37-9923b24b5d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534507845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2534507845
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3158169716
Short name T127
Test name
Test status
Simulation time 498666184179 ps
CPU time 457.91 seconds
Started Apr 18 12:20:57 PM PDT 24
Finished Apr 18 12:28:36 PM PDT 24
Peak memory 182388 kb
Host smart-a0ea6d3f-e738-44d2-8176-517c2f6f8ff5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158169716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3158169716
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1603746104
Short name T421
Test name
Test status
Simulation time 345538715744 ps
CPU time 144.13 seconds
Started Apr 18 12:23:42 PM PDT 24
Finished Apr 18 12:26:07 PM PDT 24
Peak memory 182052 kb
Host smart-40bea8d2-36cd-406d-b4be-a47e73fafb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603746104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1603746104
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1116846571
Short name T113
Test name
Test status
Simulation time 449823631544 ps
CPU time 248.65 seconds
Started Apr 18 12:22:48 PM PDT 24
Finished Apr 18 12:26:58 PM PDT 24
Peak memory 187800 kb
Host smart-1af055ae-2b33-4103-94d1-6001a24d5e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116846571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1116846571
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.4241640520
Short name T389
Test name
Test status
Simulation time 6407921805 ps
CPU time 11.58 seconds
Started Apr 18 12:23:42 PM PDT 24
Finished Apr 18 12:23:55 PM PDT 24
Peak memory 181392 kb
Host smart-afa8479d-93b8-423b-b549-7278a93f3820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241640520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.4241640520
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3422067423
Short name T6
Test name
Test status
Simulation time 188387343354 ps
CPU time 98.9 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:25:09 PM PDT 24
Peak memory 190372 kb
Host smart-f7b4b512-f066-4030-96cd-f85c4b66f860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422067423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3422067423
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1059661684
Short name T343
Test name
Test status
Simulation time 51751197260 ps
CPU time 26.35 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:24:11 PM PDT 24
Peak memory 182432 kb
Host smart-34de063c-54c8-42b4-a397-18991c237edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059661684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1059661684
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.556054629
Short name T125
Test name
Test status
Simulation time 133643861562 ps
CPU time 60.04 seconds
Started Apr 18 12:23:34 PM PDT 24
Finished Apr 18 12:24:35 PM PDT 24
Peak memory 182364 kb
Host smart-9b1e5aaa-a03d-4250-9fe1-6698609e5c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556054629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.556054629
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.773779214
Short name T100
Test name
Test status
Simulation time 117790528473 ps
CPU time 220.97 seconds
Started Apr 18 12:23:32 PM PDT 24
Finished Apr 18 12:27:14 PM PDT 24
Peak memory 193312 kb
Host smart-8e48a90d-70a8-4a46-bb9d-8f39a9c3d0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773779214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.773779214
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2768534899
Short name T281
Test name
Test status
Simulation time 167855439876 ps
CPU time 1375.14 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 190588 kb
Host smart-b44f2398-14de-4c11-92e9-2cf0747da4ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768534899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2768534899
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1264858168
Short name T339
Test name
Test status
Simulation time 286312575988 ps
CPU time 172.63 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:26:40 PM PDT 24
Peak memory 190584 kb
Host smart-ff18de91-59e7-4885-b7cd-625f6362c542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264858168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1264858168
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3198879880
Short name T325
Test name
Test status
Simulation time 100404684481 ps
CPU time 143.85 seconds
Started Apr 18 12:23:34 PM PDT 24
Finished Apr 18 12:25:59 PM PDT 24
Peak memory 190632 kb
Host smart-1cf1c784-9022-4168-9ef2-7f42a27d2b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198879880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3198879880
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.504789110
Short name T22
Test name
Test status
Simulation time 636499467815 ps
CPU time 489.51 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 190564 kb
Host smart-52546d86-74de-437d-a9d0-020f1624a960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504789110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.504789110
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3031047678
Short name T235
Test name
Test status
Simulation time 50725527365 ps
CPU time 40.51 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:24:29 PM PDT 24
Peak memory 182412 kb
Host smart-d4575a5c-9492-4de7-826d-334407c142c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031047678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3031047678
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.915110102
Short name T434
Test name
Test status
Simulation time 334652940003 ps
CPU time 146.82 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:26:15 PM PDT 24
Peak memory 190028 kb
Host smart-26cb5c79-bf7b-4ccf-8480-ee3b21f3ecb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915110102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.915110102
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.370133213
Short name T399
Test name
Test status
Simulation time 244925431962 ps
CPU time 158.85 seconds
Started Apr 18 12:22:48 PM PDT 24
Finished Apr 18 12:25:28 PM PDT 24
Peak memory 179772 kb
Host smart-9d62c9b8-b04e-40a2-a820-699830216a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370133213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.370133213
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1789234788
Short name T265
Test name
Test status
Simulation time 45656901877 ps
CPU time 72.38 seconds
Started Apr 18 12:22:48 PM PDT 24
Finished Apr 18 12:24:02 PM PDT 24
Peak memory 179316 kb
Host smart-b73b0088-a106-46c2-b2fa-705f57bc56bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789234788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1789234788
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.151666971
Short name T317
Test name
Test status
Simulation time 12888255723 ps
CPU time 11.97 seconds
Started Apr 18 12:22:58 PM PDT 24
Finished Apr 18 12:23:11 PM PDT 24
Peak memory 193592 kb
Host smart-dff6b8a3-2710-435f-a4de-c596b94d46b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151666971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.151666971
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.3125949007
Short name T442
Test name
Test status
Simulation time 76156325660 ps
CPU time 401.32 seconds
Started Apr 18 12:23:34 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 190560 kb
Host smart-ebb83a7d-0e39-4384-a31e-ab88a38f03b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125949007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3125949007
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3311942928
Short name T179
Test name
Test status
Simulation time 819715740625 ps
CPU time 598.36 seconds
Started Apr 18 12:23:43 PM PDT 24
Finished Apr 18 12:33:42 PM PDT 24
Peak memory 190604 kb
Host smart-e4d96c7d-61e4-4f37-8177-ab40020264c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311942928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3311942928
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1334868718
Short name T63
Test name
Test status
Simulation time 642763959723 ps
CPU time 777.89 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:36:43 PM PDT 24
Peak memory 190468 kb
Host smart-bf8f6b1e-4573-4ea0-bb46-af82d3301c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334868718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1334868718
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3782382382
Short name T122
Test name
Test status
Simulation time 194154212562 ps
CPU time 914.11 seconds
Started Apr 18 12:23:37 PM PDT 24
Finished Apr 18 12:38:52 PM PDT 24
Peak memory 182472 kb
Host smart-3011a86b-d530-4867-94af-653fc97143ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782382382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3782382382
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2809052727
Short name T451
Test name
Test status
Simulation time 286414186939 ps
CPU time 144.61 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:26:13 PM PDT 24
Peak memory 190612 kb
Host smart-0c901918-a270-4302-b6c6-b78c409b0e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809052727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2809052727
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.458734255
Short name T307
Test name
Test status
Simulation time 174379254153 ps
CPU time 89.29 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:25:18 PM PDT 24
Peak memory 190600 kb
Host smart-40b9d116-9e73-47b4-ad17-d620e5191f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458734255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.458734255
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.972957192
Short name T141
Test name
Test status
Simulation time 35130928809 ps
CPU time 56.43 seconds
Started Apr 18 12:20:55 PM PDT 24
Finished Apr 18 12:21:52 PM PDT 24
Peak memory 182536 kb
Host smart-bdc42727-a8c7-47db-b277-03a3944a0311
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972957192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.972957192
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.557619804
Short name T373
Test name
Test status
Simulation time 267563728003 ps
CPU time 199.14 seconds
Started Apr 18 12:22:49 PM PDT 24
Finished Apr 18 12:26:09 PM PDT 24
Peak memory 181924 kb
Host smart-6c058a25-8946-43d6-9192-e3f917fbf6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557619804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.557619804
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3335419803
Short name T131
Test name
Test status
Simulation time 177469335048 ps
CPU time 376.83 seconds
Started Apr 18 12:21:34 PM PDT 24
Finished Apr 18 12:27:52 PM PDT 24
Peak memory 190796 kb
Host smart-c1eefdf3-4405-4393-8d8a-7aa2ea87201c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335419803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3335419803
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3113493959
Short name T157
Test name
Test status
Simulation time 118488135762 ps
CPU time 545.55 seconds
Started Apr 18 12:23:09 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 193840 kb
Host smart-ef71cf91-2605-4b0a-affc-7654ca0f611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113493959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3113493959
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.1043637991
Short name T119
Test name
Test status
Simulation time 24037156923 ps
CPU time 13.64 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:24:00 PM PDT 24
Peak memory 182412 kb
Host smart-f2845e82-9c52-43a2-a984-b7287ba496b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043637991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1043637991
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.635715797
Short name T271
Test name
Test status
Simulation time 783583375857 ps
CPU time 1751.3 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:53:00 PM PDT 24
Peak memory 190064 kb
Host smart-d8f8a171-1e5d-44dd-9d26-85350d746fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635715797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.635715797
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3427793611
Short name T149
Test name
Test status
Simulation time 41399773668 ps
CPU time 69.99 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:24:55 PM PDT 24
Peak memory 182272 kb
Host smart-6ec37bd7-57e8-4444-89c6-b09d04c4be65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427793611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3427793611
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1779959534
Short name T144
Test name
Test status
Simulation time 74166831977 ps
CPU time 203.55 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:27:02 PM PDT 24
Peak memory 190664 kb
Host smart-a20436d3-e162-4204-9dba-27f0a562acdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779959534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1779959534
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2035694441
Short name T178
Test name
Test status
Simulation time 170534127415 ps
CPU time 81.94 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:25:04 PM PDT 24
Peak memory 182360 kb
Host smart-2970c7f9-ba9b-4935-ba68-6d6a77aeccf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035694441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2035694441
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.732009229
Short name T332
Test name
Test status
Simulation time 366412196060 ps
CPU time 603.78 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:33:52 PM PDT 24
Peak memory 190492 kb
Host smart-86f16dc5-34d9-4956-9e87-411d912f5a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732009229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.732009229
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3203313306
Short name T241
Test name
Test status
Simulation time 176353231316 ps
CPU time 796.68 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:37:04 PM PDT 24
Peak memory 192944 kb
Host smart-79e26ab3-f935-41e2-96b6-cb987fc00ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203313306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3203313306
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2535853208
Short name T239
Test name
Test status
Simulation time 2376678479607 ps
CPU time 525.9 seconds
Started Apr 18 12:23:05 PM PDT 24
Finished Apr 18 12:31:52 PM PDT 24
Peak memory 182228 kb
Host smart-06add7b3-2ed0-4e1a-a824-0e17d0e8289e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535853208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2535853208
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3497360157
Short name T379
Test name
Test status
Simulation time 1303148552 ps
CPU time 1.38 seconds
Started Apr 18 12:20:50 PM PDT 24
Finished Apr 18 12:20:52 PM PDT 24
Peak memory 182148 kb
Host smart-38daeb66-f19e-41e3-b50a-9771d6d61781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497360157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3497360157
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3769866821
Short name T116
Test name
Test status
Simulation time 331291741483 ps
CPU time 438.72 seconds
Started Apr 18 12:22:57 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 189840 kb
Host smart-6023dc73-3d98-4e7e-8563-bad59a213c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769866821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3769866821
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3797395195
Short name T19
Test name
Test status
Simulation time 84908509 ps
CPU time 0.59 seconds
Started Apr 18 12:21:39 PM PDT 24
Finished Apr 18 12:21:41 PM PDT 24
Peak memory 190744 kb
Host smart-bbe593ad-efc6-40bd-a253-4aa24aad09b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797395195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3797395195
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4000125861
Short name T372
Test name
Test status
Simulation time 196674877952 ps
CPU time 263.38 seconds
Started Apr 18 12:22:29 PM PDT 24
Finished Apr 18 12:26:54 PM PDT 24
Peak memory 193844 kb
Host smart-0a00f5e4-b913-4f63-99e5-974db97e9ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000125861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4000125861
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.50498646
Short name T49
Test name
Test status
Simulation time 246345515622 ps
CPU time 185.82 seconds
Started Apr 18 12:22:23 PM PDT 24
Finished Apr 18 12:25:30 PM PDT 24
Peak memory 205236 kb
Host smart-2bcca2f8-331a-4942-b47f-f80809caf016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50498646 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.50498646
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3873230249
Short name T5
Test name
Test status
Simulation time 284660540631 ps
CPU time 244.99 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:27:47 PM PDT 24
Peak memory 190552 kb
Host smart-2031aa04-d3b3-42b1-b949-951b9b52f73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873230249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3873230249
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2835138568
Short name T124
Test name
Test status
Simulation time 3010403501940 ps
CPU time 749.79 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 190540 kb
Host smart-ee0bc74f-b207-496e-869f-07949ac7d15c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835138568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2835138568
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2294944176
Short name T418
Test name
Test status
Simulation time 78184015347 ps
CPU time 67.55 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:24:52 PM PDT 24
Peak memory 182440 kb
Host smart-99d25d5b-e16b-4f16-99cd-18534903ab13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294944176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2294944176
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.550220171
Short name T164
Test name
Test status
Simulation time 1437982402972 ps
CPU time 741.12 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:36:03 PM PDT 24
Peak memory 190688 kb
Host smart-e6a383ca-5549-47a7-9b26-42b29f9dd1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550220171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.550220171
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.294222245
Short name T247
Test name
Test status
Simulation time 72394038219 ps
CPU time 120.31 seconds
Started Apr 18 12:23:42 PM PDT 24
Finished Apr 18 12:25:43 PM PDT 24
Peak memory 190560 kb
Host smart-239fc45b-1165-4b42-b971-647b41ddedbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294222245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.294222245
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.4267078105
Short name T369
Test name
Test status
Simulation time 556831920080 ps
CPU time 233.13 seconds
Started Apr 18 12:24:04 PM PDT 24
Finished Apr 18 12:27:58 PM PDT 24
Peak memory 182396 kb
Host smart-37108827-9a18-41c4-9761-26a24c2fa684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267078105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4267078105
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.111619650
Short name T136
Test name
Test status
Simulation time 225304173024 ps
CPU time 736.52 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:36:10 PM PDT 24
Peak memory 190364 kb
Host smart-19f6f57a-6664-41bb-9d7f-3304c0d5fbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111619650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.111619650
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2956262873
Short name T387
Test name
Test status
Simulation time 231157729 ps
CPU time 0.73 seconds
Started Apr 18 12:22:22 PM PDT 24
Finished Apr 18 12:22:24 PM PDT 24
Peak memory 190636 kb
Host smart-c45e861e-1b9e-439c-904c-99b1e4938fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956262873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2956262873
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2355299062
Short name T221
Test name
Test status
Simulation time 108446762192 ps
CPU time 1427.63 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:47:35 PM PDT 24
Peak memory 190612 kb
Host smart-c9e55cad-8b97-4640-aebd-e441954f8783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355299062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2355299062
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.596428727
Short name T321
Test name
Test status
Simulation time 73173792121 ps
CPU time 295.72 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:28:43 PM PDT 24
Peak memory 192812 kb
Host smart-2314e631-a84a-4a76-ac20-d35e03878559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596428727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.596428727
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.806125642
Short name T439
Test name
Test status
Simulation time 252134186510 ps
CPU time 220.87 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:27:32 PM PDT 24
Peak memory 192984 kb
Host smart-15e7029d-bc0e-433e-9ebf-4870015c9d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806125642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.806125642
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.565883383
Short name T109
Test name
Test status
Simulation time 284802470286 ps
CPU time 503.33 seconds
Started Apr 18 12:23:42 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 190568 kb
Host smart-df3aa863-12a0-4fd1-a5e8-24e4059533ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565883383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.565883383
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2437108733
Short name T232
Test name
Test status
Simulation time 649056617711 ps
CPU time 480.03 seconds
Started Apr 18 12:23:40 PM PDT 24
Finished Apr 18 12:31:41 PM PDT 24
Peak memory 190616 kb
Host smart-37d8a479-c9ab-4a0c-bd85-44f455a96349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437108733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2437108733
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2912373382
Short name T305
Test name
Test status
Simulation time 367634497604 ps
CPU time 109.84 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:25:41 PM PDT 24
Peak memory 190588 kb
Host smart-e87569a3-e077-439c-8f00-209132c87784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912373382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2912373382
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3799223966
Short name T291
Test name
Test status
Simulation time 51969083416 ps
CPU time 61.93 seconds
Started Apr 18 12:23:48 PM PDT 24
Finished Apr 18 12:24:51 PM PDT 24
Peak memory 182412 kb
Host smart-1e40ec96-5486-4d54-a79a-2a265691455d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799223966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3799223966
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2221890474
Short name T230
Test name
Test status
Simulation time 94161377880 ps
CPU time 154.94 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:26:21 PM PDT 24
Peak memory 190540 kb
Host smart-a8d43b23-ed13-4604-80c5-d9f9769f8969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221890474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2221890474
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1925486185
Short name T160
Test name
Test status
Simulation time 67621647457 ps
CPU time 105.93 seconds
Started Apr 18 12:23:40 PM PDT 24
Finished Apr 18 12:25:26 PM PDT 24
Peak memory 190592 kb
Host smart-700d2ada-a80f-4581-8461-0cc46e1eebb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925486185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1925486185
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.756369019
Short name T416
Test name
Test status
Simulation time 195785981697 ps
CPU time 370.95 seconds
Started Apr 18 12:24:06 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 182408 kb
Host smart-805b1b2b-4e5d-47bc-b726-e1433669ea99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756369019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.756369019
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3968632299
Short name T427
Test name
Test status
Simulation time 24167528564 ps
CPU time 19.84 seconds
Started Apr 18 12:21:58 PM PDT 24
Finished Apr 18 12:22:19 PM PDT 24
Peak memory 190640 kb
Host smart-2db5f742-bfe1-4509-ada9-d82f8ea4053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968632299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3968632299
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3262121514
Short name T431
Test name
Test status
Simulation time 341385135198 ps
CPU time 273.36 seconds
Started Apr 18 12:21:05 PM PDT 24
Finished Apr 18 12:25:38 PM PDT 24
Peak memory 190628 kb
Host smart-7ecc63ed-7dc5-4530-809d-9a4bca299054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262121514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3262121514
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.725077939
Short name T46
Test name
Test status
Simulation time 141016449892 ps
CPU time 183.87 seconds
Started Apr 18 12:22:24 PM PDT 24
Finished Apr 18 12:25:28 PM PDT 24
Peak memory 205260 kb
Host smart-a448958c-0611-4437-9867-80cbd9b8ebce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725077939 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.725077939
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.rv_timer_random.1631556386
Short name T151
Test name
Test status
Simulation time 1103882625294 ps
CPU time 291.6 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:28:38 PM PDT 24
Peak memory 190616 kb
Host smart-38087e18-a247-46e9-93e6-f7fca2875595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631556386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1631556386
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.4070252436
Short name T443
Test name
Test status
Simulation time 14364354883 ps
CPU time 25.27 seconds
Started Apr 18 12:23:45 PM PDT 24
Finished Apr 18 12:24:11 PM PDT 24
Peak memory 182312 kb
Host smart-cbecbc10-ea80-45e4-848d-1eac93bf1146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070252436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.4070252436
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1515381663
Short name T195
Test name
Test status
Simulation time 540282466271 ps
CPU time 460.37 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:31:32 PM PDT 24
Peak memory 190592 kb
Host smart-287bdfe1-451b-454c-8fbd-efb4d86960c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515381663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1515381663
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2749527545
Short name T206
Test name
Test status
Simulation time 169437554094 ps
CPU time 307.49 seconds
Started Apr 18 12:23:46 PM PDT 24
Finished Apr 18 12:28:55 PM PDT 24
Peak memory 190544 kb
Host smart-e4ee9dfe-303f-4203-a23c-a22825cd21bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749527545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2749527545
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.4041331025
Short name T203
Test name
Test status
Simulation time 108393983786 ps
CPU time 92.1 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:25:14 PM PDT 24
Peak memory 193032 kb
Host smart-7d22c9b6-0740-4eac-9964-b98cd5141a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041331025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4041331025
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.4023998662
Short name T123
Test name
Test status
Simulation time 50497970141 ps
CPU time 84.4 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:25:18 PM PDT 24
Peak memory 182396 kb
Host smart-50f1bdc0-e861-4b6b-8786-ee6b6ed97f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023998662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.4023998662
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2185881313
Short name T430
Test name
Test status
Simulation time 2580615707 ps
CPU time 2.95 seconds
Started Apr 18 12:21:12 PM PDT 24
Finished Apr 18 12:21:15 PM PDT 24
Peak memory 182872 kb
Host smart-ee35430d-9ceb-41c6-aad4-5b999b7308e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185881313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2185881313
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1028400611
Short name T364
Test name
Test status
Simulation time 127865164978 ps
CPU time 81.21 seconds
Started Apr 18 12:21:07 PM PDT 24
Finished Apr 18 12:22:29 PM PDT 24
Peak memory 182404 kb
Host smart-1e1cf495-fd1f-40ff-bd76-2ec82cd6c4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028400611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1028400611
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2720741156
Short name T85
Test name
Test status
Simulation time 156457128899 ps
CPU time 124.34 seconds
Started Apr 18 12:21:04 PM PDT 24
Finished Apr 18 12:23:09 PM PDT 24
Peak memory 193044 kb
Host smart-98dc28d3-d2ba-41e8-a8fd-e75e90778cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720741156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2720741156
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1061258887
Short name T220
Test name
Test status
Simulation time 57844372504 ps
CPU time 60.28 seconds
Started Apr 18 12:21:14 PM PDT 24
Finished Apr 18 12:22:15 PM PDT 24
Peak memory 190732 kb
Host smart-c98660a3-f35d-451d-a36c-f932861aec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061258887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1061258887
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3379825059
Short name T329
Test name
Test status
Simulation time 398573272981 ps
CPU time 330.45 seconds
Started Apr 18 12:23:35 PM PDT 24
Finished Apr 18 12:29:07 PM PDT 24
Peak memory 189844 kb
Host smart-e7ae87af-cbe0-4142-96d8-4b8118391fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379825059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3379825059
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/192.rv_timer_random.2197925946
Short name T424
Test name
Test status
Simulation time 73422653111 ps
CPU time 153.37 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:26:19 PM PDT 24
Peak memory 190500 kb
Host smart-ad18a637-b9ec-49f4-b571-c829b7f3edd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197925946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2197925946
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2786220989
Short name T188
Test name
Test status
Simulation time 246487814996 ps
CPU time 556.88 seconds
Started Apr 18 12:23:49 PM PDT 24
Finished Apr 18 12:33:07 PM PDT 24
Peak memory 190616 kb
Host smart-aec4dabe-08ec-4f13-beba-5cb944869aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786220989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2786220989
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2664031086
Short name T310
Test name
Test status
Simulation time 52572960988 ps
CPU time 63.82 seconds
Started Apr 18 12:23:47 PM PDT 24
Finished Apr 18 12:24:52 PM PDT 24
Peak memory 190624 kb
Host smart-2a395f5f-1365-4c90-a559-a689e1f22293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664031086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2664031086
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.94812633
Short name T292
Test name
Test status
Simulation time 458253640725 ps
CPU time 1876.12 seconds
Started Apr 18 12:23:46 PM PDT 24
Finished Apr 18 12:55:03 PM PDT 24
Peak memory 190584 kb
Host smart-c93990cd-8e22-41f4-a2ef-13bf75b9d274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94812633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.94812633
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4188050939
Short name T121
Test name
Test status
Simulation time 94451401476 ps
CPU time 363.5 seconds
Started Apr 18 12:23:48 PM PDT 24
Finished Apr 18 12:29:52 PM PDT 24
Peak memory 190640 kb
Host smart-e369a43a-e43c-4903-8b41-ac7426d0292b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188050939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4188050939
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2509123499
Short name T396
Test name
Test status
Simulation time 38087636251 ps
CPU time 10.7 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:24:08 PM PDT 24
Peak memory 181716 kb
Host smart-d4b8d9d9-69b2-4067-a7fa-b0fabe6fa0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509123499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2509123499
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1459303133
Short name T302
Test name
Test status
Simulation time 114975912142 ps
CPU time 47.27 seconds
Started Apr 18 12:18:41 PM PDT 24
Finished Apr 18 12:19:30 PM PDT 24
Peak memory 181932 kb
Host smart-1da68e5f-94dc-46bb-bd00-daeb9a90321e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459303133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1459303133
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.967490322
Short name T9
Test name
Test status
Simulation time 71192176 ps
CPU time 0.81 seconds
Started Apr 18 12:18:41 PM PDT 24
Finished Apr 18 12:18:44 PM PDT 24
Peak memory 213780 kb
Host smart-4e22002a-8f91-4849-a044-bea2e80f21b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967490322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.967490322
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2860383026
Short name T243
Test name
Test status
Simulation time 109209335410 ps
CPU time 48.1 seconds
Started Apr 18 12:23:55 PM PDT 24
Finished Apr 18 12:24:44 PM PDT 24
Peak memory 194304 kb
Host smart-adabac3a-c015-4af3-bb0f-f57953ab4cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860383026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2860383026
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4087955346
Short name T117
Test name
Test status
Simulation time 260779590542 ps
CPU time 139.8 seconds
Started Apr 18 12:24:37 PM PDT 24
Finished Apr 18 12:26:59 PM PDT 24
Peak memory 188232 kb
Host smart-248cc655-6763-42fb-bc8e-9b0a35ccdf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087955346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4087955346
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.4058910960
Short name T156
Test name
Test status
Simulation time 591597720204 ps
CPU time 333.06 seconds
Started Apr 18 12:21:17 PM PDT 24
Finished Apr 18 12:26:50 PM PDT 24
Peak memory 182544 kb
Host smart-4733bfa8-5be9-432f-a969-9b819d756578
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058910960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.4058910960
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.820275685
Short name T361
Test name
Test status
Simulation time 54231077030 ps
CPU time 37.04 seconds
Started Apr 18 12:23:59 PM PDT 24
Finished Apr 18 12:24:37 PM PDT 24
Peak memory 181976 kb
Host smart-cb011189-f1e3-4c7e-802a-866c62f5ec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820275685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.820275685
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2405253065
Short name T80
Test name
Test status
Simulation time 343673903159 ps
CPU time 85.91 seconds
Started Apr 18 12:23:58 PM PDT 24
Finished Apr 18 12:25:25 PM PDT 24
Peak memory 190940 kb
Host smart-f400fb12-1ebc-477b-ba9f-2024c53ef8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405253065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2405253065
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2018156834
Short name T267
Test name
Test status
Simulation time 51588996338 ps
CPU time 91.01 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:25:25 PM PDT 24
Peak memory 182204 kb
Host smart-40466c2e-5586-4956-9908-80a7c3f7cbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018156834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2018156834
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.920818576
Short name T245
Test name
Test status
Simulation time 460369686338 ps
CPU time 795.94 seconds
Started Apr 18 12:23:08 PM PDT 24
Finished Apr 18 12:36:24 PM PDT 24
Peak memory 190120 kb
Host smart-18d47cca-c0ca-4c9e-b4ec-a1cd71342345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920818576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
920818576
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3250846373
Short name T219
Test name
Test status
Simulation time 813121279556 ps
CPU time 962.83 seconds
Started Apr 18 12:24:37 PM PDT 24
Finished Apr 18 12:40:42 PM PDT 24
Peak memory 180168 kb
Host smart-746cf661-2a4d-49a6-afc7-747889b43c77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250846373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3250846373
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3169744083
Short name T446
Test name
Test status
Simulation time 180803386685 ps
CPU time 298.54 seconds
Started Apr 18 12:23:58 PM PDT 24
Finished Apr 18 12:28:58 PM PDT 24
Peak memory 179712 kb
Host smart-6ab82cb4-283b-4a19-9e3c-597ba62c45da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169744083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3169744083
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2657943627
Short name T147
Test name
Test status
Simulation time 225819436361 ps
CPU time 460.83 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:31:35 PM PDT 24
Peak memory 192468 kb
Host smart-8f9c88eb-4fd1-41ef-9a42-81d2d4b32d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657943627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2657943627
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1146161211
Short name T375
Test name
Test status
Simulation time 266498706 ps
CPU time 0.86 seconds
Started Apr 18 12:23:54 PM PDT 24
Finished Apr 18 12:23:56 PM PDT 24
Peak memory 181384 kb
Host smart-7b6ae284-cfc8-4095-9e07-bed275d5651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146161211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1146161211
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.1254609273
Short name T448
Test name
Test status
Simulation time 21531486958 ps
CPU time 118.06 seconds
Started Apr 18 12:22:41 PM PDT 24
Finished Apr 18 12:24:40 PM PDT 24
Peak memory 196296 kb
Host smart-40dd2ff5-a9d7-4b43-ae68-90cac8c30973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254609273 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.1254609273
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.961306859
Short name T410
Test name
Test status
Simulation time 106066654472 ps
CPU time 55.57 seconds
Started Apr 18 12:22:51 PM PDT 24
Finished Apr 18 12:23:48 PM PDT 24
Peak memory 182308 kb
Host smart-eb100928-697b-4f4d-8c93-7635bf74bf71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961306859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.961306859
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3258110721
Short name T388
Test name
Test status
Simulation time 398897246663 ps
CPU time 165.19 seconds
Started Apr 18 12:23:58 PM PDT 24
Finished Apr 18 12:26:45 PM PDT 24
Peak memory 179992 kb
Host smart-4fb71d5f-854c-44d6-8c72-2095509a9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258110721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3258110721
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1572710424
Short name T340
Test name
Test status
Simulation time 433227426525 ps
CPU time 1672.55 seconds
Started Apr 18 12:22:20 PM PDT 24
Finished Apr 18 12:50:13 PM PDT 24
Peak memory 191072 kb
Host smart-5ddaeafb-21c1-47dc-bb48-c1bdd3f94306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572710424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1572710424
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3231808782
Short name T11
Test name
Test status
Simulation time 195488088195 ps
CPU time 76.78 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:24:08 PM PDT 24
Peak memory 190408 kb
Host smart-0f1c58f4-7e63-464d-a092-b5363910b598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231808782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3231808782
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2120111393
Short name T333
Test name
Test status
Simulation time 2217715847722 ps
CPU time 1164.35 seconds
Started Apr 18 12:23:58 PM PDT 24
Finished Apr 18 12:43:24 PM PDT 24
Peak memory 179728 kb
Host smart-f6122443-9056-4d1f-809d-3fa594fd2db8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120111393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2120111393
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3965808122
Short name T390
Test name
Test status
Simulation time 97184439469 ps
CPU time 93.05 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:24:24 PM PDT 24
Peak memory 182220 kb
Host smart-83152c0b-e53f-4791-9510-a9eb46a31bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965808122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3965808122
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3799071027
Short name T420
Test name
Test status
Simulation time 7566113284 ps
CPU time 6.81 seconds
Started Apr 18 12:21:17 PM PDT 24
Finished Apr 18 12:21:24 PM PDT 24
Peak memory 182412 kb
Host smart-6280ebe2-c4dc-49c6-a57d-68ce6933a139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799071027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3799071027
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.3281586083
Short name T32
Test name
Test status
Simulation time 115049285011 ps
CPU time 129.8 seconds
Started Apr 18 12:22:38 PM PDT 24
Finished Apr 18 12:24:49 PM PDT 24
Peak memory 195428 kb
Host smart-1f8e1417-f7fd-48c6-871f-14e0a43c5634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281586083 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.3281586083
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2188127901
Short name T260
Test name
Test status
Simulation time 3815053775102 ps
CPU time 840.23 seconds
Started Apr 18 12:23:06 PM PDT 24
Finished Apr 18 12:37:07 PM PDT 24
Peak memory 182364 kb
Host smart-d4f325f6-82a5-4fbf-8de2-b6de987ec58b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188127901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2188127901
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3177734822
Short name T385
Test name
Test status
Simulation time 227333613071 ps
CPU time 157.32 seconds
Started Apr 18 12:22:51 PM PDT 24
Finished Apr 18 12:25:31 PM PDT 24
Peak memory 180684 kb
Host smart-1a623b1f-1f4a-4c24-b444-6cba549595e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177734822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3177734822
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1076803547
Short name T391
Test name
Test status
Simulation time 62795775 ps
CPU time 0.66 seconds
Started Apr 18 12:22:51 PM PDT 24
Finished Apr 18 12:22:54 PM PDT 24
Peak memory 180352 kb
Host smart-87cc64a1-3d2a-4204-a0df-802b484af2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076803547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1076803547
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2892408238
Short name T330
Test name
Test status
Simulation time 587556331552 ps
CPU time 454.28 seconds
Started Apr 18 12:23:16 PM PDT 24
Finished Apr 18 12:30:51 PM PDT 24
Peak memory 190596 kb
Host smart-0c1bda94-fad7-4351-8035-34e431fe3135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892408238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2892408238
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.194906337
Short name T212
Test name
Test status
Simulation time 829730867175 ps
CPU time 480.15 seconds
Started Apr 18 12:23:04 PM PDT 24
Finished Apr 18 12:31:05 PM PDT 24
Peak memory 182152 kb
Host smart-1e66d84c-8553-487e-9818-6f56e95d5973
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194906337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.194906337
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2254067258
Short name T378
Test name
Test status
Simulation time 582888593521 ps
CPU time 246.82 seconds
Started Apr 18 12:23:03 PM PDT 24
Finished Apr 18 12:27:11 PM PDT 24
Peak memory 180204 kb
Host smart-a204526c-0fa4-47bd-aab4-17b628317804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254067258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2254067258
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2817225875
Short name T238
Test name
Test status
Simulation time 39905910281 ps
CPU time 71.44 seconds
Started Apr 18 12:23:03 PM PDT 24
Finished Apr 18 12:24:16 PM PDT 24
Peak memory 180300 kb
Host smart-ea560e11-f4dd-4e36-9630-d18362cd8ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817225875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2817225875
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2593439378
Short name T35
Test name
Test status
Simulation time 52954727036 ps
CPU time 417.21 seconds
Started Apr 18 12:24:38 PM PDT 24
Finished Apr 18 12:31:36 PM PDT 24
Peak memory 196232 kb
Host smart-cde04641-159c-4ab4-a9af-9beeece697d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593439378 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2593439378
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1312632572
Short name T358
Test name
Test status
Simulation time 139116320253 ps
CPU time 56.86 seconds
Started Apr 18 12:22:52 PM PDT 24
Finished Apr 18 12:23:50 PM PDT 24
Peak memory 181936 kb
Host smart-4f0d10a4-049d-4f10-a47b-96ea399c1a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312632572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1312632572
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.229499287
Short name T161
Test name
Test status
Simulation time 429744429944 ps
CPU time 339.26 seconds
Started Apr 18 12:23:03 PM PDT 24
Finished Apr 18 12:28:44 PM PDT 24
Peak memory 188760 kb
Host smart-2d81b3dd-54f1-49bd-b059-6e230f65479f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229499287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.229499287
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2293251411
Short name T318
Test name
Test status
Simulation time 174460959550 ps
CPU time 408.18 seconds
Started Apr 18 12:23:06 PM PDT 24
Finished Apr 18 12:29:55 PM PDT 24
Peak memory 192564 kb
Host smart-99458624-0336-4538-8c80-36e849203fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293251411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2293251411
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2836842121
Short name T415
Test name
Test status
Simulation time 302931932820 ps
CPU time 476.01 seconds
Started Apr 18 12:23:00 PM PDT 24
Finished Apr 18 12:30:58 PM PDT 24
Peak memory 189532 kb
Host smart-aa9d66bb-a411-4a5d-8701-cd368c43540f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836842121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2836842121
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2428055640
Short name T37
Test name
Test status
Simulation time 81869632006 ps
CPU time 531.67 seconds
Started Apr 18 12:21:29 PM PDT 24
Finished Apr 18 12:30:22 PM PDT 24
Peak memory 209208 kb
Host smart-293eaa77-36bb-47ab-a013-ee5d3f285141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428055640 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2428055640
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2526634748
Short name T231
Test name
Test status
Simulation time 125541126350 ps
CPU time 106.56 seconds
Started Apr 18 12:23:09 PM PDT 24
Finished Apr 18 12:24:57 PM PDT 24
Peak memory 182132 kb
Host smart-05cc7c05-d76b-4d7c-8f90-3d384a92dbcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526634748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2526634748
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2343062957
Short name T404
Test name
Test status
Simulation time 19805905950 ps
CPU time 27.71 seconds
Started Apr 18 12:23:06 PM PDT 24
Finished Apr 18 12:23:34 PM PDT 24
Peak memory 182324 kb
Host smart-ac526cbd-3861-4d65-9a87-853ec7aa6d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343062957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2343062957
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3590683200
Short name T272
Test name
Test status
Simulation time 39291615659 ps
CPU time 156.13 seconds
Started Apr 18 12:23:06 PM PDT 24
Finished Apr 18 12:25:43 PM PDT 24
Peak memory 182324 kb
Host smart-c9ac96de-b3dc-4adb-b87d-37ee50969f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590683200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3590683200
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.873032016
Short name T384
Test name
Test status
Simulation time 561688208 ps
CPU time 0.93 seconds
Started Apr 18 12:23:06 PM PDT 24
Finished Apr 18 12:23:08 PM PDT 24
Peak memory 182072 kb
Host smart-4bf061b2-ff8e-4d03-81e0-bf39c4e3bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873032016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.873032016
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2082918866
Short name T257
Test name
Test status
Simulation time 1991512802218 ps
CPU time 1134.96 seconds
Started Apr 18 12:22:30 PM PDT 24
Finished Apr 18 12:41:26 PM PDT 24
Peak memory 182876 kb
Host smart-9f971606-c2cb-4cab-a645-b648b620032a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082918866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2082918866
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1416912541
Short name T444
Test name
Test status
Simulation time 63935495652 ps
CPU time 25.65 seconds
Started Apr 18 12:21:39 PM PDT 24
Finished Apr 18 12:22:06 PM PDT 24
Peak memory 182600 kb
Host smart-511a730f-73c2-45b1-bcb8-e817d2dfc461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416912541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1416912541
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.4247649655
Short name T350
Test name
Test status
Simulation time 8887869888 ps
CPU time 15.06 seconds
Started Apr 18 12:22:31 PM PDT 24
Finished Apr 18 12:22:47 PM PDT 24
Peak memory 182596 kb
Host smart-80df458f-27bb-4ca9-ad5a-5c0907088d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247649655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.4247649655
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.808398562
Short name T66
Test name
Test status
Simulation time 21382776491 ps
CPU time 122.47 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:26:00 PM PDT 24
Peak memory 196668 kb
Host smart-70b83c47-cef1-4c06-9cc3-deab60f6b5f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808398562 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.808398562
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3138857006
Short name T342
Test name
Test status
Simulation time 851187411887 ps
CPU time 466.2 seconds
Started Apr 18 12:19:42 PM PDT 24
Finished Apr 18 12:27:29 PM PDT 24
Peak memory 182540 kb
Host smart-ed1c94aa-768d-4105-8a19-8a05398da774
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138857006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3138857006
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1770627979
Short name T423
Test name
Test status
Simulation time 589306158547 ps
CPU time 244.22 seconds
Started Apr 18 12:24:30 PM PDT 24
Finished Apr 18 12:28:35 PM PDT 24
Peak memory 180576 kb
Host smart-142f9ad8-fcd1-43e1-bc08-6e32bba0f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770627979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1770627979
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2621572833
Short name T194
Test name
Test status
Simulation time 238791060311 ps
CPU time 135.33 seconds
Started Apr 18 12:22:54 PM PDT 24
Finished Apr 18 12:25:11 PM PDT 24
Peak memory 190680 kb
Host smart-beb32c9e-4e48-43c8-859a-df2e9a9f1305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621572833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2621572833
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.895188404
Short name T237
Test name
Test status
Simulation time 209249559148 ps
CPU time 1565.94 seconds
Started Apr 18 12:20:16 PM PDT 24
Finished Apr 18 12:46:23 PM PDT 24
Peak memory 182588 kb
Host smart-bb236e91-fbde-4177-9056-957024d7bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895188404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.895188404
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.127063183
Short name T17
Test name
Test status
Simulation time 44789774 ps
CPU time 0.79 seconds
Started Apr 18 12:19:43 PM PDT 24
Finished Apr 18 12:19:44 PM PDT 24
Peak memory 213000 kb
Host smart-53b89bd2-511c-4f21-b4ab-069cc8e1497d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127063183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.127063183
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2089741368
Short name T56
Test name
Test status
Simulation time 613076662708 ps
CPU time 842.6 seconds
Started Apr 18 12:20:27 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 190580 kb
Host smart-b0b1b1dc-6834-4aff-b437-0111c41187f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089741368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2089741368
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2744635684
Short name T12
Test name
Test status
Simulation time 29002582755 ps
CPU time 222.2 seconds
Started Apr 18 12:23:54 PM PDT 24
Finished Apr 18 12:27:37 PM PDT 24
Peak memory 205292 kb
Host smart-7bd17e35-c359-499b-a672-9ca9319f246d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744635684 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2744635684
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2558187023
Short name T107
Test name
Test status
Simulation time 113135929584 ps
CPU time 202.21 seconds
Started Apr 18 12:23:24 PM PDT 24
Finished Apr 18 12:26:47 PM PDT 24
Peak memory 182176 kb
Host smart-c1c17837-cfcf-429c-b2e2-50fa2e907a9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558187023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2558187023
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.536968372
Short name T359
Test name
Test status
Simulation time 80386847604 ps
CPU time 117.34 seconds
Started Apr 18 12:24:30 PM PDT 24
Finished Apr 18 12:26:28 PM PDT 24
Peak memory 182212 kb
Host smart-50aa7ca2-c849-42bc-85c4-1e50b04f78f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536968372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.536968372
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3695549104
Short name T171
Test name
Test status
Simulation time 78948011121 ps
CPU time 296.72 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:28:55 PM PDT 24
Peak memory 190408 kb
Host smart-0825673b-25df-4eaa-8971-437774abb0a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695549104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3695549104
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2743748779
Short name T337
Test name
Test status
Simulation time 50286328764 ps
CPU time 20.82 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:24:19 PM PDT 24
Peak memory 182308 kb
Host smart-33258cc9-41ab-4327-b450-9c692162d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743748779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2743748779
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3520401992
Short name T25
Test name
Test status
Simulation time 1844614682051 ps
CPU time 861.39 seconds
Started Apr 18 12:21:37 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 190616 kb
Host smart-f1842cb3-d39c-47c8-9195-2cad325da19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520401992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3520401992
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3363099232
Short name T414
Test name
Test status
Simulation time 24287055110 ps
CPU time 13.81 seconds
Started Apr 18 12:24:37 PM PDT 24
Finished Apr 18 12:24:53 PM PDT 24
Peak memory 179928 kb
Host smart-fa7fd152-8ae2-4a79-8f3f-5b202e659b49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363099232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3363099232
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.399613118
Short name T407
Test name
Test status
Simulation time 76867592094 ps
CPU time 121.23 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:25:59 PM PDT 24
Peak memory 181972 kb
Host smart-38ad0174-e170-42a2-9333-fef50dfff047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399613118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.399613118
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.740403609
Short name T397
Test name
Test status
Simulation time 33127409519 ps
CPU time 20.56 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:24:01 PM PDT 24
Peak memory 180068 kb
Host smart-60b00665-646b-4d6c-8823-9e03f3024984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740403609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.740403609
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3429743436
Short name T110
Test name
Test status
Simulation time 901104488548 ps
CPU time 870.36 seconds
Started Apr 18 12:23:38 PM PDT 24
Finished Apr 18 12:38:11 PM PDT 24
Peak memory 180196 kb
Host smart-c8f38740-d3d0-416a-990a-6049c0616ed2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429743436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3429743436
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1119447806
Short name T352
Test name
Test status
Simulation time 553640117379 ps
CPU time 205.5 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:27:17 PM PDT 24
Peak memory 182012 kb
Host smart-af10ebae-4d69-4700-b343-86df842008e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119447806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1119447806
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.277800841
Short name T312
Test name
Test status
Simulation time 50503988846 ps
CPU time 90.77 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:25:22 PM PDT 24
Peak memory 191880 kb
Host smart-ba1dc71a-7189-41da-9252-9a4647b85b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277800841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.277800841
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1276050323
Short name T393
Test name
Test status
Simulation time 156257742180 ps
CPU time 69.36 seconds
Started Apr 18 12:23:40 PM PDT 24
Finished Apr 18 12:24:50 PM PDT 24
Peak memory 190360 kb
Host smart-b0b5575f-3074-4fe9-ac30-0435edab3cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276050323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1276050323
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.11439626
Short name T253
Test name
Test status
Simulation time 958364887278 ps
CPU time 740.88 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:36:03 PM PDT 24
Peak memory 181676 kb
Host smart-5b32fb87-436a-4b80-b7d0-368b78da22e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11439626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.rv_timer_cfg_update_on_fly.11439626
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3511625754
Short name T83
Test name
Test status
Simulation time 75057034805 ps
CPU time 116.84 seconds
Started Apr 18 12:21:58 PM PDT 24
Finished Apr 18 12:23:56 PM PDT 24
Peak memory 182404 kb
Host smart-dc261a7e-b7f1-4b47-897a-1d03dc066772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511625754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3511625754
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2614504782
Short name T102
Test name
Test status
Simulation time 95891010219 ps
CPU time 180.61 seconds
Started Apr 18 12:23:55 PM PDT 24
Finished Apr 18 12:26:57 PM PDT 24
Peak memory 190384 kb
Host smart-1756dddf-71da-4350-a8ed-838159729680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614504782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2614504782
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1436499120
Short name T45
Test name
Test status
Simulation time 49156584585 ps
CPU time 1385.97 seconds
Started Apr 18 12:24:28 PM PDT 24
Finished Apr 18 12:47:35 PM PDT 24
Peak memory 190368 kb
Host smart-29bf5e47-9bee-493f-bf77-f92abe0af14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436499120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1436499120
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2100872626
Short name T118
Test name
Test status
Simulation time 1052317548402 ps
CPU time 615.23 seconds
Started Apr 18 12:23:55 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 180096 kb
Host smart-920c9630-0dab-4997-aa89-83ef4b5c26cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100872626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2100872626
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1928260740
Short name T377
Test name
Test status
Simulation time 272198041647 ps
CPU time 119.19 seconds
Started Apr 18 12:22:36 PM PDT 24
Finished Apr 18 12:24:36 PM PDT 24
Peak memory 182600 kb
Host smart-4d81ce3d-d09f-4db9-8738-fa7c38bddd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928260740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1928260740
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.248736944
Short name T181
Test name
Test status
Simulation time 234825715110 ps
CPU time 837.46 seconds
Started Apr 18 12:21:58 PM PDT 24
Finished Apr 18 12:35:56 PM PDT 24
Peak memory 192376 kb
Host smart-ae560c3b-efe0-4312-abd8-7f0cad8530df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248736944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.248736944
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.299153977
Short name T315
Test name
Test status
Simulation time 34378035860 ps
CPU time 33.57 seconds
Started Apr 18 12:23:25 PM PDT 24
Finished Apr 18 12:23:59 PM PDT 24
Peak memory 190348 kb
Host smart-5c435285-fac8-4374-b45a-8e8a9c5f1c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299153977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.299153977
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3274149800
Short name T441
Test name
Test status
Simulation time 556089565109 ps
CPU time 877.56 seconds
Started Apr 18 12:23:14 PM PDT 24
Finished Apr 18 12:37:53 PM PDT 24
Peak memory 189868 kb
Host smart-e32abc1d-086c-413e-9d05-5ae2169b6fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274149800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3274149800
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1718361829
Short name T303
Test name
Test status
Simulation time 335966877218 ps
CPU time 619.46 seconds
Started Apr 18 12:23:50 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 182436 kb
Host smart-53bf5f6a-de85-4483-a9f9-15a36d0a3c2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718361829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1718361829
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.677511723
Short name T386
Test name
Test status
Simulation time 230419687522 ps
CPU time 377.12 seconds
Started Apr 18 12:22:04 PM PDT 24
Finished Apr 18 12:28:21 PM PDT 24
Peak memory 182584 kb
Host smart-47b3832e-7526-46a7-bc3e-c14efd297694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677511723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.677511723
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2626001789
Short name T334
Test name
Test status
Simulation time 50529633963 ps
CPU time 76.35 seconds
Started Apr 18 12:22:14 PM PDT 24
Finished Apr 18 12:23:31 PM PDT 24
Peak memory 182248 kb
Host smart-951c374b-a0d0-4a0d-9107-2e6f5a966ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626001789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2626001789
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1423367018
Short name T244
Test name
Test status
Simulation time 2177634518492 ps
CPU time 731.08 seconds
Started Apr 18 12:23:21 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 181652 kb
Host smart-0c9bfc07-af60-4fd2-bdd7-832665fa2103
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423367018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1423367018
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.51586582
Short name T353
Test name
Test status
Simulation time 344324883172 ps
CPU time 143.69 seconds
Started Apr 18 12:22:14 PM PDT 24
Finished Apr 18 12:24:38 PM PDT 24
Peak memory 182440 kb
Host smart-4f9a98cb-2b9a-4838-9505-dc20d0ac6dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51586582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.51586582
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3665312997
Short name T216
Test name
Test status
Simulation time 112504618833 ps
CPU time 202.48 seconds
Started Apr 18 12:23:30 PM PDT 24
Finished Apr 18 12:26:53 PM PDT 24
Peak memory 190384 kb
Host smart-6f9bf836-5ab1-43a1-8012-9828716618f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665312997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3665312997
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1274586788
Short name T363
Test name
Test status
Simulation time 1990878858 ps
CPU time 3.86 seconds
Started Apr 18 12:23:31 PM PDT 24
Finished Apr 18 12:23:36 PM PDT 24
Peak memory 190244 kb
Host smart-411715f1-0e8d-4223-8069-a407836f7e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274586788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1274586788
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1822006817
Short name T40
Test name
Test status
Simulation time 2392671271187 ps
CPU time 705.35 seconds
Started Apr 18 12:23:55 PM PDT 24
Finished Apr 18 12:35:41 PM PDT 24
Peak memory 180032 kb
Host smart-79391986-e038-4fd9-9e9b-3879cfd8524c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822006817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1822006817
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1390658155
Short name T422
Test name
Test status
Simulation time 157822180379 ps
CPU time 208.7 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:27:22 PM PDT 24
Peak memory 181908 kb
Host smart-d691aa96-71f5-46a0-a64f-d2cd7f196012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390658155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1390658155
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3156884189
Short name T348
Test name
Test status
Simulation time 66334080 ps
CPU time 0.68 seconds
Started Apr 18 12:23:44 PM PDT 24
Finished Apr 18 12:23:46 PM PDT 24
Peak memory 181724 kb
Host smart-1fbf7935-ac8d-479c-a369-a311971939c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156884189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3156884189
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1542616749
Short name T297
Test name
Test status
Simulation time 623268495394 ps
CPU time 318.13 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:29:16 PM PDT 24
Peak memory 182032 kb
Host smart-e6e3605c-8338-4123-af49-78c28c090631
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542616749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1542616749
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2713734802
Short name T354
Test name
Test status
Simulation time 78774884538 ps
CPU time 109.27 seconds
Started Apr 18 12:22:18 PM PDT 24
Finished Apr 18 12:24:07 PM PDT 24
Peak memory 182600 kb
Host smart-e8b607a4-94b8-4558-ae89-0b25cd7bef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713734802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2713734802
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2675002267
Short name T293
Test name
Test status
Simulation time 25357215130 ps
CPU time 48.13 seconds
Started Apr 18 12:22:29 PM PDT 24
Finished Apr 18 12:23:18 PM PDT 24
Peak memory 190584 kb
Host smart-86975a85-2bc1-46ae-96ff-ba6c1fd8910b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675002267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2675002267
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.397710693
Short name T228
Test name
Test status
Simulation time 13100693039 ps
CPU time 21.93 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:24:20 PM PDT 24
Peak memory 193528 kb
Host smart-63556cec-bf64-4c17-b466-41c9a7a72ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397710693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.397710693
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3454473844
Short name T300
Test name
Test status
Simulation time 382847559927 ps
CPU time 366.2 seconds
Started Apr 18 12:22:29 PM PDT 24
Finished Apr 18 12:28:36 PM PDT 24
Peak memory 182380 kb
Host smart-37c14e92-9e1a-4a4f-8982-4ec73f133fd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454473844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3454473844
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1241137689
Short name T400
Test name
Test status
Simulation time 922364339219 ps
CPU time 344.6 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:29:42 PM PDT 24
Peak memory 182000 kb
Host smart-14415fdc-c2de-4265-9138-5392975e1507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241137689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1241137689
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2836486125
Short name T172
Test name
Test status
Simulation time 244261333444 ps
CPU time 1352.23 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 188808 kb
Host smart-1d59bc19-c80e-425b-83d3-72034c95b7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836486125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2836486125
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1555606663
Short name T274
Test name
Test status
Simulation time 159514529420 ps
CPU time 132.74 seconds
Started Apr 18 12:23:55 PM PDT 24
Finished Apr 18 12:26:09 PM PDT 24
Peak memory 190876 kb
Host smart-27a0124b-bcd7-485e-965e-112a3e818118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555606663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1555606663
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3048958289
Short name T31
Test name
Test status
Simulation time 58280626779 ps
CPU time 273.38 seconds
Started Apr 18 12:22:23 PM PDT 24
Finished Apr 18 12:26:57 PM PDT 24
Peak memory 205240 kb
Host smart-28c9564c-a45d-4fd6-b90e-59fd793b4ff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048958289 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3048958289
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2493845828
Short name T196
Test name
Test status
Simulation time 2712193099249 ps
CPU time 1019.68 seconds
Started Apr 18 12:20:21 PM PDT 24
Finished Apr 18 12:37:22 PM PDT 24
Peak memory 182556 kb
Host smart-240f6ce0-323e-4db5-be67-42e39ad5ba86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493845828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2493845828
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1094538199
Short name T366
Test name
Test status
Simulation time 458806364600 ps
CPU time 195.44 seconds
Started Apr 18 12:22:49 PM PDT 24
Finished Apr 18 12:26:06 PM PDT 24
Peak memory 181372 kb
Host smart-cc00443c-f300-4d69-9914-2cbc3d6cbf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094538199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1094538199
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1721447324
Short name T438
Test name
Test status
Simulation time 43783855578 ps
CPU time 73.1 seconds
Started Apr 18 12:22:43 PM PDT 24
Finished Apr 18 12:23:56 PM PDT 24
Peak memory 182100 kb
Host smart-d8e732a5-145f-43be-a0f1-a4878c9781ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721447324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1721447324
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2280682242
Short name T18
Test name
Test status
Simulation time 58899765 ps
CPU time 0.81 seconds
Started Apr 18 12:23:31 PM PDT 24
Finished Apr 18 12:23:33 PM PDT 24
Peak memory 211380 kb
Host smart-5becff72-85fd-4092-a907-342e7f85e98c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280682242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2280682242
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1600834059
Short name T13
Test name
Test status
Simulation time 47010326454 ps
CPU time 229.37 seconds
Started Apr 18 12:23:49 PM PDT 24
Finished Apr 18 12:27:39 PM PDT 24
Peak memory 197072 kb
Host smart-452b8a39-a8c2-4f52-b232-e56959b438ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600834059 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1600834059
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1313411396
Short name T450
Test name
Test status
Simulation time 22072993866 ps
CPU time 19.92 seconds
Started Apr 18 12:23:43 PM PDT 24
Finished Apr 18 12:24:04 PM PDT 24
Peak memory 180620 kb
Host smart-5830c051-5d1f-4cb0-bc04-78e3156e0c70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313411396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1313411396
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2263748924
Short name T349
Test name
Test status
Simulation time 108155257099 ps
CPU time 147.32 seconds
Started Apr 18 12:22:24 PM PDT 24
Finished Apr 18 12:24:52 PM PDT 24
Peak memory 182380 kb
Host smart-d0f810b4-6963-446c-ac9e-94bd84de098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263748924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2263748924
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3753311405
Short name T445
Test name
Test status
Simulation time 5780028719 ps
CPU time 2.84 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:24:00 PM PDT 24
Peak memory 181824 kb
Host smart-1aff3ebb-6b1c-4786-9316-30d4c0e8aa3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753311405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3753311405
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.588040067
Short name T365
Test name
Test status
Simulation time 1144810566 ps
CPU time 1.66 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:23:59 PM PDT 24
Peak memory 190336 kb
Host smart-b56c8196-9f75-40f1-941c-17160c8afb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588040067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.588040067
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.887357767
Short name T417
Test name
Test status
Simulation time 143237565493 ps
CPU time 35.51 seconds
Started Apr 18 12:22:25 PM PDT 24
Finished Apr 18 12:23:01 PM PDT 24
Peak memory 182580 kb
Host smart-7bb1bbc7-de64-4c27-93e5-5266a8ab3970
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887357767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.887357767
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.132118327
Short name T405
Test name
Test status
Simulation time 40291083739 ps
CPU time 62.19 seconds
Started Apr 18 12:22:28 PM PDT 24
Finished Apr 18 12:23:32 PM PDT 24
Peak memory 182884 kb
Host smart-f4bcbf8c-f7be-400e-8e22-28c1f01e9f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132118327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.132118327
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3448589683
Short name T316
Test name
Test status
Simulation time 139121612017 ps
CPU time 228.5 seconds
Started Apr 18 12:22:35 PM PDT 24
Finished Apr 18 12:26:24 PM PDT 24
Peak memory 191072 kb
Host smart-73d19484-e634-4e47-bcb7-ed2db07e73ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448589683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3448589683
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.841063484
Short name T304
Test name
Test status
Simulation time 28958472335 ps
CPU time 63.27 seconds
Started Apr 18 12:24:00 PM PDT 24
Finished Apr 18 12:25:04 PM PDT 24
Peak memory 190296 kb
Host smart-c5f27bfd-87fc-44b8-a86b-29f6c13d65fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841063484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.841063484
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1977199819
Short name T398
Test name
Test status
Simulation time 776899848972 ps
CPU time 705.39 seconds
Started Apr 18 12:23:58 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 189040 kb
Host smart-ffec1082-5f33-487a-abf3-ec9fc9745809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977199819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1977199819
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.902835010
Short name T313
Test name
Test status
Simulation time 109304764863 ps
CPU time 56.19 seconds
Started Apr 18 12:22:26 PM PDT 24
Finished Apr 18 12:23:23 PM PDT 24
Peak memory 182596 kb
Host smart-b475a2a1-1a5a-40d7-9e1e-6e12f58a9d55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902835010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.902835010
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2112958120
Short name T371
Test name
Test status
Simulation time 111092961669 ps
CPU time 145.31 seconds
Started Apr 18 12:22:31 PM PDT 24
Finished Apr 18 12:24:57 PM PDT 24
Peak memory 182536 kb
Host smart-2e4852ff-ac42-4507-93f5-d3af3445a59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112958120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2112958120
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4206780925
Short name T268
Test name
Test status
Simulation time 143004749890 ps
CPU time 138.8 seconds
Started Apr 18 12:22:25 PM PDT 24
Finished Apr 18 12:24:44 PM PDT 24
Peak memory 194600 kb
Host smart-7fc3a142-6b79-453f-93c3-30b9c26d6676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206780925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4206780925
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1407676738
Short name T226
Test name
Test status
Simulation time 250545651619 ps
CPU time 884.12 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:38:42 PM PDT 24
Peak memory 190376 kb
Host smart-0bfe2dc8-aaa9-41ab-a053-7703d5b5c187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407676738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1407676738
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.915105536
Short name T401
Test name
Test status
Simulation time 54512087186 ps
CPU time 97.04 seconds
Started Apr 18 12:23:40 PM PDT 24
Finished Apr 18 12:25:19 PM PDT 24
Peak memory 181104 kb
Host smart-8ecdd327-c9d9-40db-a78d-eb1650f66618
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915105536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.915105536
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.903935824
Short name T403
Test name
Test status
Simulation time 129241532799 ps
CPU time 190.76 seconds
Started Apr 18 12:23:57 PM PDT 24
Finished Apr 18 12:27:09 PM PDT 24
Peak memory 182008 kb
Host smart-19ef67f9-1248-4ee2-ac2f-69d9d1f4bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903935824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.903935824
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2754966500
Short name T296
Test name
Test status
Simulation time 313352082079 ps
CPU time 148.25 seconds
Started Apr 18 12:23:41 PM PDT 24
Finished Apr 18 12:26:10 PM PDT 24
Peak memory 189588 kb
Host smart-1557d967-bfca-4476-ab18-90a982b18e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754966500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2754966500
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3978466351
Short name T409
Test name
Test status
Simulation time 91723151975 ps
CPU time 141.77 seconds
Started Apr 18 12:22:36 PM PDT 24
Finished Apr 18 12:24:59 PM PDT 24
Peak memory 192944 kb
Host smart-2dd5363d-f15b-4db6-a91a-84d6fd868317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978466351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3978466351
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1596845682
Short name T381
Test name
Test status
Simulation time 128831109595 ps
CPU time 184.79 seconds
Started Apr 18 12:22:39 PM PDT 24
Finished Apr 18 12:25:45 PM PDT 24
Peak memory 182608 kb
Host smart-23b5a4c5-01f8-48ba-98ff-f8e4f0cfc147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596845682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1596845682
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1915839657
Short name T345
Test name
Test status
Simulation time 676604589511 ps
CPU time 371.88 seconds
Started Apr 18 12:23:57 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 182032 kb
Host smart-caa73af3-62b5-46e5-ba21-7894d91142ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915839657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1915839657
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2213170181
Short name T355
Test name
Test status
Simulation time 174794935996 ps
CPU time 238.36 seconds
Started Apr 18 12:23:56 PM PDT 24
Finished Apr 18 12:27:56 PM PDT 24
Peak memory 182016 kb
Host smart-b1c74e93-86c7-4598-a967-46b87929feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213170181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2213170181
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1712523464
Short name T425
Test name
Test status
Simulation time 146760323713 ps
CPU time 145.38 seconds
Started Apr 18 12:22:41 PM PDT 24
Finished Apr 18 12:25:07 PM PDT 24
Peak memory 190620 kb
Host smart-72478331-38df-4706-bd14-ab098d4df4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712523464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1712523464
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3881111234
Short name T383
Test name
Test status
Simulation time 371160924741 ps
CPU time 141.1 seconds
Started Apr 18 12:22:47 PM PDT 24
Finished Apr 18 12:25:09 PM PDT 24
Peak memory 194196 kb
Host smart-4ab5d033-d412-407c-bc3c-4923b3e9a27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881111234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3881111234
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1904027973
Short name T82
Test name
Test status
Simulation time 188168548360 ps
CPU time 331.18 seconds
Started Apr 18 12:24:37 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 180068 kb
Host smart-fd955d04-b8d4-4cbc-8ee2-350d48484b0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904027973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1904027973
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1984167006
Short name T376
Test name
Test status
Simulation time 560572679924 ps
CPU time 231.23 seconds
Started Apr 18 12:22:46 PM PDT 24
Finished Apr 18 12:26:38 PM PDT 24
Peak memory 182404 kb
Host smart-6bdb1d07-459d-43f2-8f6c-4d3c05ef972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984167006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1984167006
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2262652630
Short name T132
Test name
Test status
Simulation time 10791838033 ps
CPU time 9.14 seconds
Started Apr 18 12:22:47 PM PDT 24
Finished Apr 18 12:22:57 PM PDT 24
Peak memory 182608 kb
Host smart-c2ba67e0-e4fb-4829-a6c8-04738f1f9bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262652630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2262652630
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2904195296
Short name T273
Test name
Test status
Simulation time 147891084565 ps
CPU time 247.88 seconds
Started Apr 18 12:24:30 PM PDT 24
Finished Apr 18 12:28:39 PM PDT 24
Peak memory 180948 kb
Host smart-ad33e550-3d38-493d-a432-d254b251aa85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904195296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2904195296
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2446726546
Short name T360
Test name
Test status
Simulation time 547916638096 ps
CPU time 130 seconds
Started Apr 18 12:24:28 PM PDT 24
Finished Apr 18 12:26:39 PM PDT 24
Peak memory 180556 kb
Host smart-10832f45-a557-48d6-bbc0-d5c0f139f893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446726546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2446726546
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2246636267
Short name T166
Test name
Test status
Simulation time 406569384621 ps
CPU time 219.61 seconds
Started Apr 18 12:24:31 PM PDT 24
Finished Apr 18 12:28:12 PM PDT 24
Peak memory 190324 kb
Host smart-37d2210d-5ed2-4659-b82c-e6e2c529a4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246636267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2246636267
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1585259100
Short name T402
Test name
Test status
Simulation time 110283248954 ps
CPU time 44.86 seconds
Started Apr 18 12:22:50 PM PDT 24
Finished Apr 18 12:23:36 PM PDT 24
Peak memory 190684 kb
Host smart-c49f0d87-6c6a-4b98-8c98-bd907187f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585259100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1585259100
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2809969830
Short name T392
Test name
Test status
Simulation time 207733860587 ps
CPU time 378.45 seconds
Started Apr 18 12:22:57 PM PDT 24
Finished Apr 18 12:29:16 PM PDT 24
Peak memory 182420 kb
Host smart-b2f4ce8f-94ab-4203-b057-09f505060075
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809969830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2809969830
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2686257284
Short name T436
Test name
Test status
Simulation time 1291472283 ps
CPU time 1.62 seconds
Started Apr 18 12:22:58 PM PDT 24
Finished Apr 18 12:23:00 PM PDT 24
Peak memory 182200 kb
Host smart-17d88132-04bd-42e8-b0dd-771787ba7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686257284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2686257284
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.926533274
Short name T280
Test name
Test status
Simulation time 17554336310 ps
CPU time 74.2 seconds
Started Apr 18 12:22:57 PM PDT 24
Finished Apr 18 12:24:12 PM PDT 24
Peak memory 190640 kb
Host smart-2e1cd1d4-968d-4932-83be-7de33173e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926533274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.926533274
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3927429097
Short name T105
Test name
Test status
Simulation time 103253494631 ps
CPU time 95.83 seconds
Started Apr 18 12:22:58 PM PDT 24
Finished Apr 18 12:24:35 PM PDT 24
Peak memory 194732 kb
Host smart-c8a8fb3a-4894-4863-850c-0e6072d9165b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927429097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3927429097
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.476391594
Short name T309
Test name
Test status
Simulation time 1349281724944 ps
CPU time 761.26 seconds
Started Apr 18 12:24:30 PM PDT 24
Finished Apr 18 12:37:13 PM PDT 24
Peak memory 180812 kb
Host smart-fb460841-73c2-43a0-9446-8309de2c71c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476391594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.476391594
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2913644922
Short name T395
Test name
Test status
Simulation time 144811986636 ps
CPU time 217.5 seconds
Started Apr 18 12:23:03 PM PDT 24
Finished Apr 18 12:26:41 PM PDT 24
Peak memory 182536 kb
Host smart-72fc3099-86a1-4959-bde6-398f1b1e753d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913644922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2913644922
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1722024489
Short name T362
Test name
Test status
Simulation time 66185863 ps
CPU time 0.56 seconds
Started Apr 18 12:23:02 PM PDT 24
Finished Apr 18 12:23:02 PM PDT 24
Peak memory 182132 kb
Host smart-52a52a07-76b5-425b-a3e2-bb85bfb71f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722024489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1722024489
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2095583874
Short name T426
Test name
Test status
Simulation time 113165377128 ps
CPU time 158.37 seconds
Started Apr 18 12:24:31 PM PDT 24
Finished Apr 18 12:27:10 PM PDT 24
Peak memory 193828 kb
Host smart-17c66d32-cfc8-4a0e-a1e4-7226c084620d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095583874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2095583874
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.624855756
Short name T170
Test name
Test status
Simulation time 142019313009 ps
CPU time 228.17 seconds
Started Apr 18 12:23:07 PM PDT 24
Finished Apr 18 12:26:56 PM PDT 24
Peak memory 182544 kb
Host smart-42044d34-019f-4d05-9575-40c117473238
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624855756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.624855756
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2691632321
Short name T24
Test name
Test status
Simulation time 421508379171 ps
CPU time 164.57 seconds
Started Apr 18 12:23:07 PM PDT 24
Finished Apr 18 12:25:52 PM PDT 24
Peak memory 182404 kb
Host smart-b82092fa-7d6b-47de-a6e9-b454f6d3a34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691632321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2691632321
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3842051155
Short name T214
Test name
Test status
Simulation time 79685594937 ps
CPU time 608.74 seconds
Started Apr 18 12:23:09 PM PDT 24
Finished Apr 18 12:33:19 PM PDT 24
Peak memory 190788 kb
Host smart-bfa6028e-c570-40ed-b59a-43b1709458a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842051155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3842051155
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.702469185
Short name T356
Test name
Test status
Simulation time 695278894 ps
CPU time 0.8 seconds
Started Apr 18 12:23:06 PM PDT 24
Finished Apr 18 12:23:08 PM PDT 24
Peak memory 190928 kb
Host smart-e9e16972-4fff-443a-931f-615a665780e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702469185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.702469185
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1562909116
Short name T86
Test name
Test status
Simulation time 213827082 ps
CPU time 0.63 seconds
Started Apr 18 12:23:17 PM PDT 24
Finished Apr 18 12:23:19 PM PDT 24
Peak memory 182276 kb
Host smart-bd6a9b4d-2091-476e-b6a2-bcc042c2d3a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562909116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1562909116
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1031888547
Short name T323
Test name
Test status
Simulation time 234185058647 ps
CPU time 401.47 seconds
Started Apr 18 12:21:39 PM PDT 24
Finished Apr 18 12:28:21 PM PDT 24
Peak memory 182408 kb
Host smart-1ac6e03f-55db-4476-9495-59808897258c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031888547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1031888547
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3768614621
Short name T367
Test name
Test status
Simulation time 46968826634 ps
CPU time 77.16 seconds
Started Apr 18 12:23:48 PM PDT 24
Finished Apr 18 12:25:06 PM PDT 24
Peak memory 182424 kb
Host smart-aac6adde-a223-4e58-801a-495c157d0cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768614621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3768614621
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.580113811
Short name T254
Test name
Test status
Simulation time 100029564826 ps
CPU time 498.91 seconds
Started Apr 18 12:22:27 PM PDT 24
Finished Apr 18 12:30:47 PM PDT 24
Peak memory 190680 kb
Host smart-e9769c2d-3935-45b7-8da6-c6bdec6526c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580113811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.580113811
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3503968340
Short name T347
Test name
Test status
Simulation time 83187546 ps
CPU time 0.71 seconds
Started Apr 18 12:23:03 PM PDT 24
Finished Apr 18 12:23:05 PM PDT 24
Peak memory 179844 kb
Host smart-1612c257-af31-4d6f-9af4-2526d7746ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503968340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3503968340
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3715698965
Short name T428
Test name
Test status
Simulation time 84022318122 ps
CPU time 62.16 seconds
Started Apr 18 12:22:15 PM PDT 24
Finished Apr 18 12:23:18 PM PDT 24
Peak memory 194280 kb
Host smart-118b8992-7dd9-4515-92e8-fc3b7b8138ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715698965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3715698965
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.3422139148
Short name T152
Test name
Test status
Simulation time 69328509123 ps
CPU time 203.96 seconds
Started Apr 18 12:23:17 PM PDT 24
Finished Apr 18 12:26:42 PM PDT 24
Peak memory 190736 kb
Host smart-41f6c83b-61a0-45c7-94b2-b66b321a0631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422139148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3422139148
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1032371809
Short name T266
Test name
Test status
Simulation time 101609592895 ps
CPU time 996.56 seconds
Started Apr 18 12:24:28 PM PDT 24
Finished Apr 18 12:41:06 PM PDT 24
Peak memory 188844 kb
Host smart-314f65fc-c0a0-4e01-a2c0-1a289a3263c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032371809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1032371809
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.997010199
Short name T411
Test name
Test status
Simulation time 232385407305 ps
CPU time 105.03 seconds
Started Apr 18 12:23:21 PM PDT 24
Finished Apr 18 12:25:06 PM PDT 24
Peak memory 190736 kb
Host smart-c37caf71-bf22-45be-bbb9-8120c43c2fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997010199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.997010199
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.249943030
Short name T322
Test name
Test status
Simulation time 15637959981 ps
CPU time 81.34 seconds
Started Apr 18 12:24:30 PM PDT 24
Finished Apr 18 12:25:53 PM PDT 24
Peak memory 192392 kb
Host smart-dea0c8da-e727-4db3-a431-ef506750d5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249943030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.249943030
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2641164111
Short name T205
Test name
Test status
Simulation time 183168981344 ps
CPU time 296.85 seconds
Started Apr 18 12:23:16 PM PDT 24
Finished Apr 18 12:28:14 PM PDT 24
Peak memory 190620 kb
Host smart-5d27bd14-c275-48dc-99d3-7fd7287ac1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641164111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2641164111
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.993593755
Short name T167
Test name
Test status
Simulation time 978932811047 ps
CPU time 1390.7 seconds
Started Apr 18 12:23:15 PM PDT 24
Finished Apr 18 12:46:26 PM PDT 24
Peak memory 190752 kb
Host smart-052dfa3c-5c68-4bb9-91b2-dbcf946e18ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993593755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.993593755
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1497708872
Short name T341
Test name
Test status
Simulation time 27312814901 ps
CPU time 28.56 seconds
Started Apr 18 12:22:42 PM PDT 24
Finished Apr 18 12:23:11 PM PDT 24
Peak memory 182012 kb
Host smart-09f1b0df-3b04-4527-bf2b-2d076bea13b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497708872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1497708872
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.934544044
Short name T394
Test name
Test status
Simulation time 857384389418 ps
CPU time 169.13 seconds
Started Apr 18 12:20:28 PM PDT 24
Finished Apr 18 12:23:17 PM PDT 24
Peak memory 182628 kb
Host smart-4f00c042-fa35-401e-901d-2adec89c7346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934544044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.934544044
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1326119500
Short name T277
Test name
Test status
Simulation time 314901016328 ps
CPU time 443.46 seconds
Started Apr 18 12:23:54 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 194180 kb
Host smart-d9f47a42-8eb8-435a-9d11-8104adc9f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326119500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1326119500
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2769852086
Short name T283
Test name
Test status
Simulation time 56008955795 ps
CPU time 207.14 seconds
Started Apr 18 12:23:54 PM PDT 24
Finished Apr 18 12:27:22 PM PDT 24
Peak memory 190624 kb
Host smart-7b08a38c-d61d-47c0-aeee-41d679f73b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769852086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2769852086
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.1144354615
Short name T255
Test name
Test status
Simulation time 214013969220 ps
CPU time 112.41 seconds
Started Apr 18 12:24:38 PM PDT 24
Finished Apr 18 12:26:31 PM PDT 24
Peak memory 194100 kb
Host smart-0820d46f-4a52-4083-9188-fb2019337f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144354615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1144354615
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.992400868
Short name T185
Test name
Test status
Simulation time 538056505479 ps
CPU time 290.65 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:28:20 PM PDT 24
Peak memory 190304 kb
Host smart-b5eb0dba-f785-4e3b-9b2a-87ccde090892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992400868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.992400868
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1797731232
Short name T191
Test name
Test status
Simulation time 78729891026 ps
CPU time 272.69 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:28:02 PM PDT 24
Peak memory 190284 kb
Host smart-f5843f6d-6219-4407-9a86-36cd03ac4959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797731232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1797731232
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4110631125
Short name T449
Test name
Test status
Simulation time 275461143335 ps
CPU time 115.41 seconds
Started Apr 18 12:23:21 PM PDT 24
Finished Apr 18 12:25:17 PM PDT 24
Peak memory 191072 kb
Host smart-d80bbc9b-9f67-4e38-8f06-81c0daaae6b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110631125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4110631125
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.988403528
Short name T138
Test name
Test status
Simulation time 44828355052 ps
CPU time 80.46 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:24:50 PM PDT 24
Peak memory 182132 kb
Host smart-afb01929-9f01-442c-afc8-1639e637db7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988403528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.988403528
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1715557414
Short name T200
Test name
Test status
Simulation time 194520734865 ps
CPU time 1885.36 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:54:54 PM PDT 24
Peak memory 190380 kb
Host smart-1b5eb7a1-59fc-4be9-8506-f67f3ea800db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715557414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1715557414
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2810676695
Short name T207
Test name
Test status
Simulation time 1104264036581 ps
CPU time 298.55 seconds
Started Apr 18 12:23:24 PM PDT 24
Finished Apr 18 12:28:23 PM PDT 24
Peak memory 190556 kb
Host smart-54694192-ba5a-433f-92e0-675f38cb7e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810676695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2810676695
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4141155674
Short name T150
Test name
Test status
Simulation time 74469442699 ps
CPU time 121.9 seconds
Started Apr 18 12:23:43 PM PDT 24
Finished Apr 18 12:25:45 PM PDT 24
Peak memory 190372 kb
Host smart-8998dc06-fabd-446a-9f21-5b04a320cb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141155674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4141155674
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1577616429
Short name T433
Test name
Test status
Simulation time 112128272881 ps
CPU time 62 seconds
Started Apr 18 12:23:28 PM PDT 24
Finished Apr 18 12:24:30 PM PDT 24
Peak memory 182428 kb
Host smart-ba7fd388-e30f-461d-8a1c-ac0b95e3937d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577616429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1577616429
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.610798509
Short name T314
Test name
Test status
Simulation time 99552628516 ps
CPU time 54.91 seconds
Started Apr 18 12:23:27 PM PDT 24
Finished Apr 18 12:24:23 PM PDT 24
Peak memory 182356 kb
Host smart-0c3f2582-2d58-479e-9b4c-27bad8a0c1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610798509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.610798509
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3816160944
Short name T217
Test name
Test status
Simulation time 333902635906 ps
CPU time 541.05 seconds
Started Apr 18 12:20:30 PM PDT 24
Finished Apr 18 12:29:32 PM PDT 24
Peak memory 182460 kb
Host smart-5d7c4f95-7194-4a43-ac8b-b00247444e51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816160944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3816160944
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1204855242
Short name T357
Test name
Test status
Simulation time 57362533257 ps
CPU time 36.62 seconds
Started Apr 18 12:22:41 PM PDT 24
Finished Apr 18 12:23:19 PM PDT 24
Peak memory 181324 kb
Host smart-b6a3ac15-96ab-40fc-9487-4b8327aeede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204855242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1204855242
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2008186668
Short name T346
Test name
Test status
Simulation time 49788569977 ps
CPU time 22.28 seconds
Started Apr 18 12:21:19 PM PDT 24
Finished Apr 18 12:21:42 PM PDT 24
Peak memory 182612 kb
Host smart-afb7bf20-a04c-4028-a29b-577285b4bffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008186668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2008186668
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3093013995
Short name T382
Test name
Test status
Simulation time 119500864 ps
CPU time 0.63 seconds
Started Apr 18 12:23:53 PM PDT 24
Finished Apr 18 12:23:55 PM PDT 24
Peak memory 182116 kb
Host smart-3a88e3de-76b1-4d67-bdbd-d4689aeb2d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093013995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3093013995
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1785090373
Short name T142
Test name
Test status
Simulation time 1475849810875 ps
CPU time 1111.09 seconds
Started Apr 18 12:21:39 PM PDT 24
Finished Apr 18 12:40:11 PM PDT 24
Peak memory 190604 kb
Host smart-fee4f0ef-4cf8-4854-bfaa-f7769867226c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785090373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1785090373
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.3403163880
Short name T278
Test name
Test status
Simulation time 181374114671 ps
CPU time 294.22 seconds
Started Apr 18 12:24:39 PM PDT 24
Finished Apr 18 12:29:34 PM PDT 24
Peak memory 190336 kb
Host smart-27739c81-679e-42ab-bd71-4a4fa11d7d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403163880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3403163880
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.785944936
Short name T186
Test name
Test status
Simulation time 1079900099852 ps
CPU time 599.82 seconds
Started Apr 18 12:24:39 PM PDT 24
Finished Apr 18 12:34:40 PM PDT 24
Peak memory 190348 kb
Host smart-da70f835-a8f3-4a77-ab9c-68205b52398c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785944936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.785944936
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2465921527
Short name T331
Test name
Test status
Simulation time 676413996615 ps
CPU time 349.75 seconds
Started Apr 18 12:23:23 PM PDT 24
Finished Apr 18 12:29:13 PM PDT 24
Peak memory 190800 kb
Host smart-aa5b0081-eef6-4448-b8c7-00344d5fb885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465921527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2465921527
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1172891692
Short name T129
Test name
Test status
Simulation time 435705399062 ps
CPU time 198.75 seconds
Started Apr 18 12:23:20 PM PDT 24
Finished Apr 18 12:26:39 PM PDT 24
Peak memory 190796 kb
Host smart-c033c613-2a42-4a9d-b852-74314133aaae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172891692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1172891692
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2475034243
Short name T146
Test name
Test status
Simulation time 162665505744 ps
CPU time 233.05 seconds
Started Apr 18 12:23:27 PM PDT 24
Finished Apr 18 12:27:21 PM PDT 24
Peak memory 190564 kb
Host smart-237b7ae2-ce8b-4e71-ac0e-388727758eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475034243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2475034243
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.69022408
Short name T8
Test name
Test status
Simulation time 51789353415 ps
CPU time 81.96 seconds
Started Apr 18 12:23:27 PM PDT 24
Finished Apr 18 12:24:49 PM PDT 24
Peak memory 182172 kb
Host smart-ac87c5cb-aeb6-451c-a173-b5f084ddbb28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69022408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.69022408
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1953977371
Short name T440
Test name
Test status
Simulation time 682797443598 ps
CPU time 798.25 seconds
Started Apr 18 12:23:22 PM PDT 24
Finished Apr 18 12:36:40 PM PDT 24
Peak memory 190800 kb
Host smart-3eddcfe6-6a60-49d4-888d-cee15ac699c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953977371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1953977371
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1736962684
Short name T264
Test name
Test status
Simulation time 289537960522 ps
CPU time 499.94 seconds
Started Apr 18 12:20:30 PM PDT 24
Finished Apr 18 12:28:51 PM PDT 24
Peak memory 182452 kb
Host smart-33f318d9-6d1b-4e0f-9aec-5d072a67468d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736962684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1736962684
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.566699816
Short name T380
Test name
Test status
Simulation time 371250563845 ps
CPU time 148.05 seconds
Started Apr 18 12:20:26 PM PDT 24
Finished Apr 18 12:22:55 PM PDT 24
Peak memory 182404 kb
Host smart-9d40bc90-46e8-41c4-94d6-8c11423fafcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566699816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.566699816
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.949455600
Short name T408
Test name
Test status
Simulation time 539471443 ps
CPU time 0.86 seconds
Started Apr 18 12:23:52 PM PDT 24
Finished Apr 18 12:23:55 PM PDT 24
Peak memory 181880 kb
Host smart-7a97f28e-88cc-4656-913e-53034dc714a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949455600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.949455600
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4155405182
Short name T189
Test name
Test status
Simulation time 167655341006 ps
CPU time 1889.91 seconds
Started Apr 18 12:20:37 PM PDT 24
Finished Apr 18 12:52:07 PM PDT 24
Peak memory 190728 kb
Host smart-bb81d789-dba8-4c47-a064-1f99a55107de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155405182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4155405182
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3373088290
Short name T36
Test name
Test status
Simulation time 5818625741 ps
CPU time 61.85 seconds
Started Apr 18 12:21:50 PM PDT 24
Finished Apr 18 12:22:53 PM PDT 24
Peak memory 193768 kb
Host smart-690127ae-f340-413b-a202-cfc48f0c83e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373088290 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3373088290
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.rv_timer_random.1021416821
Short name T447
Test name
Test status
Simulation time 75782934511 ps
CPU time 280.19 seconds
Started Apr 18 12:24:32 PM PDT 24
Finished Apr 18 12:29:14 PM PDT 24
Peak memory 189824 kb
Host smart-d395d33b-c3a2-4f25-a9bf-40696dc3344b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021416821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1021416821
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3328041146
Short name T10
Test name
Test status
Simulation time 41199134078 ps
CPU time 66.23 seconds
Started Apr 18 12:23:29 PM PDT 24
Finished Apr 18 12:24:35 PM PDT 24
Peak memory 182432 kb
Host smart-7d68c39d-e2e5-42c2-b37a-790d40b9807b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328041146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3328041146
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1661543422
Short name T130
Test name
Test status
Simulation time 21906883741 ps
CPU time 9.3 seconds
Started Apr 18 12:23:26 PM PDT 24
Finished Apr 18 12:23:36 PM PDT 24
Peak memory 182240 kb
Host smart-037edb35-4a44-47f7-bbc0-5fa5682c8f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661543422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1661543422
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3203039302
Short name T202
Test name
Test status
Simulation time 71870548767 ps
CPU time 167.45 seconds
Started Apr 18 12:24:41 PM PDT 24
Finished Apr 18 12:27:29 PM PDT 24
Peak memory 190336 kb
Host smart-ef0f8df8-e2f6-4967-8343-c646d41fe29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203039302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3203039302
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3656026156
Short name T201
Test name
Test status
Simulation time 746366806276 ps
CPU time 723.01 seconds
Started Apr 18 12:23:26 PM PDT 24
Finished Apr 18 12:35:29 PM PDT 24
Peak memory 190632 kb
Host smart-55d4c41b-e984-4dd0-ae99-3f6c2a92b148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656026156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3656026156
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.492992903
Short name T184
Test name
Test status
Simulation time 198809161132 ps
CPU time 472.14 seconds
Started Apr 18 12:24:40 PM PDT 24
Finished Apr 18 12:32:33 PM PDT 24
Peak memory 190348 kb
Host smart-fdd9f618-b68e-499a-9225-94f43945c6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492992903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.492992903
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4043853512
Short name T155
Test name
Test status
Simulation time 58334748183 ps
CPU time 100.63 seconds
Started Apr 18 12:24:38 PM PDT 24
Finished Apr 18 12:26:20 PM PDT 24
Peak memory 193992 kb
Host smart-36f5cd71-afe1-43bc-aea6-6683f12a4564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043853512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4043853512
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3363569766
Short name T209
Test name
Test status
Simulation time 136087373695 ps
CPU time 2216.06 seconds
Started Apr 18 12:24:37 PM PDT 24
Finished Apr 18 01:01:35 PM PDT 24
Peak memory 190344 kb
Host smart-52df87f8-1bb2-498d-969d-8e3f828d4252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363569766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3363569766
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2221676503
Short name T79
Test name
Test status
Simulation time 49862777837 ps
CPU time 31.4 seconds
Started Apr 18 12:23:37 PM PDT 24
Finished Apr 18 12:24:09 PM PDT 24
Peak memory 181940 kb
Host smart-662920f6-e4e2-4d3c-be3b-5fdb03eb0854
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221676503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2221676503
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.866669058
Short name T368
Test name
Test status
Simulation time 734825773408 ps
CPU time 157.01 seconds
Started Apr 18 12:22:14 PM PDT 24
Finished Apr 18 12:24:51 PM PDT 24
Peak memory 182536 kb
Host smart-f97b1c7c-d9f4-45a2-9659-2a99c07e5659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866669058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.866669058
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3620670452
Short name T338
Test name
Test status
Simulation time 201999496676 ps
CPU time 397 seconds
Started Apr 18 12:22:41 PM PDT 24
Finished Apr 18 12:29:20 PM PDT 24
Peak memory 192936 kb
Host smart-2818322e-c553-411d-9cbf-e95ceb9aadc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620670452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3620670452
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2067294071
Short name T429
Test name
Test status
Simulation time 216052411529 ps
CPU time 152.07 seconds
Started Apr 18 12:20:45 PM PDT 24
Finished Apr 18 12:23:17 PM PDT 24
Peak memory 182868 kb
Host smart-a4a225ad-0516-49f6-84f5-55be791c2aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067294071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2067294071
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2000576378
Short name T48
Test name
Test status
Simulation time 77081206792 ps
CPU time 551.7 seconds
Started Apr 18 12:23:04 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 205012 kb
Host smart-48f6eada-d853-42dc-bc90-0c246bf755b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000576378 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2000576378
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.4060614540
Short name T111
Test name
Test status
Simulation time 113717185881 ps
CPU time 1666.07 seconds
Started Apr 18 12:24:40 PM PDT 24
Finished Apr 18 12:52:27 PM PDT 24
Peak memory 190392 kb
Host smart-fbec0c8a-5efe-4b23-afe0-ebcecc47155d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060614540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4060614540
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.852504208
Short name T133
Test name
Test status
Simulation time 241927872534 ps
CPU time 180.41 seconds
Started Apr 18 12:24:40 PM PDT 24
Finished Apr 18 12:27:41 PM PDT 24
Peak memory 194028 kb
Host smart-e40f25e1-c939-4eba-80d6-6112c240e47b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852504208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.852504208
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3460169140
Short name T432
Test name
Test status
Simulation time 47652520077 ps
CPU time 75.53 seconds
Started Apr 18 12:24:40 PM PDT 24
Finished Apr 18 12:25:56 PM PDT 24
Peak memory 182000 kb
Host smart-4b96dbdb-332a-4fb0-b121-e02fe9a5b6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460169140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3460169140
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1727211063
Short name T286
Test name
Test status
Simulation time 347022058549 ps
CPU time 322 seconds
Started Apr 18 12:23:25 PM PDT 24
Finished Apr 18 12:28:47 PM PDT 24
Peak memory 190364 kb
Host smart-46fc4681-9ffd-4ec5-9e22-fd4b15f67007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727211063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1727211063
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3708858218
Short name T198
Test name
Test status
Simulation time 39029065567 ps
CPU time 62.89 seconds
Started Apr 18 12:23:26 PM PDT 24
Finished Apr 18 12:24:30 PM PDT 24
Peak memory 182124 kb
Host smart-6964629a-2853-46f7-b0c1-7c8ac220b117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708858218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3708858218
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3328747391
Short name T39
Test name
Test status
Simulation time 363094317325 ps
CPU time 267.33 seconds
Started Apr 18 12:23:27 PM PDT 24
Finished Apr 18 12:27:55 PM PDT 24
Peak memory 192656 kb
Host smart-cf898b87-1104-4895-b6dc-1048bd635ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328747391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3328747391
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3156781448
Short name T225
Test name
Test status
Simulation time 53886319800 ps
CPU time 86.38 seconds
Started Apr 18 12:24:39 PM PDT 24
Finished Apr 18 12:26:06 PM PDT 24
Peak memory 190344 kb
Host smart-ca2481ae-341e-4a35-b43e-0860ce7e7dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156781448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3156781448
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1452882620
Short name T108
Test name
Test status
Simulation time 51592841946 ps
CPU time 86.6 seconds
Started Apr 18 12:24:41 PM PDT 24
Finished Apr 18 12:26:08 PM PDT 24
Peak memory 190392 kb
Host smart-ff8f9a5c-500a-40b4-896b-77b125a55599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452882620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1452882620
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%