| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.65 | 99.33 | 99.04 | 100.00 | 100.00 | 100.00 | 99.55 |
| T504 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4034355487 | Oct 14 10:06:35 PM UTC 24 | Oct 14 10:06:37 PM UTC 24 | 50039477 ps | ||
| T505 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.145679207 | Oct 14 10:06:33 PM UTC 24 | Oct 14 10:06:38 PM UTC 24 | 424675997 ps | ||
| T506 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.969202158 | Oct 14 10:06:36 PM UTC 24 | Oct 14 10:06:38 PM UTC 24 | 14173569 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1575003980 | Oct 14 10:06:36 PM UTC 24 | Oct 14 10:06:39 PM UTC 24 | 105991558 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3534176155 | Oct 14 10:06:37 PM UTC 24 | Oct 14 10:06:39 PM UTC 24 | 14506157 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2853028436 | Oct 14 10:06:37 PM UTC 24 | Oct 14 10:06:40 PM UTC 24 | 39138199 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.282976109 | Oct 14 10:06:37 PM UTC 24 | Oct 14 10:06:40 PM UTC 24 | 137515996 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3587790649 | Oct 14 10:06:37 PM UTC 24 | Oct 14 10:06:40 PM UTC 24 | 79552279 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.2577115100 | Oct 14 10:06:37 PM UTC 24 | Oct 14 10:06:40 PM UTC 24 | 176523260 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2303303621 | Oct 14 10:06:39 PM UTC 24 | Oct 14 10:06:41 PM UTC 24 | 30090650 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.3051813117 | Oct 14 10:06:39 PM UTC 24 | Oct 14 10:06:41 PM UTC 24 | 192527455 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1405346564 | Oct 14 10:06:39 PM UTC 24 | Oct 14 10:06:41 PM UTC 24 | 18258851 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4104932817 | Oct 14 10:06:39 PM UTC 24 | Oct 14 10:06:42 PM UTC 24 | 51433254 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3478087946 | Oct 14 10:06:41 PM UTC 24 | Oct 14 10:06:42 PM UTC 24 | 35355493 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1760646139 | Oct 14 10:06:40 PM UTC 24 | Oct 14 10:06:42 PM UTC 24 | 59481417 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1384426129 | Oct 14 10:06:40 PM UTC 24 | Oct 14 10:06:43 PM UTC 24 | 54169679 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.1998195058 | Oct 14 10:06:40 PM UTC 24 | Oct 14 10:06:44 PM UTC 24 | 27902164 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.3766733286 | Oct 14 10:06:42 PM UTC 24 | Oct 14 10:06:44 PM UTC 24 | 48878193 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3193815790 | Oct 14 10:06:42 PM UTC 24 | Oct 14 10:06:44 PM UTC 24 | 21990618 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2499444634 | Oct 14 10:06:42 PM UTC 24 | Oct 14 10:06:44 PM UTC 24 | 19814327 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2300381037 | Oct 14 10:06:42 PM UTC 24 | Oct 14 10:06:44 PM UTC 24 | 111675450 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3752377221 | Oct 14 10:06:42 PM UTC 24 | Oct 14 10:06:45 PM UTC 24 | 152137557 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.156341792 | Oct 14 10:06:42 PM UTC 24 | Oct 14 10:06:45 PM UTC 24 | 57015386 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1920898629 | Oct 14 10:06:44 PM UTC 24 | Oct 14 10:06:46 PM UTC 24 | 49495393 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3095127599 | Oct 14 10:06:44 PM UTC 24 | Oct 14 10:06:46 PM UTC 24 | 310639004 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3717367559 | Oct 14 10:06:44 PM UTC 24 | Oct 14 10:06:47 PM UTC 24 | 134478270 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.2192628792 | Oct 14 10:06:45 PM UTC 24 | Oct 14 10:06:47 PM UTC 24 | 54226271 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3732045189 | Oct 14 10:06:46 PM UTC 24 | Oct 14 10:06:47 PM UTC 24 | 65985105 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3628928201 | Oct 14 10:06:45 PM UTC 24 | Oct 14 10:06:47 PM UTC 24 | 29857970 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.564390559 | Oct 14 10:06:42 PM UTC 24 | Oct 14 10:06:48 PM UTC 24 | 151937606 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1856455558 | Oct 14 10:06:46 PM UTC 24 | Oct 14 10:06:48 PM UTC 24 | 311825090 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1684648245 | Oct 14 10:06:45 PM UTC 24 | Oct 14 10:06:48 PM UTC 24 | 25454044 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2133802873 | Oct 14 10:06:46 PM UTC 24 | Oct 14 10:06:48 PM UTC 24 | 133213002 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1780942153 | Oct 14 10:06:47 PM UTC 24 | Oct 14 10:06:49 PM UTC 24 | 53276825 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2821245743 | Oct 14 10:06:47 PM UTC 24 | Oct 14 10:06:49 PM UTC 24 | 107081636 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1908232943 | Oct 14 10:06:44 PM UTC 24 | Oct 14 10:06:49 PM UTC 24 | 663606357 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3557614397 | Oct 14 10:06:47 PM UTC 24 | Oct 14 10:06:50 PM UTC 24 | 100728370 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1051113812 | Oct 14 10:06:49 PM UTC 24 | Oct 14 10:06:51 PM UTC 24 | 33177610 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.2739947760 | Oct 14 10:06:49 PM UTC 24 | Oct 14 10:06:51 PM UTC 24 | 36546503 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3212492077 | Oct 14 10:06:49 PM UTC 24 | Oct 14 10:06:51 PM UTC 24 | 62426657 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3002525957 | Oct 14 10:06:49 PM UTC 24 | Oct 14 10:06:51 PM UTC 24 | 136854214 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1461407227 | Oct 14 10:06:49 PM UTC 24 | Oct 14 10:06:51 PM UTC 24 | 21116639 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1608859221 | Oct 14 10:06:51 PM UTC 24 | Oct 14 10:06:52 PM UTC 24 | 16134986 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.3734554978 | Oct 14 10:06:51 PM UTC 24 | Oct 14 10:06:52 PM UTC 24 | 14081951 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4033795403 | Oct 14 10:06:51 PM UTC 24 | Oct 14 10:06:53 PM UTC 24 | 24206654 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.3190728593 | Oct 14 10:06:49 PM UTC 24 | Oct 14 10:06:53 PM UTC 24 | 469966604 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1133347504 | Oct 14 10:06:50 PM UTC 24 | Oct 14 10:06:53 PM UTC 24 | 110523401 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.4148727348 | Oct 14 10:06:49 PM UTC 24 | Oct 14 10:06:53 PM UTC 24 | 241083216 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2271566244 | Oct 14 10:06:51 PM UTC 24 | Oct 14 10:06:53 PM UTC 24 | 27916423 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4057306339 | Oct 14 10:06:52 PM UTC 24 | Oct 14 10:06:54 PM UTC 24 | 39595685 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2310209285 | Oct 14 10:06:52 PM UTC 24 | Oct 14 10:06:54 PM UTC 24 | 14577765 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.827172201 | Oct 14 10:06:52 PM UTC 24 | Oct 14 10:06:54 PM UTC 24 | 17227069 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.1995083197 | Oct 14 10:06:52 PM UTC 24 | Oct 14 10:06:54 PM UTC 24 | 20294201 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1194907664 | Oct 14 10:06:52 PM UTC 24 | Oct 14 10:06:54 PM UTC 24 | 14984919 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.1939384885 | Oct 14 10:06:54 PM UTC 24 | Oct 14 10:06:56 PM UTC 24 | 14281178 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3413926998 | Oct 14 10:06:54 PM UTC 24 | Oct 14 10:06:56 PM UTC 24 | 14037407 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.4053161713 | Oct 14 10:06:54 PM UTC 24 | Oct 14 10:06:56 PM UTC 24 | 11596049 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1098734147 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 13557881 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3034769706 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 34236657 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.2767661237 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 33793099 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.70413759 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 13707931 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.4093059379 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 38748894 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.94533290 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 29380572 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.4133998127 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 13891692 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.748151574 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 36831580 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.1103401101 | Oct 14 10:06:56 PM UTC 24 | Oct 14 10:06:58 PM UTC 24 | 23988792 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.4272940530 | Oct 14 10:06:57 PM UTC 24 | Oct 14 10:07:00 PM UTC 24 | 13320533 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1217535048 | Oct 14 10:06:57 PM UTC 24 | Oct 14 10:07:00 PM UTC 24 | 29400138 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3082567319 | Oct 14 10:06:57 PM UTC 24 | Oct 14 10:07:00 PM UTC 24 | 13941581 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.2557698646 | Oct 14 10:06:59 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 57776381 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.1079274346 | Oct 14 10:06:59 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 42074994 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2235186220 | Oct 14 10:06:59 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 18006509 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2548022301 | Oct 14 10:06:59 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 19610420 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1852209101 | Oct 14 10:06:59 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 30547617 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.3384263787 | Oct 14 10:06:59 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 66174717 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3026669454 | Oct 14 10:07:00 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 12748328 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1987863316 | Oct 14 10:06:59 PM UTC 24 | Oct 14 10:07:01 PM UTC 24 | 15014244 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.2553231017 | Oct 14 10:07:00 PM UTC 24 | Oct 14 10:07:02 PM UTC 24 | 42942666 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.345841611 | Oct 14 10:07:01 PM UTC 24 | Oct 14 10:07:03 PM UTC 24 | 32846945 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.1152948567 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 427340308867 ps |
| CPU time | 168.23 seconds |
| Started | Oct 14 09:23:03 PM UTC 24 |
| Finished | Oct 14 09:25:54 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152948567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1152948567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all_with_rand_reset.1410026351 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3656440014 ps |
| CPU time | 33.59 seconds |
| Started | Oct 14 09:20:22 PM UTC 24 |
| Finished | Oct 14 09:20:57 PM UTC 24 |
| Peak memory | 203080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1410026351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.rv_timer_stress_all_with_rand_reset.1410026351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.2259763898 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 110237338040 ps |
| CPU time | 98.37 seconds |
| Started | Oct 14 09:20:25 PM UTC 24 |
| Finished | Oct 14 09:22:06 PM UTC 24 |
| Peak memory | 196680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259763898 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.2259763898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3460338302 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1119802672 ps |
| CPU time | 1.61 seconds |
| Started | Oct 14 10:05:56 PM UTC 24 |
| Finished | Oct 14 10:05:59 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460338302 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.3460338302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.1950555785 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 511252130920 ps |
| CPU time | 818.82 seconds |
| Started | Oct 14 09:20:22 PM UTC 24 |
| Finished | Oct 14 09:34:09 PM UTC 24 |
| Peak memory | 200356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950555785 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.1950555785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.1268761647 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 637390570430 ps |
| CPU time | 1933.59 seconds |
| Started | Oct 14 09:21:37 PM UTC 24 |
| Finished | Oct 14 09:54:09 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268761647 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.1268761647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.2850650339 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2089123764158 ps |
| CPU time | 3913.02 seconds |
| Started | Oct 14 09:22:36 PM UTC 24 |
| Finished | Oct 14 10:28:27 PM UTC 24 |
| Peak memory | 200440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850650339 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.2850650339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1718345947 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12568797 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 10:05:46 PM UTC 24 |
| Finished | Oct 14 10:05:48 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718345947 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.1718345947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.1123398207 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 712541197175 ps |
| CPU time | 1472.36 seconds |
| Started | Oct 14 09:26:19 PM UTC 24 |
| Finished | Oct 14 09:51:06 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123398207 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.1123398207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.3800624572 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2464762692090 ps |
| CPU time | 1948.86 seconds |
| Started | Oct 14 09:38:07 PM UTC 24 |
| Finished | Oct 14 10:10:57 PM UTC 24 |
| Peak memory | 200360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800624572 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.3800624572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2504164492 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 523168705187 ps |
| CPU time | 325.36 seconds |
| Started | Oct 14 09:21:03 PM UTC 24 |
| Finished | Oct 14 09:26:32 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504164492 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2504164492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.3420088343 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2597699341825 ps |
| CPU time | 2252.03 seconds |
| Started | Oct 14 09:37:12 PM UTC 24 |
| Finished | Oct 14 10:15:07 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420088343 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.3420088343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.4013712787 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 80339680538 ps |
| CPU time | 160.47 seconds |
| Started | Oct 14 09:20:38 PM UTC 24 |
| Finished | Oct 14 09:23:21 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013712787 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.4013712787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.635490040 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3101577528405 ps |
| CPU time | 3491 seconds |
| Started | Oct 14 09:31:18 PM UTC 24 |
| Finished | Oct 14 10:30:05 PM UTC 24 |
| Peak memory | 200368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635490040 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.635490040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.768657736 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1220925511408 ps |
| CPU time | 1540.21 seconds |
| Started | Oct 14 09:42:43 PM UTC 24 |
| Finished | Oct 14 10:08:40 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768657736 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.768657736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.125594500 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 250122784 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 09:20:25 PM UTC 24 |
| Finished | Oct 14 09:20:28 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125594500 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.125594500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.3477730091 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1856522769257 ps |
| CPU time | 1648.85 seconds |
| Started | Oct 14 09:26:55 PM UTC 24 |
| Finished | Oct 14 09:54:42 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477730091 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.3477730091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.2944146697 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2762592068219 ps |
| CPU time | 3336.99 seconds |
| Started | Oct 14 09:24:49 PM UTC 24 |
| Finished | Oct 14 10:20:59 PM UTC 24 |
| Peak memory | 200508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944146697 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.2944146697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.2288286356 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 234670906584 ps |
| CPU time | 1005.59 seconds |
| Started | Oct 14 09:32:21 PM UTC 24 |
| Finished | Oct 14 09:49:17 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288286356 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.2288286356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.3650657705 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1200776990888 ps |
| CPU time | 1650.13 seconds |
| Started | Oct 14 09:38:26 PM UTC 24 |
| Finished | Oct 14 10:06:13 PM UTC 24 |
| Peak memory | 200364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650657705 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.3650657705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.2197917673 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 145989911155 ps |
| CPU time | 317.07 seconds |
| Started | Oct 14 09:34:32 PM UTC 24 |
| Finished | Oct 14 09:39:53 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197917673 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2197917673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.1851419126 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2092250711129 ps |
| CPU time | 1750.73 seconds |
| Started | Oct 14 09:25:44 PM UTC 24 |
| Finished | Oct 14 09:55:14 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851419126 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.1851419126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.1435207133 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 230588209877 ps |
| CPU time | 640.79 seconds |
| Started | Oct 14 09:23:32 PM UTC 24 |
| Finished | Oct 14 09:34:20 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435207133 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.1435207133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.784564125 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 625908272701 ps |
| CPU time | 463.54 seconds |
| Started | Oct 14 10:02:47 PM UTC 24 |
| Finished | Oct 14 10:10:36 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784564125 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.784564125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.2318036026 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 266214171262 ps |
| CPU time | 552.59 seconds |
| Started | Oct 14 09:45:48 PM UTC 24 |
| Finished | Oct 14 09:55:07 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318036026 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2318036026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.3503069850 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 301267122929 ps |
| CPU time | 273.79 seconds |
| Started | Oct 14 09:21:01 PM UTC 24 |
| Finished | Oct 14 09:25:38 PM UTC 24 |
| Peak memory | 196668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503069850 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3503069850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.2259902547 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1418071957674 ps |
| CPU time | 824.24 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:34:28 PM UTC 24 |
| Peak memory | 200352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259902547 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.2259902547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.3305063464 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 425225544362 ps |
| CPU time | 1949.91 seconds |
| Started | Oct 14 09:30:44 PM UTC 24 |
| Finished | Oct 14 10:03:34 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305063464 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3305063464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.56682573 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 155096329658 ps |
| CPU time | 426.63 seconds |
| Started | Oct 14 09:53:26 PM UTC 24 |
| Finished | Oct 14 10:00:38 PM UTC 24 |
| Peak memory | 196732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56682573 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.56682573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.1639169241 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 106289927011 ps |
| CPU time | 725.47 seconds |
| Started | Oct 14 09:37:17 PM UTC 24 |
| Finished | Oct 14 09:49:31 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639169241 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1639169241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.359379804 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 163386530413 ps |
| CPU time | 665.59 seconds |
| Started | Oct 14 09:49:18 PM UTC 24 |
| Finished | Oct 14 10:00:32 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359379804 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.359379804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.308619912 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 109020095025 ps |
| CPU time | 538.44 seconds |
| Started | Oct 14 10:02:20 PM UTC 24 |
| Finished | Oct 14 10:11:25 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308619912 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.308619912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.140774873 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 95460071617 ps |
| CPU time | 333.78 seconds |
| Started | Oct 14 10:03:34 PM UTC 24 |
| Finished | Oct 14 10:09:12 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140774873 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.140774873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.3388919283 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 384894515856 ps |
| CPU time | 726.25 seconds |
| Started | Oct 14 09:28:07 PM UTC 24 |
| Finished | Oct 14 09:40:21 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388919283 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3388919283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.2786247193 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1644688848402 ps |
| CPU time | 621.58 seconds |
| Started | Oct 14 09:50:42 PM UTC 24 |
| Finished | Oct 14 10:01:12 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786247193 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2786247193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.1122055316 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 22220798 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:22 PM UTC 24 |
| Finished | Oct 14 10:06:24 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122055316 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1122055316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.3430659268 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 700064819317 ps |
| CPU time | 1910.93 seconds |
| Started | Oct 14 09:24:30 PM UTC 24 |
| Finished | Oct 14 09:56:39 PM UTC 24 |
| Peak memory | 200368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430659268 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.3430659268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2045648524 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 275655250111 ps |
| CPU time | 506.09 seconds |
| Started | Oct 14 10:05:28 PM UTC 24 |
| Finished | Oct 14 10:14:01 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045648524 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2045648524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.1729311748 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 312377789628 ps |
| CPU time | 1269.3 seconds |
| Started | Oct 14 09:41:35 PM UTC 24 |
| Finished | Oct 14 10:02:59 PM UTC 24 |
| Peak memory | 200508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729311748 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.1729311748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1605571447 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1401348400303 ps |
| CPU time | 2103 seconds |
| Started | Oct 14 09:20:51 PM UTC 24 |
| Finished | Oct 14 09:56:16 PM UTC 24 |
| Peak memory | 200364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605571447 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.1605571447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.1196705300 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 57828008257 ps |
| CPU time | 58.84 seconds |
| Started | Oct 14 09:20:21 PM UTC 24 |
| Finished | Oct 14 09:21:22 PM UTC 24 |
| Peak memory | 196884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196705300 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.1196705300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.3373410673 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 629854419361 ps |
| CPU time | 829.86 seconds |
| Started | Oct 14 09:52:17 PM UTC 24 |
| Finished | Oct 14 10:06:17 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373410673 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3373410673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.1608633513 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 129373289449 ps |
| CPU time | 606.64 seconds |
| Started | Oct 14 09:54:09 PM UTC 24 |
| Finished | Oct 14 10:04:24 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608633513 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1608633513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.488966654 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 116238849653 ps |
| CPU time | 296.24 seconds |
| Started | Oct 14 09:56:37 PM UTC 24 |
| Finished | Oct 14 10:01:37 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488966654 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.488966654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.2667424340 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 393880782403 ps |
| CPU time | 169.29 seconds |
| Started | Oct 14 09:56:51 PM UTC 24 |
| Finished | Oct 14 09:59:43 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667424340 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2667424340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.1555064420 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4906953895657 ps |
| CPU time | 1885.69 seconds |
| Started | Oct 14 09:35:31 PM UTC 24 |
| Finished | Oct 14 10:07:16 PM UTC 24 |
| Peak memory | 200444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555064420 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.1555064420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.3020456117 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 156512594208 ps |
| CPU time | 311.98 seconds |
| Started | Oct 14 09:47:43 PM UTC 24 |
| Finished | Oct 14 09:53:00 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020456117 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3020456117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.3407270820 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 71181567052 ps |
| CPU time | 72.08 seconds |
| Started | Oct 14 09:53:47 PM UTC 24 |
| Finished | Oct 14 09:55:01 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407270820 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3407270820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.407575966 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 157028439323 ps |
| CPU time | 773.8 seconds |
| Started | Oct 14 09:54:33 PM UTC 24 |
| Finished | Oct 14 10:07:36 PM UTC 24 |
| Peak memory | 198800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407575966 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.407575966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.1549503829 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 280599248965 ps |
| CPU time | 366.27 seconds |
| Started | Oct 14 09:54:43 PM UTC 24 |
| Finished | Oct 14 10:00:54 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549503829 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1549503829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1095278983 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1580195749596 ps |
| CPU time | 990.39 seconds |
| Started | Oct 14 09:21:25 PM UTC 24 |
| Finished | Oct 14 09:38:06 PM UTC 24 |
| Peak memory | 200508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095278983 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1095278983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.179565071 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 174391943642 ps |
| CPU time | 495.38 seconds |
| Started | Oct 14 09:55:30 PM UTC 24 |
| Finished | Oct 14 10:03:51 PM UTC 24 |
| Peak memory | 196876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179565071 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.179565071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.363668102 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3027123998051 ps |
| CPU time | 1012.01 seconds |
| Started | Oct 14 09:22:02 PM UTC 24 |
| Finished | Oct 14 09:39:05 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363668102 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.363668102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.378016366 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 329867952693 ps |
| CPU time | 245.47 seconds |
| Started | Oct 14 10:00:56 PM UTC 24 |
| Finished | Oct 14 10:05:05 PM UTC 24 |
| Peak memory | 196884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378016366 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.378016366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.303402789 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 408119949437 ps |
| CPU time | 243.93 seconds |
| Started | Oct 14 10:01:12 PM UTC 24 |
| Finished | Oct 14 10:05:20 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303402789 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.303402789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.2988726366 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1100782645390 ps |
| CPU time | 702.61 seconds |
| Started | Oct 14 09:32:59 PM UTC 24 |
| Finished | Oct 14 09:44:50 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988726366 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.2988726366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.1631892786 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 482384947565 ps |
| CPU time | 320.87 seconds |
| Started | Oct 14 09:38:43 PM UTC 24 |
| Finished | Oct 14 09:44:08 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631892786 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1631892786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.1940270619 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 615752522514 ps |
| CPU time | 1127.39 seconds |
| Started | Oct 14 09:43:02 PM UTC 24 |
| Finished | Oct 14 10:02:02 PM UTC 24 |
| Peak memory | 200368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940270619 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.1940270619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.153044599 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 406107620012 ps |
| CPU time | 700.8 seconds |
| Started | Oct 14 09:43:40 PM UTC 24 |
| Finished | Oct 14 09:55:29 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153044599 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.153044599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3742108200 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 177597105036 ps |
| CPU time | 1252.31 seconds |
| Started | Oct 14 09:44:51 PM UTC 24 |
| Finished | Oct 14 10:05:57 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742108200 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3742108200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.1079995910 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7711811776 ps |
| CPU time | 13.93 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:20:34 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079995910 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1079995910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.1302645634 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 677465150700 ps |
| CPU time | 233.22 seconds |
| Started | Oct 14 09:52:08 PM UTC 24 |
| Finished | Oct 14 09:56:05 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302645634 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1302645634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.1810151201 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 115576963407 ps |
| CPU time | 310.19 seconds |
| Started | Oct 14 09:52:12 PM UTC 24 |
| Finished | Oct 14 09:57:26 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810151201 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1810151201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.845203726 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 966646812508 ps |
| CPU time | 1463.23 seconds |
| Started | Oct 14 09:52:22 PM UTC 24 |
| Finished | Oct 14 10:17:01 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845203726 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.845203726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.2703183727 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 191349967033 ps |
| CPU time | 366.83 seconds |
| Started | Oct 14 09:52:35 PM UTC 24 |
| Finished | Oct 14 09:58:46 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703183727 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2703183727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.324154810 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 171558395975 ps |
| CPU time | 429.26 seconds |
| Started | Oct 14 09:53:12 PM UTC 24 |
| Finished | Oct 14 10:00:26 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324154810 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.324154810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.3554955003 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 495282903436 ps |
| CPU time | 743.41 seconds |
| Started | Oct 14 09:21:23 PM UTC 24 |
| Finished | Oct 14 09:33:55 PM UTC 24 |
| Peak memory | 200504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554955003 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3554955003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1104739194 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 112385725152 ps |
| CPU time | 397.01 seconds |
| Started | Oct 14 09:57:39 PM UTC 24 |
| Finished | Oct 14 10:04:21 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104739194 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1104739194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.1874698991 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2386085835250 ps |
| CPU time | 936.56 seconds |
| Started | Oct 14 09:23:10 PM UTC 24 |
| Finished | Oct 14 09:38:57 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874698991 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.1874698991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.462401877 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 515748991196 ps |
| CPU time | 466.46 seconds |
| Started | Oct 14 10:04:26 PM UTC 24 |
| Finished | Oct 14 10:12:18 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462401877 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.462401877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.904429152 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 421022916859 ps |
| CPU time | 1838.25 seconds |
| Started | Oct 14 10:05:22 PM UTC 24 |
| Finished | Oct 14 10:36:20 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904429152 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.904429152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.1986016235 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 131903588702 ps |
| CPU time | 3234.93 seconds |
| Started | Oct 14 09:24:30 PM UTC 24 |
| Finished | Oct 14 10:18:58 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986016235 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1986016235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.2425423612 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 93935163720 ps |
| CPU time | 130.75 seconds |
| Started | Oct 14 09:25:37 PM UTC 24 |
| Finished | Oct 14 09:27:50 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425423612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2425423612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.421441646 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 94615442780 ps |
| CPU time | 61.87 seconds |
| Started | Oct 14 09:29:22 PM UTC 24 |
| Finished | Oct 14 09:30:25 PM UTC 24 |
| Peak memory | 196740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421441646 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.421441646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.177273524 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 74353132736 ps |
| CPU time | 330.08 seconds |
| Started | Oct 14 09:32:07 PM UTC 24 |
| Finished | Oct 14 09:37:41 PM UTC 24 |
| Peak memory | 196732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177273524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.177273524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.3152369282 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 162531222360 ps |
| CPU time | 341.05 seconds |
| Started | Oct 14 09:32:34 PM UTC 24 |
| Finished | Oct 14 09:38:19 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152369282 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3152369282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.1219765239 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1002066184179 ps |
| CPU time | 549.6 seconds |
| Started | Oct 14 09:33:43 PM UTC 24 |
| Finished | Oct 14 09:42:59 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219765239 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.1219765239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.2214496873 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 154935873638 ps |
| CPU time | 424.56 seconds |
| Started | Oct 14 09:37:42 PM UTC 24 |
| Finished | Oct 14 09:44:52 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214496873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2214496873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.2603713730 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 330233201623 ps |
| CPU time | 174.05 seconds |
| Started | Oct 14 09:38:46 PM UTC 24 |
| Finished | Oct 14 09:41:43 PM UTC 24 |
| Peak memory | 196740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603713730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2603713730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.893987338 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 391144126286 ps |
| CPU time | 179.49 seconds |
| Started | Oct 14 09:45:28 PM UTC 24 |
| Finished | Oct 14 09:48:31 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893987338 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.893987338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.2282665589 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 392476729748 ps |
| CPU time | 237.81 seconds |
| Started | Oct 14 09:49:45 PM UTC 24 |
| Finished | Oct 14 09:53:46 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282665589 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2282665589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.4216135311 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 800587490375 ps |
| CPU time | 2182.84 seconds |
| Started | Oct 14 09:51:06 PM UTC 24 |
| Finished | Oct 14 10:27:53 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216135311 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4216135311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.2610777424 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2775501139813 ps |
| CPU time | 2308.86 seconds |
| Started | Oct 14 09:20:30 PM UTC 24 |
| Finished | Oct 14 09:59:25 PM UTC 24 |
| Peak memory | 200412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610777424 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.2610777424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.4134450363 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3671101256 ps |
| CPU time | 8.1 seconds |
| Started | Oct 14 09:21:09 PM UTC 24 |
| Finished | Oct 14 09:21:19 PM UTC 24 |
| Peak memory | 196680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134450363 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.4134450363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.3518264456 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 92442626705 ps |
| CPU time | 98.99 seconds |
| Started | Oct 14 09:21:13 PM UTC 24 |
| Finished | Oct 14 09:22:54 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518264456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3518264456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.1587120717 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 38576080749 ps |
| CPU time | 200.48 seconds |
| Started | Oct 14 09:56:05 PM UTC 24 |
| Finished | Oct 14 09:59:29 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587120717 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1587120717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.832012299 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 295725690428 ps |
| CPU time | 703.21 seconds |
| Started | Oct 14 09:56:11 PM UTC 24 |
| Finished | Oct 14 10:08:04 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832012299 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.832012299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.2815860760 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 20557377874 ps |
| CPU time | 177.84 seconds |
| Started | Oct 14 09:56:38 PM UTC 24 |
| Finished | Oct 14 09:59:38 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815860760 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2815860760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.749800438 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 24407251359 ps |
| CPU time | 29.93 seconds |
| Started | Oct 14 09:22:04 PM UTC 24 |
| Finished | Oct 14 09:22:35 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749800438 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.749800438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2828777724 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1659242348195 ps |
| CPU time | 765.53 seconds |
| Started | Oct 14 09:59:36 PM UTC 24 |
| Finished | Oct 14 10:12:31 PM UTC 24 |
| Peak memory | 200504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828777724 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2828777724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.2584438895 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 51009547648 ps |
| CPU time | 430.43 seconds |
| Started | Oct 14 10:00:34 PM UTC 24 |
| Finished | Oct 14 10:07:50 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584438895 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2584438895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.2847547931 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 324644531279 ps |
| CPU time | 231.33 seconds |
| Started | Oct 14 10:00:45 PM UTC 24 |
| Finished | Oct 14 10:04:40 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847547931 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2847547931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.43451780 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 805051296386 ps |
| CPU time | 392.25 seconds |
| Started | Oct 14 10:02:03 PM UTC 24 |
| Finished | Oct 14 10:08:40 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43451780 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.43451780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.3515969650 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 377203976685 ps |
| CPU time | 2508.67 seconds |
| Started | Oct 14 10:02:48 PM UTC 24 |
| Finished | Oct 14 10:45:04 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515969650 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3515969650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.545582183 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 463860846370 ps |
| CPU time | 916.97 seconds |
| Started | Oct 14 09:24:17 PM UTC 24 |
| Finished | Oct 14 09:39:44 PM UTC 24 |
| Peak memory | 200420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545582183 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.545582183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3183547825 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 42237997588 ps |
| CPU time | 52.84 seconds |
| Started | Oct 14 09:24:55 PM UTC 24 |
| Finished | Oct 14 09:25:50 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183547825 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3183547825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.3003163623 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1890219197124 ps |
| CPU time | 442.82 seconds |
| Started | Oct 14 09:25:30 PM UTC 24 |
| Finished | Oct 14 09:32:58 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003163623 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3003163623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.1619281076 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 128894348732 ps |
| CPU time | 198.19 seconds |
| Started | Oct 14 09:27:12 PM UTC 24 |
| Finished | Oct 14 09:30:34 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619281076 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1619281076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.3909197997 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 249569419577 ps |
| CPU time | 393.77 seconds |
| Started | Oct 14 09:29:57 PM UTC 24 |
| Finished | Oct 14 09:36:37 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909197997 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3909197997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.1357953892 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2660848106280 ps |
| CPU time | 1093.96 seconds |
| Started | Oct 14 09:33:24 PM UTC 24 |
| Finished | Oct 14 09:51:48 PM UTC 24 |
| Peak memory | 200416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357953892 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.1357953892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.281032669 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 786684347729 ps |
| CPU time | 681.46 seconds |
| Started | Oct 14 09:35:22 PM UTC 24 |
| Finished | Oct 14 09:46:52 PM UTC 24 |
| Peak memory | 196816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281032669 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.281032669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.621565706 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 208708518069 ps |
| CPU time | 700.01 seconds |
| Started | Oct 14 09:36:15 PM UTC 24 |
| Finished | Oct 14 09:48:03 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621565706 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.621565706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.3747761248 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5432482087 ps |
| CPU time | 15.23 seconds |
| Started | Oct 14 09:39:54 PM UTC 24 |
| Finished | Oct 14 09:40:11 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747761248 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.3747761248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.3326408869 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2028370843756 ps |
| CPU time | 435.39 seconds |
| Started | Oct 14 09:21:01 PM UTC 24 |
| Finished | Oct 14 09:28:21 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326408869 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.3326408869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3467399552 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 156631819 ps |
| CPU time | 1.17 seconds |
| Started | Oct 14 10:05:52 PM UTC 24 |
| Finished | Oct 14 10:05:54 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467399552 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.3467399552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1434999566 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1659347070 ps |
| CPU time | 5.62 seconds |
| Started | Oct 14 10:05:49 PM UTC 24 |
| Finished | Oct 14 10:05:56 PM UTC 24 |
| Peak memory | 200888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434999566 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.1434999566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2435689898 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 33293130 ps |
| CPU time | 1.19 seconds |
| Started | Oct 14 10:05:55 PM UTC 24 |
| Finished | Oct 14 10:05:57 PM UTC 24 |
| Peak memory | 199248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2435689898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.2435689898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.3887930515 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 15224383 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 10:05:49 PM UTC 24 |
| Finished | Oct 14 10:05:51 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887930515 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3887930515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.1632281039 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 56512813 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 10:05:43 PM UTC 24 |
| Finished | Oct 14 10:05:44 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632281039 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1632281039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2792616614 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 33262840 ps |
| CPU time | 1.08 seconds |
| Started | Oct 14 10:05:53 PM UTC 24 |
| Finished | Oct 14 10:05:55 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792616614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.2792616614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.648397904 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 159963318 ps |
| CPU time | 3.94 seconds |
| Started | Oct 14 10:05:34 PM UTC 24 |
| Finished | Oct 14 10:05:38 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648397904 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.648397904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1799089343 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 83560346 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 10:05:40 PM UTC 24 |
| Finished | Oct 14 10:05:42 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799089343 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.1799089343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.321201052 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 256903404 ps |
| CPU time | 0.99 seconds |
| Started | Oct 14 10:06:01 PM UTC 24 |
| Finished | Oct 14 10:06:03 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321201052 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.321201052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.446922524 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1140917622 ps |
| CPU time | 4.81 seconds |
| Started | Oct 14 10:06:00 PM UTC 24 |
| Finished | Oct 14 10:06:05 PM UTC 24 |
| Peak memory | 200956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446922524 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.446922524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3861152711 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 233999040 ps |
| CPU time | 0.87 seconds |
| Started | Oct 14 10:05:58 PM UTC 24 |
| Finished | Oct 14 10:06:00 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861152711 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.3861152711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3842960562 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 74261231 ps |
| CPU time | 1.05 seconds |
| Started | Oct 14 10:06:02 PM UTC 24 |
| Finished | Oct 14 10:06:04 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3842960562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.3842960562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1095701744 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 41070397 ps |
| CPU time | 0.9 seconds |
| Started | Oct 14 10:06:00 PM UTC 24 |
| Finished | Oct 14 10:06:01 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095701744 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1095701744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.3874765343 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 24121376 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:05:57 PM UTC 24 |
| Finished | Oct 14 10:05:59 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874765343 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3874765343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4136410694 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 169755575 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 10:06:01 PM UTC 24 |
| Finished | Oct 14 10:06:03 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136410694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.4136410694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.3966632324 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 748571358 ps |
| CPU time | 1.88 seconds |
| Started | Oct 14 10:05:56 PM UTC 24 |
| Finished | Oct 14 10:05:59 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966632324 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3966632324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4204355418 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 20449725 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 10:06:33 PM UTC 24 |
| Finished | Oct 14 10:06:36 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4204355418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.4204355418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.725097872 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 12993656 ps |
| CPU time | 0.79 seconds |
| Started | Oct 14 10:06:32 PM UTC 24 |
| Finished | Oct 14 10:06:34 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725097872 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.725097872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.865800712 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 47604685 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:32 PM UTC 24 |
| Finished | Oct 14 10:06:34 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865800712 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.865800712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4011598619 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 68735983 ps |
| CPU time | 1.12 seconds |
| Started | Oct 14 10:06:32 PM UTC 24 |
| Finished | Oct 14 10:06:34 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011598619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.4011598619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.1244125901 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 435850948 ps |
| CPU time | 3.48 seconds |
| Started | Oct 14 10:06:31 PM UTC 24 |
| Finished | Oct 14 10:06:36 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244125901 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1244125901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2563760413 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 132942610 ps |
| CPU time | 0.99 seconds |
| Started | Oct 14 10:06:32 PM UTC 24 |
| Finished | Oct 14 10:06:34 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563760413 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.2563760413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4034355487 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 50039477 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 10:06:35 PM UTC 24 |
| Finished | Oct 14 10:06:37 PM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4034355487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.4034355487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.1242857425 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 44402004 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 10:06:34 PM UTC 24 |
| Finished | Oct 14 10:06:36 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242857425 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1242857425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.799896441 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 21755746 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:33 PM UTC 24 |
| Finished | Oct 14 10:06:35 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799896441 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.799896441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.942041485 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 80412593 ps |
| CPU time | 1.12 seconds |
| Started | Oct 14 10:06:35 PM UTC 24 |
| Finished | Oct 14 10:06:37 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942041485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.942041485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.145679207 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 424675997 ps |
| CPU time | 3.2 seconds |
| Started | Oct 14 10:06:33 PM UTC 24 |
| Finished | Oct 14 10:06:38 PM UTC 24 |
| Peak memory | 203328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145679207 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.145679207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4019242267 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1456036873 ps |
| CPU time | 2.03 seconds |
| Started | Oct 14 10:06:33 PM UTC 24 |
| Finished | Oct 14 10:06:36 PM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019242267 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.4019242267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3587790649 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 79552279 ps |
| CPU time | 1.44 seconds |
| Started | Oct 14 10:06:37 PM UTC 24 |
| Finished | Oct 14 10:06:40 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3587790649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.3587790649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3534176155 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 14506157 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:37 PM UTC 24 |
| Finished | Oct 14 10:06:39 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534176155 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3534176155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.969202158 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 14173569 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 10:06:36 PM UTC 24 |
| Finished | Oct 14 10:06:38 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969202158 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.969202158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2853028436 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 39138199 ps |
| CPU time | 0.85 seconds |
| Started | Oct 14 10:06:37 PM UTC 24 |
| Finished | Oct 14 10:06:40 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853028436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.2853028436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3107010044 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 52660611 ps |
| CPU time | 1.4 seconds |
| Started | Oct 14 10:06:35 PM UTC 24 |
| Finished | Oct 14 10:06:37 PM UTC 24 |
| Peak memory | 199364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107010044 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3107010044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1575003980 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 105991558 ps |
| CPU time | 2.01 seconds |
| Started | Oct 14 10:06:36 PM UTC 24 |
| Finished | Oct 14 10:06:39 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575003980 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.1575003980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4104932817 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 51433254 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 10:06:39 PM UTC 24 |
| Finished | Oct 14 10:06:42 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4104932817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.4104932817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.3051813117 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 192527455 ps |
| CPU time | 0.84 seconds |
| Started | Oct 14 10:06:39 PM UTC 24 |
| Finished | Oct 14 10:06:41 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051813117 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3051813117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2303303621 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 30090650 ps |
| CPU time | 0.75 seconds |
| Started | Oct 14 10:06:39 PM UTC 24 |
| Finished | Oct 14 10:06:41 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303303621 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2303303621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1405346564 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 18258851 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:39 PM UTC 24 |
| Finished | Oct 14 10:06:41 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405346564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.1405346564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.2577115100 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 176523260 ps |
| CPU time | 1.64 seconds |
| Started | Oct 14 10:06:37 PM UTC 24 |
| Finished | Oct 14 10:06:40 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577115100 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2577115100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.282976109 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 137515996 ps |
| CPU time | 1.09 seconds |
| Started | Oct 14 10:06:37 PM UTC 24 |
| Finished | Oct 14 10:06:40 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282976109 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.282976109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.156341792 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 57015386 ps |
| CPU time | 1.48 seconds |
| Started | Oct 14 10:06:42 PM UTC 24 |
| Finished | Oct 14 10:06:45 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=156341792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_cs r_mem_rw_with_rand_reset.156341792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3478087946 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 35355493 ps |
| CPU time | 0.76 seconds |
| Started | Oct 14 10:06:41 PM UTC 24 |
| Finished | Oct 14 10:06:42 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478087946 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3478087946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1760646139 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 59481417 ps |
| CPU time | 0.81 seconds |
| Started | Oct 14 10:06:40 PM UTC 24 |
| Finished | Oct 14 10:06:42 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760646139 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1760646139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2300381037 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 111675450 ps |
| CPU time | 1.17 seconds |
| Started | Oct 14 10:06:42 PM UTC 24 |
| Finished | Oct 14 10:06:44 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300381037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.2300381037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.1998195058 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 27902164 ps |
| CPU time | 1.95 seconds |
| Started | Oct 14 10:06:40 PM UTC 24 |
| Finished | Oct 14 10:06:44 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998195058 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1998195058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1384426129 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 54169679 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 10:06:40 PM UTC 24 |
| Finished | Oct 14 10:06:43 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384426129 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.1384426129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3095127599 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 310639004 ps |
| CPU time | 1.01 seconds |
| Started | Oct 14 10:06:44 PM UTC 24 |
| Finished | Oct 14 10:06:46 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3095127599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.3095127599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3193815790 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 21990618 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:42 PM UTC 24 |
| Finished | Oct 14 10:06:44 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193815790 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3193815790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.3766733286 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 48878193 ps |
| CPU time | 0.72 seconds |
| Started | Oct 14 10:06:42 PM UTC 24 |
| Finished | Oct 14 10:06:44 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766733286 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3766733286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2499444634 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 19814327 ps |
| CPU time | 0.77 seconds |
| Started | Oct 14 10:06:42 PM UTC 24 |
| Finished | Oct 14 10:06:44 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499444634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.2499444634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.564390559 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 151937606 ps |
| CPU time | 4.31 seconds |
| Started | Oct 14 10:06:42 PM UTC 24 |
| Finished | Oct 14 10:06:48 PM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564390559 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.564390559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3752377221 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 152137557 ps |
| CPU time | 1.22 seconds |
| Started | Oct 14 10:06:42 PM UTC 24 |
| Finished | Oct 14 10:06:45 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752377221 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3752377221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1684648245 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 25454044 ps |
| CPU time | 1.57 seconds |
| Started | Oct 14 10:06:45 PM UTC 24 |
| Finished | Oct 14 10:06:48 PM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1684648245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c sr_mem_rw_with_rand_reset.1684648245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.2192628792 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 54226271 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 10:06:45 PM UTC 24 |
| Finished | Oct 14 10:06:47 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192628792 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2192628792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1920898629 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 49495393 ps |
| CPU time | 0.85 seconds |
| Started | Oct 14 10:06:44 PM UTC 24 |
| Finished | Oct 14 10:06:46 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920898629 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1920898629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3628928201 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 29857970 ps |
| CPU time | 0.9 seconds |
| Started | Oct 14 10:06:45 PM UTC 24 |
| Finished | Oct 14 10:06:47 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628928201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.3628928201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1908232943 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 663606357 ps |
| CPU time | 4.3 seconds |
| Started | Oct 14 10:06:44 PM UTC 24 |
| Finished | Oct 14 10:06:49 PM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908232943 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1908232943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3717367559 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 134478270 ps |
| CPU time | 1.99 seconds |
| Started | Oct 14 10:06:44 PM UTC 24 |
| Finished | Oct 14 10:06:47 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717367559 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.3717367559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3557614397 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 100728370 ps |
| CPU time | 1.94 seconds |
| Started | Oct 14 10:06:47 PM UTC 24 |
| Finished | Oct 14 10:06:50 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3557614397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.3557614397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1780942153 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 53276825 ps |
| CPU time | 0.85 seconds |
| Started | Oct 14 10:06:47 PM UTC 24 |
| Finished | Oct 14 10:06:49 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780942153 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1780942153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3732045189 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 65985105 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 10:06:46 PM UTC 24 |
| Finished | Oct 14 10:06:47 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732045189 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3732045189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2821245743 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 107081636 ps |
| CPU time | 0.91 seconds |
| Started | Oct 14 10:06:47 PM UTC 24 |
| Finished | Oct 14 10:06:49 PM UTC 24 |
| Peak memory | 198916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821245743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.2821245743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2133802873 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 133213002 ps |
| CPU time | 2.03 seconds |
| Started | Oct 14 10:06:46 PM UTC 24 |
| Finished | Oct 14 10:06:48 PM UTC 24 |
| Peak memory | 201224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133802873 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2133802873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1856455558 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 311825090 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 10:06:46 PM UTC 24 |
| Finished | Oct 14 10:06:48 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856455558 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.1856455558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1461407227 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 21116639 ps |
| CPU time | 1.3 seconds |
| Started | Oct 14 10:06:49 PM UTC 24 |
| Finished | Oct 14 10:06:51 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1461407227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.1461407227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.2739947760 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 36546503 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:49 PM UTC 24 |
| Finished | Oct 14 10:06:51 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739947760 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2739947760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1051113812 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 33177610 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:49 PM UTC 24 |
| Finished | Oct 14 10:06:51 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051113812 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1051113812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3002525957 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 136854214 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 10:06:49 PM UTC 24 |
| Finished | Oct 14 10:06:51 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002525957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.3002525957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.4148727348 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 241083216 ps |
| CPU time | 3.69 seconds |
| Started | Oct 14 10:06:49 PM UTC 24 |
| Finished | Oct 14 10:06:53 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148727348 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4148727348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3212492077 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 62426657 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 10:06:49 PM UTC 24 |
| Finished | Oct 14 10:06:51 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212492077 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.3212492077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2271566244 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 27916423 ps |
| CPU time | 1.51 seconds |
| Started | Oct 14 10:06:51 PM UTC 24 |
| Finished | Oct 14 10:06:53 PM UTC 24 |
| Peak memory | 201160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2271566244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.2271566244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.3734554978 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 14081951 ps |
| CPU time | 0.89 seconds |
| Started | Oct 14 10:06:51 PM UTC 24 |
| Finished | Oct 14 10:06:52 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734554978 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3734554978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1608859221 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 16134986 ps |
| CPU time | 0.87 seconds |
| Started | Oct 14 10:06:51 PM UTC 24 |
| Finished | Oct 14 10:06:52 PM UTC 24 |
| Peak memory | 199072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608859221 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1608859221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4033795403 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 24206654 ps |
| CPU time | 1.04 seconds |
| Started | Oct 14 10:06:51 PM UTC 24 |
| Finished | Oct 14 10:06:53 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033795403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.4033795403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.3190728593 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 469966604 ps |
| CPU time | 3.1 seconds |
| Started | Oct 14 10:06:49 PM UTC 24 |
| Finished | Oct 14 10:06:53 PM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190728593 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3190728593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1133347504 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 110523401 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 10:06:50 PM UTC 24 |
| Finished | Oct 14 10:06:53 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133347504 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.1133347504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3349607467 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 18439437 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 10:06:07 PM UTC 24 |
| Finished | Oct 14 10:06:10 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349607467 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.3349607467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.851561657 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 377314027 ps |
| CPU time | 2.21 seconds |
| Started | Oct 14 10:06:07 PM UTC 24 |
| Finished | Oct 14 10:06:11 PM UTC 24 |
| Peak memory | 200872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851561657 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.851561657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1793920062 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 15344670 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:06 PM UTC 24 |
| Finished | Oct 14 10:06:08 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793920062 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.1793920062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2164533838 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 102956386 ps |
| CPU time | 1.22 seconds |
| Started | Oct 14 10:06:09 PM UTC 24 |
| Finished | Oct 14 10:06:11 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2164533838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.2164533838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.742562573 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 17991081 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:07 PM UTC 24 |
| Finished | Oct 14 10:06:09 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742562573 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.742562573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.1385174493 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 36705887 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 10:06:05 PM UTC 24 |
| Finished | Oct 14 10:06:07 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385174493 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1385174493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1364758551 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 25998293 ps |
| CPU time | 1.01 seconds |
| Started | Oct 14 10:06:07 PM UTC 24 |
| Finished | Oct 14 10:06:10 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364758551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.1364758551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.4202240213 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 22244732 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 10:06:04 PM UTC 24 |
| Finished | Oct 14 10:06:06 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202240213 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4202240213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3043821224 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 222880907 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 10:06:04 PM UTC 24 |
| Finished | Oct 14 10:06:06 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043821224 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.3043821224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4057306339 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 39595685 ps |
| CPU time | 0.85 seconds |
| Started | Oct 14 10:06:52 PM UTC 24 |
| Finished | Oct 14 10:06:54 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057306339 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4057306339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.827172201 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 17227069 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:52 PM UTC 24 |
| Finished | Oct 14 10:06:54 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827172201 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.827172201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2310209285 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 14577765 ps |
| CPU time | 0.81 seconds |
| Started | Oct 14 10:06:52 PM UTC 24 |
| Finished | Oct 14 10:06:54 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310209285 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2310209285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.1995083197 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 20294201 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:52 PM UTC 24 |
| Finished | Oct 14 10:06:54 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995083197 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1995083197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1194907664 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 14984919 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 10:06:52 PM UTC 24 |
| Finished | Oct 14 10:06:54 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194907664 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1194907664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3413926998 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 14037407 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 10:06:54 PM UTC 24 |
| Finished | Oct 14 10:06:56 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413926998 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3413926998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.1939384885 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 14281178 ps |
| CPU time | 0.84 seconds |
| Started | Oct 14 10:06:54 PM UTC 24 |
| Finished | Oct 14 10:06:56 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939384885 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1939384885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.4053161713 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 11596049 ps |
| CPU time | 0.81 seconds |
| Started | Oct 14 10:06:54 PM UTC 24 |
| Finished | Oct 14 10:06:56 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053161713 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.4053161713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.2767661237 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 33793099 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767661237 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2767661237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3034769706 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 34236657 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034769706 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3034769706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2152824524 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 30385654 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 10:06:13 PM UTC 24 |
| Finished | Oct 14 10:06:15 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152824524 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.2152824524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4245529313 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 389435439 ps |
| CPU time | 2.23 seconds |
| Started | Oct 14 10:06:13 PM UTC 24 |
| Finished | Oct 14 10:06:16 PM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245529313 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.4245529313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2500179728 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 35659620 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:12 PM UTC 24 |
| Finished | Oct 14 10:06:14 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500179728 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2500179728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2007552214 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 28068091 ps |
| CPU time | 1.67 seconds |
| Started | Oct 14 10:06:14 PM UTC 24 |
| Finished | Oct 14 10:06:17 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2007552214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.2007552214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.3125977215 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 33974300 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 10:06:12 PM UTC 24 |
| Finished | Oct 14 10:06:14 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125977215 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3125977215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3675177426 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 37961887 ps |
| CPU time | 0.81 seconds |
| Started | Oct 14 10:06:11 PM UTC 24 |
| Finished | Oct 14 10:06:13 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675177426 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3675177426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2975154029 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 84572052 ps |
| CPU time | 1.15 seconds |
| Started | Oct 14 10:06:14 PM UTC 24 |
| Finished | Oct 14 10:06:17 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975154029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.2975154029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.1062334755 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 144077719 ps |
| CPU time | 2.22 seconds |
| Started | Oct 14 10:06:10 PM UTC 24 |
| Finished | Oct 14 10:06:13 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062334755 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1062334755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2216749831 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1331783541 ps |
| CPU time | 2.05 seconds |
| Started | Oct 14 10:06:11 PM UTC 24 |
| Finished | Oct 14 10:06:14 PM UTC 24 |
| Peak memory | 201204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216749831 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.2216749831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1098734147 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 13557881 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098734147 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1098734147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.94533290 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 29380572 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94533290 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.94533290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.70413759 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 13707931 ps |
| CPU time | 0.72 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70413759 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.70413759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.4093059379 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 38748894 ps |
| CPU time | 0.85 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093059379 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4093059379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.4133998127 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 13891692 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133998127 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4133998127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.748151574 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 36831580 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748151574 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.748151574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.1103401101 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 23988792 ps |
| CPU time | 0.8 seconds |
| Started | Oct 14 10:06:56 PM UTC 24 |
| Finished | Oct 14 10:06:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103401101 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1103401101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1217535048 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 29400138 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 10:06:57 PM UTC 24 |
| Finished | Oct 14 10:07:00 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217535048 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1217535048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.4272940530 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 13320533 ps |
| CPU time | 0.87 seconds |
| Started | Oct 14 10:06:57 PM UTC 24 |
| Finished | Oct 14 10:07:00 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272940530 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4272940530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3082567319 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 13941581 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:57 PM UTC 24 |
| Finished | Oct 14 10:07:00 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082567319 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3082567319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1784563084 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 72890401 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 10:06:18 PM UTC 24 |
| Finished | Oct 14 10:06:20 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784563084 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.1784563084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2704920958 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 392452814 ps |
| CPU time | 2.24 seconds |
| Started | Oct 14 10:06:18 PM UTC 24 |
| Finished | Oct 14 10:06:21 PM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704920958 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.2704920958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.390242555 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 60437706 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:18 PM UTC 24 |
| Finished | Oct 14 10:06:20 PM UTC 24 |
| Peak memory | 199168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390242555 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.390242555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4180074396 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 55417275 ps |
| CPU time | 0.94 seconds |
| Started | Oct 14 10:06:18 PM UTC 24 |
| Finished | Oct 14 10:06:20 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4180074396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.4180074396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.2279138613 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 24227281 ps |
| CPU time | 0.84 seconds |
| Started | Oct 14 10:06:18 PM UTC 24 |
| Finished | Oct 14 10:06:20 PM UTC 24 |
| Peak memory | 199360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279138613 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2279138613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.3200214907 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 15134931 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 10:06:16 PM UTC 24 |
| Finished | Oct 14 10:06:17 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200214907 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3200214907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3022457525 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 86530134 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 10:06:18 PM UTC 24 |
| Finished | Oct 14 10:06:20 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022457525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.3022457525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.3434461344 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 93983249 ps |
| CPU time | 2.4 seconds |
| Started | Oct 14 10:06:14 PM UTC 24 |
| Finished | Oct 14 10:06:18 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434461344 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3434461344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2137848116 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 143308047 ps |
| CPU time | 1 seconds |
| Started | Oct 14 10:06:15 PM UTC 24 |
| Finished | Oct 14 10:06:17 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137848116 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.2137848116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.1079274346 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 42074994 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:59 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079274346 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1079274346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.2557698646 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 57776381 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:59 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557698646 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2557698646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2548022301 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 19610420 ps |
| CPU time | 0.88 seconds |
| Started | Oct 14 10:06:59 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548022301 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2548022301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2235186220 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 18006509 ps |
| CPU time | 0.89 seconds |
| Started | Oct 14 10:06:59 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235186220 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2235186220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.3384263787 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 66174717 ps |
| CPU time | 0.87 seconds |
| Started | Oct 14 10:06:59 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384263787 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3384263787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1852209101 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 30547617 ps |
| CPU time | 0.84 seconds |
| Started | Oct 14 10:06:59 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852209101 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1852209101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1987863316 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 15014244 ps |
| CPU time | 0.87 seconds |
| Started | Oct 14 10:06:59 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987863316 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1987863316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3026669454 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 12748328 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:07:00 PM UTC 24 |
| Finished | Oct 14 10:07:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026669454 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3026669454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.2553231017 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 42942666 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:07:00 PM UTC 24 |
| Finished | Oct 14 10:07:02 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553231017 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2553231017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.345841611 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 32846945 ps |
| CPU time | 0.81 seconds |
| Started | Oct 14 10:07:01 PM UTC 24 |
| Finished | Oct 14 10:07:03 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345841611 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.345841611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2297805191 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 27854160 ps |
| CPU time | 2.01 seconds |
| Started | Oct 14 10:06:22 PM UTC 24 |
| Finished | Oct 14 10:06:25 PM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2297805191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.2297805191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.1286521352 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 27225122 ps |
| CPU time | 0.72 seconds |
| Started | Oct 14 10:06:20 PM UTC 24 |
| Finished | Oct 14 10:06:22 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286521352 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1286521352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.245047382 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 48598219 ps |
| CPU time | 0.92 seconds |
| Started | Oct 14 10:06:22 PM UTC 24 |
| Finished | Oct 14 10:06:24 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245047382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.245047382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.2347079305 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 42519670 ps |
| CPU time | 2.01 seconds |
| Started | Oct 14 10:06:19 PM UTC 24 |
| Finished | Oct 14 10:06:22 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347079305 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2347079305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1978676037 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 606397296 ps |
| CPU time | 2.06 seconds |
| Started | Oct 14 10:06:20 PM UTC 24 |
| Finished | Oct 14 10:06:23 PM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978676037 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.1978676037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.751630297 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 25207869 ps |
| CPU time | 1.55 seconds |
| Started | Oct 14 10:06:24 PM UTC 24 |
| Finished | Oct 14 10:06:27 PM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=751630297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr _mem_rw_with_rand_reset.751630297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.406464712 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 35014205 ps |
| CPU time | 0.81 seconds |
| Started | Oct 14 10:06:23 PM UTC 24 |
| Finished | Oct 14 10:06:25 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406464712 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.406464712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.1528488234 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 24226055 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 10:06:23 PM UTC 24 |
| Finished | Oct 14 10:06:25 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528488234 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1528488234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2124361667 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 33175532 ps |
| CPU time | 1.06 seconds |
| Started | Oct 14 10:06:24 PM UTC 24 |
| Finished | Oct 14 10:06:26 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124361667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.2124361667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.3888813574 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 173508768 ps |
| CPU time | 3.31 seconds |
| Started | Oct 14 10:06:22 PM UTC 24 |
| Finished | Oct 14 10:06:26 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888813574 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3888813574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.498741075 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 760770210 ps |
| CPU time | 1.38 seconds |
| Started | Oct 14 10:06:22 PM UTC 24 |
| Finished | Oct 14 10:06:24 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498741075 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.498741075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2962532221 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 16144974 ps |
| CPU time | 1.1 seconds |
| Started | Oct 14 10:06:26 PM UTC 24 |
| Finished | Oct 14 10:06:28 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2962532221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.2962532221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.2124646055 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 34363703 ps |
| CPU time | 0.89 seconds |
| Started | Oct 14 10:06:26 PM UTC 24 |
| Finished | Oct 14 10:06:28 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124646055 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2124646055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.3797568253 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 55545852 ps |
| CPU time | 0.85 seconds |
| Started | Oct 14 10:06:26 PM UTC 24 |
| Finished | Oct 14 10:06:27 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797568253 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3797568253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2283797331 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 48567901 ps |
| CPU time | 0.93 seconds |
| Started | Oct 14 10:06:26 PM UTC 24 |
| Finished | Oct 14 10:06:28 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283797331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.2283797331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.1213180929 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 325265902 ps |
| CPU time | 3 seconds |
| Started | Oct 14 10:06:24 PM UTC 24 |
| Finished | Oct 14 10:06:28 PM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213180929 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1213180929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1832302180 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 58397534 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 10:06:26 PM UTC 24 |
| Finished | Oct 14 10:06:28 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832302180 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.1832302180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3429630160 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 89657080 ps |
| CPU time | 1.17 seconds |
| Started | Oct 14 10:06:29 PM UTC 24 |
| Finished | Oct 14 10:06:31 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3429630160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.3429630160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.540670325 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 20155000 ps |
| CPU time | 0.86 seconds |
| Started | Oct 14 10:06:29 PM UTC 24 |
| Finished | Oct 14 10:06:31 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540670325 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.540670325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.1834167283 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 21977200 ps |
| CPU time | 0.83 seconds |
| Started | Oct 14 10:06:28 PM UTC 24 |
| Finished | Oct 14 10:06:30 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834167283 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1834167283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1433666301 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 18312629 ps |
| CPU time | 0.92 seconds |
| Started | Oct 14 10:06:29 PM UTC 24 |
| Finished | Oct 14 10:06:31 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433666301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.1433666301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1958679853 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 82872081 ps |
| CPU time | 2.39 seconds |
| Started | Oct 14 10:06:27 PM UTC 24 |
| Finished | Oct 14 10:06:31 PM UTC 24 |
| Peak memory | 203116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958679853 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1958679853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2251324912 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 43340106 ps |
| CPU time | 1.24 seconds |
| Started | Oct 14 10:06:27 PM UTC 24 |
| Finished | Oct 14 10:06:30 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251324912 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.2251324912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.20981058 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 29095173 ps |
| CPU time | 1.9 seconds |
| Started | Oct 14 10:06:31 PM UTC 24 |
| Finished | Oct 14 10:06:35 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=20981058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_ mem_rw_with_rand_reset.20981058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.2672802038 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 25483244 ps |
| CPU time | 0.82 seconds |
| Started | Oct 14 10:06:30 PM UTC 24 |
| Finished | Oct 14 10:06:32 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672802038 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2672802038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.982652488 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 14455033 ps |
| CPU time | 0.81 seconds |
| Started | Oct 14 10:06:30 PM UTC 24 |
| Finished | Oct 14 10:06:32 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982652488 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.982652488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2968087036 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 32793040 ps |
| CPU time | 1.01 seconds |
| Started | Oct 14 10:06:30 PM UTC 24 |
| Finished | Oct 14 10:06:32 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968087036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.2968087036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.1094422827 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 42851115 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 10:06:29 PM UTC 24 |
| Finished | Oct 14 10:06:31 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094422827 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1094422827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3913289613 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 47640067 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 10:06:29 PM UTC 24 |
| Finished | Oct 14 10:06:31 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913289613 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.3913289613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.3687107956 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 265222705430 ps |
| CPU time | 232.15 seconds |
| Started | Oct 14 09:20:21 PM UTC 24 |
| Finished | Oct 14 09:24:17 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687107956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3687107956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.20100185 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 84779496993 ps |
| CPU time | 61.46 seconds |
| Started | Oct 14 09:20:21 PM UTC 24 |
| Finished | Oct 14 09:21:25 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20100185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.20100185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.1736099377 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 410082367037 ps |
| CPU time | 130.53 seconds |
| Started | Oct 14 09:20:25 PM UTC 24 |
| Finished | Oct 14 09:22:38 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736099377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1736099377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.1479871456 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 47134833170 ps |
| CPU time | 107.7 seconds |
| Started | Oct 14 09:20:25 PM UTC 24 |
| Finished | Oct 14 09:22:15 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479871456 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1479871456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3813959118 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 122509886596 ps |
| CPU time | 153.48 seconds |
| Started | Oct 14 09:20:25 PM UTC 24 |
| Finished | Oct 14 09:23:01 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813959118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3813959118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.690602587 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 171579627 ps |
| CPU time | 1.23 seconds |
| Started | Oct 14 09:20:30 PM UTC 24 |
| Finished | Oct 14 09:20:32 PM UTC 24 |
| Peak memory | 226072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690602587 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.690602587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.2210165870 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 663872861177 ps |
| CPU time | 263.31 seconds |
| Started | Oct 14 09:21:09 PM UTC 24 |
| Finished | Oct 14 09:25:36 PM UTC 24 |
| Peak memory | 196936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210165870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2210165870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.3249763579 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 72842077841 ps |
| CPU time | 1685.49 seconds |
| Started | Oct 14 09:21:09 PM UTC 24 |
| Finished | Oct 14 09:49:32 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249763579 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3249763579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.537471871 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 123846563202 ps |
| CPU time | 204.62 seconds |
| Started | Oct 14 09:21:16 PM UTC 24 |
| Finished | Oct 14 09:24:43 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537471871 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.537471871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.2430082853 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 462799872037 ps |
| CPU time | 141.64 seconds |
| Started | Oct 14 09:52:20 PM UTC 24 |
| Finished | Oct 14 09:54:44 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430082853 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2430082853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.1414904039 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 318050922604 ps |
| CPU time | 551.64 seconds |
| Started | Oct 14 09:53:00 PM UTC 24 |
| Finished | Oct 14 10:02:19 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414904039 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1414904039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.2866594438 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 75223045342 ps |
| CPU time | 151.36 seconds |
| Started | Oct 14 09:53:10 PM UTC 24 |
| Finished | Oct 14 09:55:43 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866594438 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2866594438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.1259857362 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8721224607 ps |
| CPU time | 13.89 seconds |
| Started | Oct 14 09:21:19 PM UTC 24 |
| Finished | Oct 14 09:21:34 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259857362 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.1259857362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.477586661 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 68985645526 ps |
| CPU time | 103.28 seconds |
| Started | Oct 14 09:21:17 PM UTC 24 |
| Finished | Oct 14 09:23:02 PM UTC 24 |
| Peak memory | 196888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477586661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.477586661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.35105979 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 95451420328 ps |
| CPU time | 254.8 seconds |
| Started | Oct 14 09:21:17 PM UTC 24 |
| Finished | Oct 14 09:25:36 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35105979 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.35105979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.662259896 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 66249940450 ps |
| CPU time | 127.19 seconds |
| Started | Oct 14 09:21:19 PM UTC 24 |
| Finished | Oct 14 09:23:29 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662259896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.662259896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.2182457996 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 632628805101 ps |
| CPU time | 1827.2 seconds |
| Started | Oct 14 09:21:23 PM UTC 24 |
| Finished | Oct 14 09:52:07 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182457996 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.2182457996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.3688196343 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 161771677612 ps |
| CPU time | 82.53 seconds |
| Started | Oct 14 09:53:49 PM UTC 24 |
| Finished | Oct 14 09:55:13 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688196343 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3688196343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.1162359098 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 124153969882 ps |
| CPU time | 344.83 seconds |
| Started | Oct 14 09:54:09 PM UTC 24 |
| Finished | Oct 14 09:59:59 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162359098 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1162359098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.4034741891 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 137581615329 ps |
| CPU time | 341.43 seconds |
| Started | Oct 14 09:54:22 PM UTC 24 |
| Finished | Oct 14 10:00:08 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034741891 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.4034741891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.2752166713 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 52602158301 ps |
| CPU time | 103.67 seconds |
| Started | Oct 14 09:54:45 PM UTC 24 |
| Finished | Oct 14 09:56:30 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752166713 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2752166713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.3256228324 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 38676477769 ps |
| CPU time | 105.74 seconds |
| Started | Oct 14 09:55:02 PM UTC 24 |
| Finished | Oct 14 09:56:50 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256228324 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3256228324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.1004606837 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 67891252574 ps |
| CPU time | 61.06 seconds |
| Started | Oct 14 09:55:08 PM UTC 24 |
| Finished | Oct 14 09:56:11 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004606837 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1004606837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.4226681831 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 147329343371 ps |
| CPU time | 192.48 seconds |
| Started | Oct 14 09:21:25 PM UTC 24 |
| Finished | Oct 14 09:24:40 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226681831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4226681831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.4135112749 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 149893418240 ps |
| CPU time | 109.9 seconds |
| Started | Oct 14 09:21:30 PM UTC 24 |
| Finished | Oct 14 09:23:22 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135112749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4135112749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.3655309117 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 218196579459 ps |
| CPU time | 142.5 seconds |
| Started | Oct 14 09:55:14 PM UTC 24 |
| Finished | Oct 14 09:57:39 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655309117 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3655309117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.2963554432 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 427140541644 ps |
| CPU time | 2706.33 seconds |
| Started | Oct 14 09:55:15 PM UTC 24 |
| Finished | Oct 14 10:40:48 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963554432 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2963554432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.1336300976 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 150929265905 ps |
| CPU time | 64.93 seconds |
| Started | Oct 14 09:55:44 PM UTC 24 |
| Finished | Oct 14 09:56:51 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336300976 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1336300976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.2871316318 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 300579701248 ps |
| CPU time | 147.65 seconds |
| Started | Oct 14 09:56:01 PM UTC 24 |
| Finished | Oct 14 09:58:31 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871316318 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2871316318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.3634159235 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 248984966532 ps |
| CPU time | 264.91 seconds |
| Started | Oct 14 09:56:13 PM UTC 24 |
| Finished | Oct 14 10:00:42 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634159235 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3634159235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.1348816576 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 642250740661 ps |
| CPU time | 709.37 seconds |
| Started | Oct 14 09:56:17 PM UTC 24 |
| Finished | Oct 14 10:08:15 PM UTC 24 |
| Peak memory | 197076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348816576 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1348816576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1421762682 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 102263661757 ps |
| CPU time | 739.39 seconds |
| Started | Oct 14 09:56:31 PM UTC 24 |
| Finished | Oct 14 10:08:59 PM UTC 24 |
| Peak memory | 198732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421762682 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1421762682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.997284069 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 219533281906 ps |
| CPU time | 414.71 seconds |
| Started | Oct 14 09:21:45 PM UTC 24 |
| Finished | Oct 14 09:28:44 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997284069 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.997284069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.1721949769 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 89871372609 ps |
| CPU time | 134.88 seconds |
| Started | Oct 14 09:21:43 PM UTC 24 |
| Finished | Oct 14 09:24:00 PM UTC 24 |
| Peak memory | 196668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721949769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1721949769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.1967640120 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 137335754547 ps |
| CPU time | 467.65 seconds |
| Started | Oct 14 09:21:37 PM UTC 24 |
| Finished | Oct 14 09:29:30 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967640120 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1967640120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.322945566 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 22996603497 ps |
| CPU time | 182.37 seconds |
| Started | Oct 14 09:21:48 PM UTC 24 |
| Finished | Oct 14 09:24:53 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322945566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.322945566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.3105419029 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 143812580857 ps |
| CPU time | 55.85 seconds |
| Started | Oct 14 09:56:40 PM UTC 24 |
| Finished | Oct 14 09:57:37 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105419029 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3105419029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.834547751 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 183215008815 ps |
| CPU time | 196.69 seconds |
| Started | Oct 14 09:56:50 PM UTC 24 |
| Finished | Oct 14 10:00:10 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834547751 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.834547751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.1626404966 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 156101060098 ps |
| CPU time | 964.81 seconds |
| Started | Oct 14 09:57:09 PM UTC 24 |
| Finished | Oct 14 10:13:26 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626404966 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1626404966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.1241901371 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 676711916944 ps |
| CPU time | 325.26 seconds |
| Started | Oct 14 09:57:27 PM UTC 24 |
| Finished | Oct 14 10:02:57 PM UTC 24 |
| Peak memory | 196740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241901371 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1241901371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.1432203609 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 102589296311 ps |
| CPU time | 841.16 seconds |
| Started | Oct 14 09:57:40 PM UTC 24 |
| Finished | Oct 14 10:11:51 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432203609 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1432203609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.1951722336 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 123102564313 ps |
| CPU time | 168.95 seconds |
| Started | Oct 14 09:58:13 PM UTC 24 |
| Finished | Oct 14 10:01:05 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951722336 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1951722336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.50338234 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1219015578092 ps |
| CPU time | 782.47 seconds |
| Started | Oct 14 09:22:13 PM UTC 24 |
| Finished | Oct 14 09:35:24 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50338234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.50338234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.2241461204 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 230672270398 ps |
| CPU time | 375.97 seconds |
| Started | Oct 14 09:22:07 PM UTC 24 |
| Finished | Oct 14 09:28:27 PM UTC 24 |
| Peak memory | 196696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241461204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2241461204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.1423560008 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 57187066402 ps |
| CPU time | 453.96 seconds |
| Started | Oct 14 09:22:15 PM UTC 24 |
| Finished | Oct 14 09:29:55 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423560008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1423560008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.739610140 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 34564619798 ps |
| CPU time | 77.24 seconds |
| Started | Oct 14 09:58:32 PM UTC 24 |
| Finished | Oct 14 09:59:51 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739610140 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.739610140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.1755929845 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 447020043431 ps |
| CPU time | 243.13 seconds |
| Started | Oct 14 09:58:47 PM UTC 24 |
| Finished | Oct 14 10:02:53 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755929845 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1755929845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.728617017 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 114670992157 ps |
| CPU time | 39.83 seconds |
| Started | Oct 14 09:58:53 PM UTC 24 |
| Finished | Oct 14 09:59:34 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728617017 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.728617017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.940561945 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 48880249529 ps |
| CPU time | 102.71 seconds |
| Started | Oct 14 09:58:57 PM UTC 24 |
| Finished | Oct 14 10:00:42 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940561945 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.940561945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.1355571031 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 25232824938 ps |
| CPU time | 45.99 seconds |
| Started | Oct 14 09:59:25 PM UTC 24 |
| Finished | Oct 14 10:00:13 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355571031 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1355571031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.3938674124 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 38782784904 ps |
| CPU time | 72.97 seconds |
| Started | Oct 14 09:59:29 PM UTC 24 |
| Finished | Oct 14 10:00:44 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938674124 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3938674124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.2624505037 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 20173933759 ps |
| CPU time | 37.12 seconds |
| Started | Oct 14 09:59:39 PM UTC 24 |
| Finished | Oct 14 10:00:17 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624505037 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2624505037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.839343752 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 394301487165 ps |
| CPU time | 447.65 seconds |
| Started | Oct 14 09:59:40 PM UTC 24 |
| Finished | Oct 14 10:07:13 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839343752 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.839343752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.401454141 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 330923866998 ps |
| CPU time | 276.79 seconds |
| Started | Oct 14 09:59:44 PM UTC 24 |
| Finished | Oct 14 10:04:24 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401454141 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.401454141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.4018141594 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1003565777449 ps |
| CPU time | 622.78 seconds |
| Started | Oct 14 09:22:52 PM UTC 24 |
| Finished | Oct 14 09:33:21 PM UTC 24 |
| Peak memory | 196936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018141594 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.4018141594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.72820518 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 70302172986 ps |
| CPU time | 53.51 seconds |
| Started | Oct 14 09:22:39 PM UTC 24 |
| Finished | Oct 14 09:23:34 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72820518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.72820518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.23255916 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 115454340357 ps |
| CPU time | 1884.88 seconds |
| Started | Oct 14 09:22:37 PM UTC 24 |
| Finished | Oct 14 09:54:21 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23255916 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.23255916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.1508049268 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 73671751097 ps |
| CPU time | 24.81 seconds |
| Started | Oct 14 09:22:54 PM UTC 24 |
| Finished | Oct 14 09:23:20 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508049268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1508049268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.1136168215 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 391130265871 ps |
| CPU time | 200.87 seconds |
| Started | Oct 14 09:22:55 PM UTC 24 |
| Finished | Oct 14 09:26:19 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136168215 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.1136168215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all_with_rand_reset.2641591076 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1909689167 ps |
| CPU time | 25.3 seconds |
| Started | Oct 14 09:22:54 PM UTC 24 |
| Finished | Oct 14 09:23:21 PM UTC 24 |
| Peak memory | 200908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2641591076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.rv_timer_stress_all_with_rand_reset.2641591076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.3946369916 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 262429870597 ps |
| CPU time | 174.19 seconds |
| Started | Oct 14 09:59:51 PM UTC 24 |
| Finished | Oct 14 10:02:48 PM UTC 24 |
| Peak memory | 196696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946369916 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3946369916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.3893244201 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 539502067353 ps |
| CPU time | 478.85 seconds |
| Started | Oct 14 09:59:52 PM UTC 24 |
| Finished | Oct 14 10:07:57 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893244201 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3893244201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.963737124 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 171901549923 ps |
| CPU time | 142.65 seconds |
| Started | Oct 14 10:00:00 PM UTC 24 |
| Finished | Oct 14 10:02:25 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963737124 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.963737124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.1283909318 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 638724589276 ps |
| CPU time | 314.2 seconds |
| Started | Oct 14 10:00:09 PM UTC 24 |
| Finished | Oct 14 10:05:27 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283909318 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1283909318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.3797593673 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 550138311486 ps |
| CPU time | 284.91 seconds |
| Started | Oct 14 10:00:10 PM UTC 24 |
| Finished | Oct 14 10:04:59 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797593673 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3797593673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.4116032956 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 246634565977 ps |
| CPU time | 183.47 seconds |
| Started | Oct 14 10:00:13 PM UTC 24 |
| Finished | Oct 14 10:03:20 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116032956 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.4116032956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.990946742 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 476754270047 ps |
| CPU time | 1826.93 seconds |
| Started | Oct 14 10:00:18 PM UTC 24 |
| Finished | Oct 14 10:31:05 PM UTC 24 |
| Peak memory | 200504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990946742 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.990946742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.1992310702 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 100287075437 ps |
| CPU time | 295.34 seconds |
| Started | Oct 14 10:00:28 PM UTC 24 |
| Finished | Oct 14 10:05:27 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992310702 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1992310702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3390768043 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 159248951031 ps |
| CPU time | 660.14 seconds |
| Started | Oct 14 10:00:39 PM UTC 24 |
| Finished | Oct 14 10:11:46 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390768043 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3390768043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.2557629167 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 355264549257 ps |
| CPU time | 700.73 seconds |
| Started | Oct 14 09:23:02 PM UTC 24 |
| Finished | Oct 14 09:34:51 PM UTC 24 |
| Peak memory | 196828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557629167 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2557629167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.2756526815 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2900760641 ps |
| CPU time | 3.88 seconds |
| Started | Oct 14 09:23:21 PM UTC 24 |
| Finished | Oct 14 09:23:26 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756526815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2756526815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all_with_rand_reset.3494047000 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5855673453 ps |
| CPU time | 21.2 seconds |
| Started | Oct 14 09:23:21 PM UTC 24 |
| Finished | Oct 14 09:23:44 PM UTC 24 |
| Peak memory | 200888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3494047000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.rv_timer_stress_all_with_rand_reset.3494047000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.866291102 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1682031834336 ps |
| CPU time | 356.3 seconds |
| Started | Oct 14 10:00:40 PM UTC 24 |
| Finished | Oct 14 10:06:41 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866291102 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.866291102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.847872069 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 108099726244 ps |
| CPU time | 114.76 seconds |
| Started | Oct 14 10:00:43 PM UTC 24 |
| Finished | Oct 14 10:02:40 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847872069 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.847872069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.2637033362 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 307180003008 ps |
| CPU time | 354.24 seconds |
| Started | Oct 14 10:00:43 PM UTC 24 |
| Finished | Oct 14 10:06:42 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637033362 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2637033362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.2392501931 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 40265598146 ps |
| CPU time | 141.33 seconds |
| Started | Oct 14 10:00:54 PM UTC 24 |
| Finished | Oct 14 10:03:18 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392501931 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2392501931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.2107101649 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 765801954073 ps |
| CPU time | 462.67 seconds |
| Started | Oct 14 10:00:58 PM UTC 24 |
| Finished | Oct 14 10:08:47 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107101649 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2107101649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.3025331704 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 890081869247 ps |
| CPU time | 296.84 seconds |
| Started | Oct 14 10:01:05 PM UTC 24 |
| Finished | Oct 14 10:06:06 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025331704 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3025331704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.2590517246 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1436512708184 ps |
| CPU time | 964.96 seconds |
| Started | Oct 14 10:01:38 PM UTC 24 |
| Finished | Oct 14 10:17:54 PM UTC 24 |
| Peak memory | 200504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590517246 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2590517246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.371120108 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 391977554035 ps |
| CPU time | 674.84 seconds |
| Started | Oct 14 09:23:27 PM UTC 24 |
| Finished | Oct 14 09:34:49 PM UTC 24 |
| Peak memory | 196740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371120108 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.371120108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.1524873466 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 178781444794 ps |
| CPU time | 338.25 seconds |
| Started | Oct 14 09:23:25 PM UTC 24 |
| Finished | Oct 14 09:29:07 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524873466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1524873466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.1634355329 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 176604819237 ps |
| CPU time | 142.19 seconds |
| Started | Oct 14 09:23:24 PM UTC 24 |
| Finished | Oct 14 09:25:48 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634355329 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1634355329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.3642917885 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 143311516690 ps |
| CPU time | 368.78 seconds |
| Started | Oct 14 09:23:30 PM UTC 24 |
| Finished | Oct 14 09:29:43 PM UTC 24 |
| Peak memory | 197076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642917885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3642917885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.326684956 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 86068995232 ps |
| CPU time | 294.96 seconds |
| Started | Oct 14 10:02:14 PM UTC 24 |
| Finished | Oct 14 10:07:13 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326684956 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.326684956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.1882011890 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 454986798284 ps |
| CPU time | 210.17 seconds |
| Started | Oct 14 10:02:19 PM UTC 24 |
| Finished | Oct 14 10:05:52 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882011890 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1882011890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.2368954132 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 19668612640 ps |
| CPU time | 44.61 seconds |
| Started | Oct 14 10:02:26 PM UTC 24 |
| Finished | Oct 14 10:03:13 PM UTC 24 |
| Peak memory | 196828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368954132 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2368954132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1795947244 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 42655140290 ps |
| CPU time | 97.85 seconds |
| Started | Oct 14 10:02:41 PM UTC 24 |
| Finished | Oct 14 10:04:21 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795947244 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1795947244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.1506175617 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 364927279075 ps |
| CPU time | 1244.74 seconds |
| Started | Oct 14 10:02:54 PM UTC 24 |
| Finished | Oct 14 10:23:53 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506175617 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1506175617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.849214363 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 52717053723 ps |
| CPU time | 299.23 seconds |
| Started | Oct 14 10:02:58 PM UTC 24 |
| Finished | Oct 14 10:08:01 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849214363 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.849214363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.569733744 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 132045813756 ps |
| CPU time | 208.16 seconds |
| Started | Oct 14 09:23:41 PM UTC 24 |
| Finished | Oct 14 09:27:12 PM UTC 24 |
| Peak memory | 196668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569733744 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.569733744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.2772674674 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 56008883415 ps |
| CPU time | 26.68 seconds |
| Started | Oct 14 09:23:41 PM UTC 24 |
| Finished | Oct 14 09:24:09 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772674674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2772674674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1614789355 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 236182613599 ps |
| CPU time | 213.41 seconds |
| Started | Oct 14 09:23:35 PM UTC 24 |
| Finished | Oct 14 09:27:12 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614789355 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1614789355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.2570555261 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 179800303978 ps |
| CPU time | 98.26 seconds |
| Started | Oct 14 09:23:47 PM UTC 24 |
| Finished | Oct 14 09:25:28 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570555261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2570555261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.2603702063 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 201426496828 ps |
| CPU time | 485.03 seconds |
| Started | Oct 14 09:23:55 PM UTC 24 |
| Finished | Oct 14 09:32:06 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603702063 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.2603702063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.890708396 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 29797966314 ps |
| CPU time | 355.15 seconds |
| Started | Oct 14 10:03:00 PM UTC 24 |
| Finished | Oct 14 10:09:00 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890708396 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.890708396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.1659795380 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 273727155229 ps |
| CPU time | 277.67 seconds |
| Started | Oct 14 10:03:14 PM UTC 24 |
| Finished | Oct 14 10:07:55 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659795380 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1659795380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.582326886 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 54866738316 ps |
| CPU time | 178.67 seconds |
| Started | Oct 14 10:03:19 PM UTC 24 |
| Finished | Oct 14 10:06:20 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582326886 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.582326886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.4224303070 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 216951568497 ps |
| CPU time | 1300.26 seconds |
| Started | Oct 14 10:03:21 PM UTC 24 |
| Finished | Oct 14 10:25:15 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224303070 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.4224303070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.3346627753 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 133364007671 ps |
| CPU time | 171.09 seconds |
| Started | Oct 14 10:03:34 PM UTC 24 |
| Finished | Oct 14 10:06:28 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346627753 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3346627753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.1592899214 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 49000297378 ps |
| CPU time | 87.51 seconds |
| Started | Oct 14 10:03:52 PM UTC 24 |
| Finished | Oct 14 10:05:22 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592899214 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1592899214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.3362457410 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 64165223432 ps |
| CPU time | 448.05 seconds |
| Started | Oct 14 10:04:17 PM UTC 24 |
| Finished | Oct 14 10:11:51 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362457410 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3362457410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.1242252391 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3157684658 ps |
| CPU time | 2.56 seconds |
| Started | Oct 14 10:04:21 PM UTC 24 |
| Finished | Oct 14 10:04:25 PM UTC 24 |
| Peak memory | 196476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242252391 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1242252391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.4092412661 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 147793916814 ps |
| CPU time | 1873.12 seconds |
| Started | Oct 14 10:04:21 PM UTC 24 |
| Finished | Oct 14 10:35:55 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092412661 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4092412661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.3937975377 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 61924831437 ps |
| CPU time | 91.88 seconds |
| Started | Oct 14 09:24:09 PM UTC 24 |
| Finished | Oct 14 09:25:43 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937975377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3937975377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.3383248723 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 75263923896 ps |
| CPU time | 215.18 seconds |
| Started | Oct 14 09:24:01 PM UTC 24 |
| Finished | Oct 14 09:27:40 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383248723 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3383248723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.3803362506 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 36104306566 ps |
| CPU time | 47.25 seconds |
| Started | Oct 14 09:24:18 PM UTC 24 |
| Finished | Oct 14 09:25:06 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803362506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3803362506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1328100622 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 543619167872 ps |
| CPU time | 1026.6 seconds |
| Started | Oct 14 10:04:25 PM UTC 24 |
| Finished | Oct 14 10:21:42 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328100622 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1328100622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.3285187056 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 163375915459 ps |
| CPU time | 332.6 seconds |
| Started | Oct 14 10:04:26 PM UTC 24 |
| Finished | Oct 14 10:10:03 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285187056 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3285187056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.330871393 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 262142794688 ps |
| CPU time | 263.29 seconds |
| Started | Oct 14 10:04:41 PM UTC 24 |
| Finished | Oct 14 10:09:08 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330871393 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.330871393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.2066002479 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 210803082940 ps |
| CPU time | 450.62 seconds |
| Started | Oct 14 10:05:00 PM UTC 24 |
| Finished | Oct 14 10:12:36 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066002479 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2066002479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.2620140949 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 38154915908 ps |
| CPU time | 114.01 seconds |
| Started | Oct 14 10:05:06 PM UTC 24 |
| Finished | Oct 14 10:07:03 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620140949 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2620140949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.1467200824 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 876300279443 ps |
| CPU time | 168.98 seconds |
| Started | Oct 14 10:05:21 PM UTC 24 |
| Finished | Oct 14 10:08:13 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467200824 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1467200824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.2224012123 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 325291673062 ps |
| CPU time | 2356.21 seconds |
| Started | Oct 14 10:05:28 PM UTC 24 |
| Finished | Oct 14 10:45:09 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224012123 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2224012123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.2436141554 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6911429150 ps |
| CPU time | 11.71 seconds |
| Started | Oct 14 09:20:30 PM UTC 24 |
| Finished | Oct 14 09:20:43 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436141554 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.2436141554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.3132839022 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 127830329402 ps |
| CPU time | 171.5 seconds |
| Started | Oct 14 09:20:30 PM UTC 24 |
| Finished | Oct 14 09:23:24 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132839022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3132839022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.3267530611 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 468907666294 ps |
| CPU time | 532.44 seconds |
| Started | Oct 14 09:20:30 PM UTC 24 |
| Finished | Oct 14 09:29:29 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267530611 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3267530611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.1900155342 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 47550081685 ps |
| CPU time | 123.69 seconds |
| Started | Oct 14 09:20:30 PM UTC 24 |
| Finished | Oct 14 09:22:36 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900155342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1900155342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.651847308 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 35100038 ps |
| CPU time | 1.17 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:20:37 PM UTC 24 |
| Peak memory | 229420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651847308 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.651847308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.2517172432 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 510082649246 ps |
| CPU time | 991.29 seconds |
| Started | Oct 14 09:24:42 PM UTC 24 |
| Finished | Oct 14 09:41:24 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517172432 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2517172432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3412731008 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 14720627022 ps |
| CPU time | 45.97 seconds |
| Started | Oct 14 09:24:42 PM UTC 24 |
| Finished | Oct 14 09:25:29 PM UTC 24 |
| Peak memory | 196536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412731008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3412731008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.3913673722 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 720356688 ps |
| CPU time | 2.12 seconds |
| Started | Oct 14 09:24:44 PM UTC 24 |
| Finished | Oct 14 09:24:47 PM UTC 24 |
| Peak memory | 196612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913673722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3913673722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.1012428387 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 140913266036 ps |
| CPU time | 231.24 seconds |
| Started | Oct 14 09:25:07 PM UTC 24 |
| Finished | Oct 14 09:29:02 PM UTC 24 |
| Peak memory | 196940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012428387 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1012428387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.3364502940 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 586916476458 ps |
| CPU time | 280.2 seconds |
| Started | Oct 14 09:25:06 PM UTC 24 |
| Finished | Oct 14 09:29:50 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364502940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3364502940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.3017163421 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 39326704346 ps |
| CPU time | 206.82 seconds |
| Started | Oct 14 09:25:27 PM UTC 24 |
| Finished | Oct 14 09:28:57 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017163421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3017163421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.1482402571 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 469432556843 ps |
| CPU time | 372.68 seconds |
| Started | Oct 14 09:25:29 PM UTC 24 |
| Finished | Oct 14 09:31:46 PM UTC 24 |
| Peak memory | 196736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482402571 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.1482402571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.643308925 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 22629645239 ps |
| CPU time | 40.82 seconds |
| Started | Oct 14 09:25:36 PM UTC 24 |
| Finished | Oct 14 09:26:18 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643308925 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.643308925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.1448552381 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 505576869042 ps |
| CPU time | 157.66 seconds |
| Started | Oct 14 09:25:30 PM UTC 24 |
| Finished | Oct 14 09:28:10 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448552381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1448552381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.1954998401 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 124682208120 ps |
| CPU time | 219.58 seconds |
| Started | Oct 14 09:25:54 PM UTC 24 |
| Finished | Oct 14 09:29:37 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954998401 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1954998401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.1023064159 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 819691266340 ps |
| CPU time | 301.53 seconds |
| Started | Oct 14 09:25:50 PM UTC 24 |
| Finished | Oct 14 09:30:56 PM UTC 24 |
| Peak memory | 197016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023064159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1023064159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.3524026605 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 506616098442 ps |
| CPU time | 290.15 seconds |
| Started | Oct 14 09:25:49 PM UTC 24 |
| Finished | Oct 14 09:30:43 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524026605 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3524026605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.2326649459 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 164937508358 ps |
| CPU time | 98.81 seconds |
| Started | Oct 14 09:25:57 PM UTC 24 |
| Finished | Oct 14 09:27:37 PM UTC 24 |
| Peak memory | 196940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326649459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2326649459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.3868749509 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 207641593863 ps |
| CPU time | 695.38 seconds |
| Started | Oct 14 09:26:33 PM UTC 24 |
| Finished | Oct 14 09:38:17 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868749509 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3868749509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.3567947343 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 63223787293 ps |
| CPU time | 53.48 seconds |
| Started | Oct 14 09:26:24 PM UTC 24 |
| Finished | Oct 14 09:27:19 PM UTC 24 |
| Peak memory | 196896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567947343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3567947343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.2680797351 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 214671455750 ps |
| CPU time | 417.96 seconds |
| Started | Oct 14 09:26:20 PM UTC 24 |
| Finished | Oct 14 09:33:23 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680797351 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2680797351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.711185721 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 34886115596 ps |
| CPU time | 128.44 seconds |
| Started | Oct 14 09:26:35 PM UTC 24 |
| Finished | Oct 14 09:28:46 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711185721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.711185721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.1284435193 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 87724825380 ps |
| CPU time | 50.97 seconds |
| Started | Oct 14 09:27:20 PM UTC 24 |
| Finished | Oct 14 09:28:12 PM UTC 24 |
| Peak memory | 196680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284435193 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.1284435193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.1502950755 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 51173086052 ps |
| CPU time | 111.51 seconds |
| Started | Oct 14 09:27:38 PM UTC 24 |
| Finished | Oct 14 09:29:32 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502950755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1502950755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.3142538747 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 316200652465 ps |
| CPU time | 866.91 seconds |
| Started | Oct 14 09:27:42 PM UTC 24 |
| Finished | Oct 14 09:42:18 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142538747 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.3142538747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.388647023 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7599239422 ps |
| CPU time | 26.89 seconds |
| Started | Oct 14 09:27:41 PM UTC 24 |
| Finished | Oct 14 09:28:09 PM UTC 24 |
| Peak memory | 201036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=388647023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.388647023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1173819063 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 183920123492 ps |
| CPU time | 148.87 seconds |
| Started | Oct 14 09:27:51 PM UTC 24 |
| Finished | Oct 14 09:30:23 PM UTC 24 |
| Peak memory | 196696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173819063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1173819063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2580998455 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 420312883213 ps |
| CPU time | 154.9 seconds |
| Started | Oct 14 09:27:47 PM UTC 24 |
| Finished | Oct 14 09:30:25 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580998455 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2580998455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.2271037407 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 20961096446 ps |
| CPU time | 39.07 seconds |
| Started | Oct 14 09:28:10 PM UTC 24 |
| Finished | Oct 14 09:28:51 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271037407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2271037407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.322363065 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 849374485680 ps |
| CPU time | 988.43 seconds |
| Started | Oct 14 09:28:13 PM UTC 24 |
| Finished | Oct 14 09:44:53 PM UTC 24 |
| Peak memory | 198784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322363065 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.322363065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.985220593 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 972833820194 ps |
| CPU time | 406.66 seconds |
| Started | Oct 14 09:28:28 PM UTC 24 |
| Finished | Oct 14 09:35:19 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985220593 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.985220593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.1305001352 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 609405242346 ps |
| CPU time | 339.43 seconds |
| Started | Oct 14 09:28:23 PM UTC 24 |
| Finished | Oct 14 09:34:06 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305001352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1305001352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1840194719 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 186816495951 ps |
| CPU time | 192.53 seconds |
| Started | Oct 14 09:28:19 PM UTC 24 |
| Finished | Oct 14 09:31:35 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840194719 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1840194719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.196888179 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 399556090 ps |
| CPU time | 1.92 seconds |
| Started | Oct 14 09:28:29 PM UTC 24 |
| Finished | Oct 14 09:28:32 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196888179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.196888179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.1418380397 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 76649738567 ps |
| CPU time | 146.77 seconds |
| Started | Oct 14 09:28:45 PM UTC 24 |
| Finished | Oct 14 09:31:15 PM UTC 24 |
| Peak memory | 196944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418380397 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.1418380397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.3439001711 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 758976082437 ps |
| CPU time | 536.49 seconds |
| Started | Oct 14 09:28:58 PM UTC 24 |
| Finished | Oct 14 09:38:02 PM UTC 24 |
| Peak memory | 196876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439001711 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.3439001711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.367059473 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 166775937358 ps |
| CPU time | 287.42 seconds |
| Started | Oct 14 09:28:51 PM UTC 24 |
| Finished | Oct 14 09:33:42 PM UTC 24 |
| Peak memory | 196740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367059473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.367059473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.1810538508 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 603294215293 ps |
| CPU time | 469.07 seconds |
| Started | Oct 14 09:28:47 PM UTC 24 |
| Finished | Oct 14 09:36:42 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810538508 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1810538508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.1447805863 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 999590872 ps |
| CPU time | 2.45 seconds |
| Started | Oct 14 09:28:59 PM UTC 24 |
| Finished | Oct 14 09:29:03 PM UTC 24 |
| Peak memory | 196484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447805863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1447805863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1741476246 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 190487341110 ps |
| CPU time | 264.01 seconds |
| Started | Oct 14 09:29:03 PM UTC 24 |
| Finished | Oct 14 09:33:31 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741476246 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.1741476246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.2287592430 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1255555068 ps |
| CPU time | 15.55 seconds |
| Started | Oct 14 09:29:02 PM UTC 24 |
| Finished | Oct 14 09:29:19 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2287592430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.rv_timer_stress_all_with_rand_reset.2287592430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.1399457075 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 30654705275 ps |
| CPU time | 34.91 seconds |
| Started | Oct 14 09:29:21 PM UTC 24 |
| Finished | Oct 14 09:29:57 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399457075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1399457075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.1771495977 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 242340323077 ps |
| CPU time | 861.98 seconds |
| Started | Oct 14 09:29:07 PM UTC 24 |
| Finished | Oct 14 09:43:39 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771495977 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1771495977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1155519271 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 57610909639 ps |
| CPU time | 148.14 seconds |
| Started | Oct 14 09:29:30 PM UTC 24 |
| Finished | Oct 14 09:32:00 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155519271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1155519271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.3795230477 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2967924685374 ps |
| CPU time | 916.64 seconds |
| Started | Oct 14 09:29:32 PM UTC 24 |
| Finished | Oct 14 09:44:58 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795230477 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.3795230477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.1846855127 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 311018666401 ps |
| CPU time | 226.67 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:24:25 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846855127 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.1846855127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.25123230 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 182490192967 ps |
| CPU time | 135.45 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:22:53 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25123230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.25123230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.266357832 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 204617018407 ps |
| CPU time | 1662.83 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:48:36 PM UTC 24 |
| Peak memory | 200272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266357832 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.266357832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.945099746 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 172128956 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:20:37 PM UTC 24 |
| Peak memory | 195476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945099746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.945099746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.4236346654 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 106331736 ps |
| CPU time | 1.32 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:20:38 PM UTC 24 |
| Peak memory | 229108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236346654 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4236346654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.837185492 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 254150992856 ps |
| CPU time | 696.77 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:32:20 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837185492 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.837185492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all_with_rand_reset.1897601685 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2982783054 ps |
| CPU time | 24.07 seconds |
| Started | Oct 14 09:20:35 PM UTC 24 |
| Finished | Oct 14 09:21:01 PM UTC 24 |
| Peak memory | 203200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1897601685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.rv_timer_stress_all_with_rand_reset.1897601685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.1389998798 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 85054702106 ps |
| CPU time | 201.66 seconds |
| Started | Oct 14 09:29:45 PM UTC 24 |
| Finished | Oct 14 09:33:10 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389998798 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.1389998798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2134113292 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 77184701166 ps |
| CPU time | 256.91 seconds |
| Started | Oct 14 09:29:44 PM UTC 24 |
| Finished | Oct 14 09:34:05 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134113292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2134113292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.4164216961 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 82640131450 ps |
| CPU time | 383.96 seconds |
| Started | Oct 14 09:29:38 PM UTC 24 |
| Finished | Oct 14 09:36:07 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164216961 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4164216961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.3082507306 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1019112640 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 09:29:51 PM UTC 24 |
| Finished | Oct 14 09:29:54 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082507306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3082507306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.1034223589 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 536662666923 ps |
| CPU time | 264 seconds |
| Started | Oct 14 09:29:56 PM UTC 24 |
| Finished | Oct 14 09:34:23 PM UTC 24 |
| Peak memory | 196760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034223589 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.1034223589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.2925033150 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2153977686 ps |
| CPU time | 24.5 seconds |
| Started | Oct 14 09:29:54 PM UTC 24 |
| Finished | Oct 14 09:30:20 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2925033150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.rv_timer_stress_all_with_rand_reset.2925033150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.3688987452 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 554746225077 ps |
| CPU time | 393.64 seconds |
| Started | Oct 14 09:30:24 PM UTC 24 |
| Finished | Oct 14 09:37:03 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688987452 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.3688987452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.3734753459 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 190551601935 ps |
| CPU time | 130.06 seconds |
| Started | Oct 14 09:30:21 PM UTC 24 |
| Finished | Oct 14 09:32:33 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734753459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3734753459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.2690646995 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 86360076665 ps |
| CPU time | 473.26 seconds |
| Started | Oct 14 09:30:26 PM UTC 24 |
| Finished | Oct 14 09:38:25 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690646995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2690646995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.3448157109 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 295246109493 ps |
| CPU time | 449.56 seconds |
| Started | Oct 14 09:30:35 PM UTC 24 |
| Finished | Oct 14 09:38:10 PM UTC 24 |
| Peak memory | 196880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448157109 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.3448157109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.3658091242 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 400813853702 ps |
| CPU time | 270.82 seconds |
| Started | Oct 14 09:31:02 PM UTC 24 |
| Finished | Oct 14 09:35:37 PM UTC 24 |
| Peak memory | 196808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658091242 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3658091242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.1003509379 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 680860949663 ps |
| CPU time | 473.86 seconds |
| Started | Oct 14 09:30:56 PM UTC 24 |
| Finished | Oct 14 09:38:56 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003509379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1003509379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.136293867 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 836195303 ps |
| CPU time | 1.11 seconds |
| Started | Oct 14 09:31:15 PM UTC 24 |
| Finished | Oct 14 09:31:17 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136293867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.136293867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1593683492 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 313386006025 ps |
| CPU time | 557.82 seconds |
| Started | Oct 14 09:32:02 PM UTC 24 |
| Finished | Oct 14 09:41:26 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593683492 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1593683492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.1342143560 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 252283549929 ps |
| CPU time | 160.96 seconds |
| Started | Oct 14 09:31:48 PM UTC 24 |
| Finished | Oct 14 09:34:31 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342143560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1342143560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.472388833 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 393680413961 ps |
| CPU time | 420.91 seconds |
| Started | Oct 14 09:31:35 PM UTC 24 |
| Finished | Oct 14 09:38:42 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472388833 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.472388833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all_with_rand_reset.841736883 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2762759841 ps |
| CPU time | 36.29 seconds |
| Started | Oct 14 09:32:13 PM UTC 24 |
| Finished | Oct 14 09:32:51 PM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=841736883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.841736883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.1919858002 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 79478976460 ps |
| CPU time | 153.49 seconds |
| Started | Oct 14 09:32:51 PM UTC 24 |
| Finished | Oct 14 09:35:27 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919858002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1919858002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.2786305403 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 67425354797 ps |
| CPU time | 251.96 seconds |
| Started | Oct 14 09:33:10 PM UTC 24 |
| Finished | Oct 14 09:37:26 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786305403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2786305403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.619101821 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 106818669107 ps |
| CPU time | 211.14 seconds |
| Started | Oct 14 09:33:37 PM UTC 24 |
| Finished | Oct 14 09:37:11 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619101821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.619101821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.1775429099 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 22417210545 ps |
| CPU time | 61.35 seconds |
| Started | Oct 14 09:33:32 PM UTC 24 |
| Finished | Oct 14 09:34:35 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775429099 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1775429099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.3521347450 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 577129008093 ps |
| CPU time | 309.67 seconds |
| Started | Oct 14 09:33:56 PM UTC 24 |
| Finished | Oct 14 09:39:10 PM UTC 24 |
| Peak memory | 197076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521347450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3521347450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.1968661995 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 209012629294 ps |
| CPU time | 1335.24 seconds |
| Started | Oct 14 09:34:07 PM UTC 24 |
| Finished | Oct 14 09:56:37 PM UTC 24 |
| Peak memory | 200580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968661995 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.1968661995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.4282142866 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 402129208656 ps |
| CPU time | 447.04 seconds |
| Started | Oct 14 09:34:16 PM UTC 24 |
| Finished | Oct 14 09:41:49 PM UTC 24 |
| Peak memory | 196936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282142866 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.4282142866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.1636144350 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 51665263442 ps |
| CPU time | 43.97 seconds |
| Started | Oct 14 09:34:12 PM UTC 24 |
| Finished | Oct 14 09:34:58 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636144350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1636144350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.3583260230 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 238397724448 ps |
| CPU time | 1092.99 seconds |
| Started | Oct 14 09:34:09 PM UTC 24 |
| Finished | Oct 14 09:52:35 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583260230 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3583260230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.1886561365 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 25184551185 ps |
| CPU time | 58.94 seconds |
| Started | Oct 14 09:34:21 PM UTC 24 |
| Finished | Oct 14 09:35:21 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886561365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1886561365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.1273074525 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 353744620343 ps |
| CPU time | 1845.99 seconds |
| Started | Oct 14 09:34:29 PM UTC 24 |
| Finished | Oct 14 10:05:33 PM UTC 24 |
| Peak memory | 200368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273074525 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.1273074525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.497527563 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 271711621448 ps |
| CPU time | 456.6 seconds |
| Started | Oct 14 09:34:42 PM UTC 24 |
| Finished | Oct 14 09:42:24 PM UTC 24 |
| Peak memory | 196928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497527563 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.497527563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.175395756 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 668808325093 ps |
| CPU time | 242.87 seconds |
| Started | Oct 14 09:34:36 PM UTC 24 |
| Finished | Oct 14 09:38:42 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175395756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.175395756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2101473200 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 534924954 ps |
| CPU time | 1.1 seconds |
| Started | Oct 14 09:34:50 PM UTC 24 |
| Finished | Oct 14 09:34:52 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101473200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2101473200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.2365407996 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 29846644135 ps |
| CPU time | 105.11 seconds |
| Started | Oct 14 09:34:53 PM UTC 24 |
| Finished | Oct 14 09:36:41 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365407996 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.2365407996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2412981975 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 488191449056 ps |
| CPU time | 176.78 seconds |
| Started | Oct 14 09:35:20 PM UTC 24 |
| Finished | Oct 14 09:38:20 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412981975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2412981975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.3678641215 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 127049631900 ps |
| CPU time | 278.07 seconds |
| Started | Oct 14 09:34:58 PM UTC 24 |
| Finished | Oct 14 09:39:40 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678641215 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3678641215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.940721404 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1644526045 ps |
| CPU time | 2.33 seconds |
| Started | Oct 14 09:35:26 PM UTC 24 |
| Finished | Oct 14 09:35:30 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940721404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.940721404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all_with_rand_reset.2713360320 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2131430590 ps |
| CPU time | 18.2 seconds |
| Started | Oct 14 09:35:28 PM UTC 24 |
| Finished | Oct 14 09:35:47 PM UTC 24 |
| Peak memory | 203092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2713360320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.rv_timer_stress_all_with_rand_reset.2713360320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.431257233 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2704183011761 ps |
| CPU time | 1475.39 seconds |
| Started | Oct 14 09:35:48 PM UTC 24 |
| Finished | Oct 14 10:00:39 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431257233 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.431257233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1956780981 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 165212119184 ps |
| CPU time | 184.75 seconds |
| Started | Oct 14 09:35:38 PM UTC 24 |
| Finished | Oct 14 09:38:46 PM UTC 24 |
| Peak memory | 197016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956780981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1956780981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.3636450434 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 56972197254 ps |
| CPU time | 14.63 seconds |
| Started | Oct 14 09:35:35 PM UTC 24 |
| Finished | Oct 14 09:35:51 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636450434 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3636450434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.581068691 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 17985068062 ps |
| CPU time | 82.75 seconds |
| Started | Oct 14 09:35:51 PM UTC 24 |
| Finished | Oct 14 09:37:16 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581068691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.581068691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.239361689 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1551719491992 ps |
| CPU time | 1211.58 seconds |
| Started | Oct 14 09:36:11 PM UTC 24 |
| Finished | Oct 14 09:56:36 PM UTC 24 |
| Peak memory | 200416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239361689 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.239361689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.172446465 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 842170487695 ps |
| CPU time | 464.94 seconds |
| Started | Oct 14 09:20:38 PM UTC 24 |
| Finished | Oct 14 09:28:28 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172446465 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.172446465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.2494842087 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 87153196038 ps |
| CPU time | 173.04 seconds |
| Started | Oct 14 09:20:36 PM UTC 24 |
| Finished | Oct 14 09:23:31 PM UTC 24 |
| Peak memory | 196944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494842087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2494842087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.4134585657 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 114827267050 ps |
| CPU time | 289.77 seconds |
| Started | Oct 14 09:20:36 PM UTC 24 |
| Finished | Oct 14 09:25:29 PM UTC 24 |
| Peak memory | 196876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134585657 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4134585657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.563487115 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 132304619926 ps |
| CPU time | 62.5 seconds |
| Started | Oct 14 09:20:38 PM UTC 24 |
| Finished | Oct 14 09:21:42 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563487115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.563487115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.153118369 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 61341698 ps |
| CPU time | 0.96 seconds |
| Started | Oct 14 09:20:38 PM UTC 24 |
| Finished | Oct 14 09:20:40 PM UTC 24 |
| Peak memory | 226012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153118369 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.153118369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.260488864 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1003661453950 ps |
| CPU time | 442.58 seconds |
| Started | Oct 14 09:20:38 PM UTC 24 |
| Finished | Oct 14 09:28:06 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260488864 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.260488864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all_with_rand_reset.1169641602 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2475822069 ps |
| CPU time | 19.17 seconds |
| Started | Oct 14 09:20:38 PM UTC 24 |
| Finished | Oct 14 09:20:58 PM UTC 24 |
| Peak memory | 202896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1169641602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.rv_timer_stress_all_with_rand_reset.1169641602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.3011771812 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 404970344831 ps |
| CPU time | 721.58 seconds |
| Started | Oct 14 09:36:42 PM UTC 24 |
| Finished | Oct 14 09:48:51 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011771812 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3011771812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.2644738881 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 78525270629 ps |
| CPU time | 172.87 seconds |
| Started | Oct 14 09:36:37 PM UTC 24 |
| Finished | Oct 14 09:39:33 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644738881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2644738881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1481694025 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 303080981464 ps |
| CPU time | 355.19 seconds |
| Started | Oct 14 09:36:43 PM UTC 24 |
| Finished | Oct 14 09:42:42 PM UTC 24 |
| Peak memory | 196812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481694025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1481694025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.1718624798 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 293397720824 ps |
| CPU time | 485.21 seconds |
| Started | Oct 14 09:37:26 PM UTC 24 |
| Finished | Oct 14 09:45:37 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718624798 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.1718624798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.3368097986 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 668988785305 ps |
| CPU time | 408.97 seconds |
| Started | Oct 14 09:37:21 PM UTC 24 |
| Finished | Oct 14 09:44:15 PM UTC 24 |
| Peak memory | 196896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368097986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3368097986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.1113303151 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 439543173411 ps |
| CPU time | 268.78 seconds |
| Started | Oct 14 09:38:20 PM UTC 24 |
| Finished | Oct 14 09:42:52 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113303151 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.1113303151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.2886720270 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1211831721998 ps |
| CPU time | 1427.11 seconds |
| Started | Oct 14 09:38:10 PM UTC 24 |
| Finished | Oct 14 10:02:13 PM UTC 24 |
| Peak memory | 200576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886720270 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2886720270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1358528096 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 169855702663 ps |
| CPU time | 216.1 seconds |
| Started | Oct 14 09:38:21 PM UTC 24 |
| Finished | Oct 14 09:42:00 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358528096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1358528096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.2985567932 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 38453286498 ps |
| CPU time | 18.03 seconds |
| Started | Oct 14 09:38:44 PM UTC 24 |
| Finished | Oct 14 09:39:03 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985567932 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.2985567932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.113092680 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 141133684467 ps |
| CPU time | 337.48 seconds |
| Started | Oct 14 09:38:43 PM UTC 24 |
| Finished | Oct 14 09:44:25 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113092680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.113092680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.1195249288 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 160471211269 ps |
| CPU time | 235.22 seconds |
| Started | Oct 14 09:38:58 PM UTC 24 |
| Finished | Oct 14 09:42:57 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195249288 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.1195249288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.956985204 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 144943301243 ps |
| CPU time | 146.11 seconds |
| Started | Oct 14 09:39:06 PM UTC 24 |
| Finished | Oct 14 09:41:34 PM UTC 24 |
| Peak memory | 196864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956985204 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.956985204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.1901424505 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 141974832814 ps |
| CPU time | 511.43 seconds |
| Started | Oct 14 09:39:05 PM UTC 24 |
| Finished | Oct 14 09:47:42 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901424505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1901424505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.99325838 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 346994372774 ps |
| CPU time | 693.89 seconds |
| Started | Oct 14 09:39:02 PM UTC 24 |
| Finished | Oct 14 09:50:44 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99325838 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.99325838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.3061571641 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 71491324984 ps |
| CPU time | 222.96 seconds |
| Started | Oct 14 09:39:11 PM UTC 24 |
| Finished | Oct 14 09:42:57 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061571641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3061571641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.3448471637 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 119394809666 ps |
| CPU time | 162.89 seconds |
| Started | Oct 14 09:39:41 PM UTC 24 |
| Finished | Oct 14 09:42:26 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448471637 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.3448471637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.1324088336 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 225387835686 ps |
| CPU time | 175.47 seconds |
| Started | Oct 14 09:39:52 PM UTC 24 |
| Finished | Oct 14 09:42:50 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324088336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1324088336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.151305471 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 121070510593 ps |
| CPU time | 357.55 seconds |
| Started | Oct 14 09:39:45 PM UTC 24 |
| Finished | Oct 14 09:45:47 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151305471 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.151305471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.1014540103 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 74430612265 ps |
| CPU time | 427.76 seconds |
| Started | Oct 14 09:40:03 PM UTC 24 |
| Finished | Oct 14 09:47:17 PM UTC 24 |
| Peak memory | 196812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014540103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1014540103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.4160697849 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 563454749478 ps |
| CPU time | 1058.93 seconds |
| Started | Oct 14 09:40:22 PM UTC 24 |
| Finished | Oct 14 09:58:12 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160697849 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.4160697849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.2869825538 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 7752563827 ps |
| CPU time | 7.39 seconds |
| Started | Oct 14 09:41:25 PM UTC 24 |
| Finished | Oct 14 09:41:34 PM UTC 24 |
| Peak memory | 196680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869825538 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2869825538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.2559959400 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 136264265908 ps |
| CPU time | 46.22 seconds |
| Started | Oct 14 09:41:24 PM UTC 24 |
| Finished | Oct 14 09:42:12 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559959400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2559959400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.489037467 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 832534798397 ps |
| CPU time | 1075.73 seconds |
| Started | Oct 14 09:40:45 PM UTC 24 |
| Finished | Oct 14 09:58:52 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489037467 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.489037467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.3781951622 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 12711537989 ps |
| CPU time | 40.73 seconds |
| Started | Oct 14 09:41:26 PM UTC 24 |
| Finished | Oct 14 09:42:08 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781951622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3781951622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all_with_rand_reset.2999431402 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2061652537 ps |
| CPU time | 26.93 seconds |
| Started | Oct 14 09:41:34 PM UTC 24 |
| Finished | Oct 14 09:42:02 PM UTC 24 |
| Peak memory | 201040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2999431402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.rv_timer_stress_all_with_rand_reset.2999431402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.4056341994 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2009890808264 ps |
| CPU time | 1125.13 seconds |
| Started | Oct 14 09:42:01 PM UTC 24 |
| Finished | Oct 14 10:00:57 PM UTC 24 |
| Peak memory | 200440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056341994 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.4056341994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2419330638 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 259572798091 ps |
| CPU time | 215.44 seconds |
| Started | Oct 14 09:41:50 PM UTC 24 |
| Finished | Oct 14 09:45:28 PM UTC 24 |
| Peak memory | 197024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419330638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2419330638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.589958946 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 81655839179 ps |
| CPU time | 148.84 seconds |
| Started | Oct 14 09:41:43 PM UTC 24 |
| Finished | Oct 14 09:44:15 PM UTC 24 |
| Peak memory | 196728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589958946 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.589958946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.992301095 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 792788753 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 09:42:04 PM UTC 24 |
| Finished | Oct 14 09:42:06 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992301095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.992301095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.4178110467 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 278961820248 ps |
| CPU time | 833.52 seconds |
| Started | Oct 14 09:42:09 PM UTC 24 |
| Finished | Oct 14 09:56:11 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178110467 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.4178110467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.764510263 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1296055467110 ps |
| CPU time | 563.63 seconds |
| Started | Oct 14 09:42:25 PM UTC 24 |
| Finished | Oct 14 09:51:56 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764510263 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.764510263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.3241719634 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 257044209252 ps |
| CPU time | 241.62 seconds |
| Started | Oct 14 09:42:19 PM UTC 24 |
| Finished | Oct 14 09:46:24 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241719634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3241719634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.1310774535 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 343358843520 ps |
| CPU time | 591.84 seconds |
| Started | Oct 14 09:42:13 PM UTC 24 |
| Finished | Oct 14 09:52:11 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310774535 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1310774535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.4163076688 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 159214394361 ps |
| CPU time | 366.15 seconds |
| Started | Oct 14 09:42:27 PM UTC 24 |
| Finished | Oct 14 09:48:38 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163076688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4163076688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.2925253449 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8435429918 ps |
| CPU time | 25.22 seconds |
| Started | Oct 14 09:42:58 PM UTC 24 |
| Finished | Oct 14 09:43:24 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925253449 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.2925253449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.4021572048 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 355621068746 ps |
| CPU time | 202.68 seconds |
| Started | Oct 14 09:42:52 PM UTC 24 |
| Finished | Oct 14 09:46:18 PM UTC 24 |
| Peak memory | 197080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021572048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4021572048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2430774714 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 167723211663 ps |
| CPU time | 133.1 seconds |
| Started | Oct 14 09:42:51 PM UTC 24 |
| Finished | Oct 14 09:45:07 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430774714 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2430774714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.1563904408 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 450946174 ps |
| CPU time | 2.39 seconds |
| Started | Oct 14 09:42:58 PM UTC 24 |
| Finished | Oct 14 09:43:01 PM UTC 24 |
| Peak memory | 196884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563904408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1563904408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.4190561392 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 764374865861 ps |
| CPU time | 214.12 seconds |
| Started | Oct 14 09:20:40 PM UTC 24 |
| Finished | Oct 14 09:24:17 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190561392 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.4190561392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.3047369202 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 448018460382 ps |
| CPU time | 236.87 seconds |
| Started | Oct 14 09:20:40 PM UTC 24 |
| Finished | Oct 14 09:24:40 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047369202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3047369202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.3843737999 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4671715622 ps |
| CPU time | 8.17 seconds |
| Started | Oct 14 09:20:41 PM UTC 24 |
| Finished | Oct 14 09:20:51 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843737999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3843737999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.4039509939 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1609405665931 ps |
| CPU time | 346.46 seconds |
| Started | Oct 14 09:20:43 PM UTC 24 |
| Finished | Oct 14 09:26:34 PM UTC 24 |
| Peak memory | 196728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039509939 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.4039509939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.730712013 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 89634936394 ps |
| CPU time | 164.58 seconds |
| Started | Oct 14 09:43:18 PM UTC 24 |
| Finished | Oct 14 09:46:05 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730712013 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.730712013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2850534381 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 39787750082 ps |
| CPU time | 88.69 seconds |
| Started | Oct 14 09:43:25 PM UTC 24 |
| Finished | Oct 14 09:44:56 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850534381 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2850534381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.4077379639 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 137996116103 ps |
| CPU time | 321.7 seconds |
| Started | Oct 14 09:43:32 PM UTC 24 |
| Finished | Oct 14 09:48:58 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077379639 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4077379639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.3045785064 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 182362466154 ps |
| CPU time | 770.35 seconds |
| Started | Oct 14 09:44:09 PM UTC 24 |
| Finished | Oct 14 09:57:09 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045785064 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3045785064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.3755635455 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 134599777881 ps |
| CPU time | 325.05 seconds |
| Started | Oct 14 09:44:15 PM UTC 24 |
| Finished | Oct 14 09:49:45 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755635455 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3755635455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.1050537071 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 401388554963 ps |
| CPU time | 224.41 seconds |
| Started | Oct 14 09:44:16 PM UTC 24 |
| Finished | Oct 14 09:48:04 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050537071 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1050537071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.225989438 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 18207275848 ps |
| CPU time | 173.67 seconds |
| Started | Oct 14 09:44:26 PM UTC 24 |
| Finished | Oct 14 09:47:22 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225989438 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.225989438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.4114760193 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 41444878501 ps |
| CPU time | 141.5 seconds |
| Started | Oct 14 09:44:53 PM UTC 24 |
| Finished | Oct 14 09:47:17 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114760193 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4114760193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.513522351 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 339820516330 ps |
| CPU time | 621.82 seconds |
| Started | Oct 14 09:20:48 PM UTC 24 |
| Finished | Oct 14 09:31:17 PM UTC 24 |
| Peak memory | 200620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513522351 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.513522351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.2672759454 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 312137245035 ps |
| CPU time | 216.05 seconds |
| Started | Oct 14 09:20:48 PM UTC 24 |
| Finished | Oct 14 09:24:27 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672759454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2672759454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.4174635166 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 352821613191 ps |
| CPU time | 174.1 seconds |
| Started | Oct 14 09:20:43 PM UTC 24 |
| Finished | Oct 14 09:23:40 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174635166 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.4174635166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.3649485655 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 256683738170 ps |
| CPU time | 350.71 seconds |
| Started | Oct 14 09:20:50 PM UTC 24 |
| Finished | Oct 14 09:26:45 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649485655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3649485655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.1524092683 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 168525314347 ps |
| CPU time | 488.96 seconds |
| Started | Oct 14 09:44:54 PM UTC 24 |
| Finished | Oct 14 09:53:09 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524092683 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1524092683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.1597285695 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 188414569734 ps |
| CPU time | 871.08 seconds |
| Started | Oct 14 09:44:57 PM UTC 24 |
| Finished | Oct 14 09:59:38 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597285695 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1597285695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.2545376646 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 155467006719 ps |
| CPU time | 266.76 seconds |
| Started | Oct 14 09:44:59 PM UTC 24 |
| Finished | Oct 14 09:49:29 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545376646 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2545376646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.3747064474 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 9963102621 ps |
| CPU time | 29.95 seconds |
| Started | Oct 14 09:45:08 PM UTC 24 |
| Finished | Oct 14 09:45:40 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747064474 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3747064474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.1371753967 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 24318613706 ps |
| CPU time | 22.75 seconds |
| Started | Oct 14 09:45:37 PM UTC 24 |
| Finished | Oct 14 09:46:01 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371753967 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1371753967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.3923087432 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 542855750670 ps |
| CPU time | 1381.98 seconds |
| Started | Oct 14 09:45:40 PM UTC 24 |
| Finished | Oct 14 10:08:58 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923087432 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3923087432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.2052311694 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 621831394050 ps |
| CPU time | 217.84 seconds |
| Started | Oct 14 09:46:03 PM UTC 24 |
| Finished | Oct 14 09:49:43 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052311694 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2052311694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.933180746 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 140443436503 ps |
| CPU time | 110.69 seconds |
| Started | Oct 14 09:46:06 PM UTC 24 |
| Finished | Oct 14 09:47:59 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933180746 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.933180746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.2143160134 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 476785218988 ps |
| CPU time | 909.71 seconds |
| Started | Oct 14 09:20:55 PM UTC 24 |
| Finished | Oct 14 09:36:14 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143160134 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.2143160134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.3000917164 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 179730698403 ps |
| CPU time | 268.99 seconds |
| Started | Oct 14 09:20:53 PM UTC 24 |
| Finished | Oct 14 09:25:26 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000917164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3000917164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1072674304 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 207451294588 ps |
| CPU time | 402.88 seconds |
| Started | Oct 14 09:20:53 PM UTC 24 |
| Finished | Oct 14 09:27:41 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072674304 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1072674304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.2087901388 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10419968471 ps |
| CPU time | 19.27 seconds |
| Started | Oct 14 09:20:55 PM UTC 24 |
| Finished | Oct 14 09:21:16 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087901388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2087901388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.2581685508 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 169443527270 ps |
| CPU time | 149.42 seconds |
| Started | Oct 14 09:20:57 PM UTC 24 |
| Finished | Oct 14 09:23:30 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581685508 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.2581685508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all_with_rand_reset.2743878746 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2463342795 ps |
| CPU time | 15.82 seconds |
| Started | Oct 14 09:20:57 PM UTC 24 |
| Finished | Oct 14 09:21:15 PM UTC 24 |
| Peak memory | 202936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2743878746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.rv_timer_stress_all_with_rand_reset.2743878746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.3786566721 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 661367459112 ps |
| CPU time | 2164.84 seconds |
| Started | Oct 14 09:46:19 PM UTC 24 |
| Finished | Oct 14 10:22:46 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786566721 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3786566721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1753039502 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 94484582105 ps |
| CPU time | 284.33 seconds |
| Started | Oct 14 09:46:25 PM UTC 24 |
| Finished | Oct 14 09:51:14 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753039502 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1753039502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.2587136727 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 207553213069 ps |
| CPU time | 832.91 seconds |
| Started | Oct 14 09:46:53 PM UTC 24 |
| Finished | Oct 14 10:00:55 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587136727 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2587136727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3745618629 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 119026486546 ps |
| CPU time | 744 seconds |
| Started | Oct 14 09:47:17 PM UTC 24 |
| Finished | Oct 14 09:59:50 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745618629 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3745618629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.4074357146 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 143593298872 ps |
| CPU time | 294.86 seconds |
| Started | Oct 14 09:47:17 PM UTC 24 |
| Finished | Oct 14 09:52:16 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074357146 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4074357146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.3647833041 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 15385995145 ps |
| CPU time | 51.09 seconds |
| Started | Oct 14 09:47:23 PM UTC 24 |
| Finished | Oct 14 09:48:16 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647833041 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3647833041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.899947508 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 42961576683 ps |
| CPU time | 258.73 seconds |
| Started | Oct 14 09:47:59 PM UTC 24 |
| Finished | Oct 14 09:52:22 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899947508 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.899947508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.1519552576 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 147040166279 ps |
| CPU time | 1088.18 seconds |
| Started | Oct 14 09:48:04 PM UTC 24 |
| Finished | Oct 14 10:06:24 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519552576 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1519552576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.339445460 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 442095309799 ps |
| CPU time | 203.89 seconds |
| Started | Oct 14 09:21:01 PM UTC 24 |
| Finished | Oct 14 09:24:28 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339445460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.339445460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2076907560 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 807343307672 ps |
| CPU time | 1131.8 seconds |
| Started | Oct 14 09:20:57 PM UTC 24 |
| Finished | Oct 14 09:40:03 PM UTC 24 |
| Peak memory | 200444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076907560 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2076907560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.1813774948 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 237717787867 ps |
| CPU time | 261.15 seconds |
| Started | Oct 14 09:21:01 PM UTC 24 |
| Finished | Oct 14 09:25:26 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813774948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1813774948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all_with_rand_reset.850213343 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2826754599 ps |
| CPU time | 27.19 seconds |
| Started | Oct 14 09:21:01 PM UTC 24 |
| Finished | Oct 14 09:21:30 PM UTC 24 |
| Peak memory | 202888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=850213343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.850213343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/8.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.4126507133 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 113068577804 ps |
| CPU time | 166.86 seconds |
| Started | Oct 14 09:48:17 PM UTC 24 |
| Finished | Oct 14 09:51:06 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126507133 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4126507133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.3813257265 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 490037449253 ps |
| CPU time | 934.59 seconds |
| Started | Oct 14 09:48:32 PM UTC 24 |
| Finished | Oct 14 10:04:17 PM UTC 24 |
| Peak memory | 198728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813257265 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3813257265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.3107403280 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 158227882136 ps |
| CPU time | 270.09 seconds |
| Started | Oct 14 09:48:37 PM UTC 24 |
| Finished | Oct 14 09:53:11 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107403280 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3107403280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.2061915600 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 85759567643 ps |
| CPU time | 205.48 seconds |
| Started | Oct 14 09:48:39 PM UTC 24 |
| Finished | Oct 14 09:52:08 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061915600 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2061915600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.2429311284 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 106260262926 ps |
| CPU time | 798.53 seconds |
| Started | Oct 14 09:48:51 PM UTC 24 |
| Finished | Oct 14 10:02:18 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429311284 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2429311284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.2255917934 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 45999520516 ps |
| CPU time | 99.57 seconds |
| Started | Oct 14 09:48:59 PM UTC 24 |
| Finished | Oct 14 09:50:41 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255917934 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2255917934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.2222432609 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 36126063429 ps |
| CPU time | 559.87 seconds |
| Started | Oct 14 09:49:30 PM UTC 24 |
| Finished | Oct 14 09:58:57 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222432609 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2222432609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.2118585187 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 188836080176 ps |
| CPU time | 965.25 seconds |
| Started | Oct 14 09:49:31 PM UTC 24 |
| Finished | Oct 14 10:05:48 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118585187 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2118585187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.3638778454 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 181056471280 ps |
| CPU time | 162.6 seconds |
| Started | Oct 14 09:49:33 PM UTC 24 |
| Finished | Oct 14 09:52:19 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638778454 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3638778454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.1508257367 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 166102861315 ps |
| CPU time | 152.49 seconds |
| Started | Oct 14 09:21:05 PM UTC 24 |
| Finished | Oct 14 09:23:40 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508257367 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.1508257367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.1623381113 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 116076537167 ps |
| CPU time | 106.41 seconds |
| Started | Oct 14 09:21:03 PM UTC 24 |
| Finished | Oct 14 09:22:51 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623381113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1623381113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.1890954372 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 47222427148 ps |
| CPU time | 44.47 seconds |
| Started | Oct 14 09:21:05 PM UTC 24 |
| Finished | Oct 14 09:21:51 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890954372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1890954372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.1249827360 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 218907868584 ps |
| CPU time | 427.28 seconds |
| Started | Oct 14 09:21:07 PM UTC 24 |
| Finished | Oct 14 09:28:19 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249827360 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.1249827360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2856332644 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 515579423312 ps |
| CPU time | 818.1 seconds |
| Started | Oct 14 09:49:46 PM UTC 24 |
| Finished | Oct 14 10:03:33 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856332644 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2856332644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2658302069 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 146726441491 ps |
| CPU time | 1796.06 seconds |
| Started | Oct 14 09:50:44 PM UTC 24 |
| Finished | Oct 14 10:21:00 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658302069 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2658302069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.1530882354 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 322035912820 ps |
| CPU time | 289.04 seconds |
| Started | Oct 14 09:51:07 PM UTC 24 |
| Finished | Oct 14 09:56:00 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530882354 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1530882354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.1171004601 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 81954263136 ps |
| CPU time | 128.57 seconds |
| Started | Oct 14 09:51:15 PM UTC 24 |
| Finished | Oct 14 09:53:25 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171004601 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1171004601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.807340208 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 229713266173 ps |
| CPU time | 137.78 seconds |
| Started | Oct 14 09:51:49 PM UTC 24 |
| Finished | Oct 14 09:54:09 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807340208 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.807340208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.4228402783 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 56013449904 ps |
| CPU time | 109.9 seconds |
| Started | Oct 14 09:51:57 PM UTC 24 |
| Finished | Oct 14 09:53:49 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228402783 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4228402783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.3303392109 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 26814294770 ps |
| CPU time | 142.64 seconds |
| Started | Oct 14 09:52:08 PM UTC 24 |
| Finished | Oct 14 09:54:33 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303392109 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3303392109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_timer-sim-vcs/99.rv_timer_random/latest |
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