SPI_DEVICE Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.340s	119.496us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.330s	77.077us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.740s	210.603us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	42.730s	3.998ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.500s	2.265ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.020s	33.017us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.740s	210.603us	20	20	100.00
		spi_device_csr_aliasing	28.500s	2.265ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	15.120s	994.577us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	7.590s	239.225us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	32.686m	270.651ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	57.454m	83.585ms	49	50	98.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	31.904m	1.500s	45	50	90.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	51.779m	125.793ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	51.779m	125.793ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.850s	24.829us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.940s	42.827us	50	50	100.00
V2	interrupts	spi_device_intr	3.050m	51.057ms	50	50	100.00
V2	abort	spi_device_abort	0.860s	16.257us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.960s	4.167ms	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.140s	3.710ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.290s	1.452ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	51.826m	296.493ms	48	50	96.00
V2	perf	spi_device_perf	53.420m	54.824ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.840s	22.854us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	231.425us	18	20	90.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	17.805us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.080s	413.273us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.080s	413.273us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	31.700s	11.483ms	50	50	100.00
		spi_device_tpm_sts_read	1.100s	132.805us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.916m	27.757ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	50.090s	18.779ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.560s	35.052ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.560s	35.052ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	cmd_read_status	spi_device_intercept	14.320s	4.360ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	14.320s	4.360ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	14.320s	4.360ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	14.320s	4.360ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	34.010s	116.771ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	51.070s	31.677ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	51.070s	31.677ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	51.070s	31.677ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.632m	84.099ms	48	50	96.00
		spi_device_read_buffer_direct	7.850s	1.886ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	51.070s	31.677ms	50	50	100.00
		spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	quad_spi	spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	dual_spi	spi_device_flash_all	6.312m	1.500s	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.170s	4.583ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.170s	4.583ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	17.407m	138.603ms	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.440m	218.480ms	49	50	98.00
V2	stress_all	spi_device_stress_all	1.178h	254.281ms	20	50	40.00
V2	alert_test	spi_device_alert_test	0.780s	29.318us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	19.289us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.810s	225.678us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.810s	225.678us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.330s	77.077us	5	5	100.00
		spi_device_csr_rw	2.740s	210.603us	20	20	100.00
		spi_device_csr_aliasing	28.500s	2.265ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	602.138us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.330s	77.077us	5	5	100.00
		spi_device_csr_rw	2.740s	210.603us	20	20	100.00
		spi_device_csr_aliasing	28.500s	2.265ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	602.138us	20	20	100.00
V2		TOTAL			1634	1680	97.26
V2S	tl_intg_err	spi_device_sec_cm	1.210s	142.897us	5	5	100.00
		spi_device_tl_intg_err	23.790s	5.239ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.790s	5.239ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1774	1820	97.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	27	75.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.95	99.01	96.23	98.63	92.06	97.95	96.16	98.63

Failure Buckets

UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 28 failures:

Test spi_device_stress_all has 28 failures.

1.spi_device_stress_all.1967768412
Line 226, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 294259896914 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xb8 [10111000] vs 0x2 [10]) addr 0x36675bc4 read out mismatch
  UVM_ERROR @ 294259896914 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x2e [101110] vs 0xce [11001110]) addr 0x36675bc5 read out mismatch
  UVM_ERROR @ 294259896914 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x7c [1111100] vs 0xae [10101110]) addr 0x36675bc6 read out mismatch
  UVM_ERROR @ 294259896914 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xcc [11001100] vs 0x8f [10001111]) addr 0x36675bc7 read out mismatch
  UVM_ERROR @ 294259980248 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x79 [1111001] vs 0x3 [11]) addr 0x36675bc8 read out mismatch

3.spi_device_stress_all.2494396970
Line 225, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 11234320561 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x40 [1000000] vs 0xb1 [10110001]) addr 0x174cd798 read out mismatch
  UVM_ERROR @ 11234320561 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xb7 [10110111] vs 0x81 [10000001]) addr 0x174cd799 read out mismatch
  UVM_ERROR @ 11234320561 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x82 [10000010] vs 0xe2 [11100010]) addr 0x174cd79a read out mismatch
  UVM_ERROR @ 11234320561 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x7a [1111010] vs 0x68 [1101000]) addr 0x174cd79b read out mismatch
  UVM_ERROR @ 11268585593 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x9d [10011101] vs 0x4e [1001110]) addr 0x174cd79c read out mismatch

... and 26 more failures.

Offending '(!dst_pulse_o)' has 4 failures:

Test spi_device_fifo_underflow_overflow has 4 failures.

9.spi_device_fifo_underflow_overflow.3459385938
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 22557102302 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  UVM_INFO @ 70578243550 ps: (spi_device_txrx_vseq.sv:109) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_fifo_underflow_overflow_vseq] starting sequence 2/2
  Starting assertion attempts at time 159547137673ps: level = 0 arg = tb.dut.u_txf_underflow.SrcPulseCheck_M (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:454))
  Starting assertion attempts at time 159547137673ps: level = 0 arg = tb.dut.u_txf_underflow.DstPulseCheck_A (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:455))

33.spi_device_fifo_underflow_overflow.1903798411
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 3012265279 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 4407909079ps failed at 4407952557ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 4407952557 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

... and 2 more failures.

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test spi_device_extreme_fifo_size has 1 failures.
  - 6.spi_device_extreme_fifo_size.3839107638
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_extreme_fifo_size/latest/run.log
```
  Job ID: smart:5500b03d-8b7d-4f06-8aab-56909fc4a9ec
```
- Test spi_device_stress_all has 1 failures.
  - 12.spi_device_stress_all.3637691172
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_stress_all/latest/run.log
```
  Job ID: smart:5c2f069b-317e-47b2-b34a-eba686fa9894
```
- Test spi_device_fifo_full has 1 failures.
  - 23.spi_device_fifo_full.3935927899
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:0629972e-e5da-492e-a9ce-72c5202f615b
```

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test spi_device_flash_all has 1 failures.

29.spi_device_flash_all.3484949670
Line 228, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_fifo_underflow_overflow has 1 failures.

41.spi_device_fifo_underflow_overflow.441036731
Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_fifo_underflow_overflow/latest/run.log

  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_extreme_fifo_size has 1 failures.

42.spi_device_extreme_fifo_size.791282867
Line 217, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_extreme_fifo_size/latest/run.log

  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:245) [spi_device_mem_parity_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:

Test spi_device_mem_parity has 2 failures.

4.spi_device_mem_parity.1416100372
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    914036 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (28672 [0x7000] vs 4294967295 [0xffffffff]) addr 0xd0 read out mismatch
  UVM_ERROR @    914036 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x000000d0
  UVM_ERROR @   1122376 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (28672 [0x7000] vs 4294967295 [0xffffffff]) addr 0xd0 read out mismatch
  UVM_ERROR @   1122376 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x000000d0
  UVM_ERROR @   1257797 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (28672 [0x7000] vs 4294967295 [0xffffffff]) addr 0xd0 read out mismatch

9.spi_device_mem_parity.2440040495
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  11605769 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x804 read out mismatch
  UVM_ERROR @  11605769 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000806
  UVM_ERROR @  12105769 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x804 read out mismatch
  UVM_ERROR @  12105769 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000806
  UVM_ERROR @  12605769 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x804 read out mismatch

UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare CmdFifoNotEmpty mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

14.spi_device_flash_and_tpm.579802243
Line 241, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 38276709150 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
  UVM_INFO @ 39182705526 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 16/17
  UVM_INFO @ 40037588397 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/15
  UVM_INFO @ 41367030122 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 17/17
  UVM_INFO @ 45322970397 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/15

UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_stress_all has 1 failures.

15.spi_device_stress_all.3026395265
Line 306, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 91154828737 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 124 [0x7c]) get_sram_filled_bytes
  UVM_ERROR @ 91155201615 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3435831905 [0xcccaa261] vs 2588849402 [0x9a4eb4fa]) Compare SPI RX data, addr: 0x7c
  UVM_ERROR @ 91155320258 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2272612476 [0x8775507c] vs 2235463011 [0x853e7563]) Compare SPI RX data, addr: 0x80
  UVM_ERROR @ 91155506697 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4090821264 [0xf3d4fa90] vs 1275579796 [0x4c07cd94]) Compare SPI RX data, addr: 0x84
  UVM_ERROR @ 91155913473 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3501947746 [0xd0bb7b62] vs 2766690729 [0xa4e859a9]) Compare SPI RX data, addr: 0x88

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

16.spi_device_flash_and_tpm_min_idle.209256772
Line 232, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 95752205970 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 96274251745 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/11
  UVM_ERROR @ 104026539752 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 107517667638 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 9/13
  UVM_INFO @ 107861346941 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/11

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

25.spi_device_flash_and_tpm.3692266995
Line 227, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 971625343389 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 971625343389 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 971625343389 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 971625343389 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 971625343389 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 40.spi_device_flash_mode.932722817
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 947732252 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1147085593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_device_scoreboard.sv:880) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 43.spi_device_flash_mode.3540764521
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/43.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 31728789604 ps: (spi_device_scoreboard.sv:880) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 31728789604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```