Unified Coverage Report :: Module :: prim_ram_2p_async_adv

Module : prim_ram_2p_async_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_memory_2p	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_memory_2p

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
19.21	0.00	0.00	76.82		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_2p_async_adv

	Line No.	Total	Covered	Percent
TOTAL		51	0	0.00
ALWAYS	136	3	0	0.00
ALWAYS	143	3	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	152	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	154	1	0	0.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	157	1	0	0.00
CONT_ASSIGN	158	1	0	0.00
CONT_ASSIGN	159	1	0	0.00
CONT_ASSIGN	160	1	0	0.00
CONT_ASSIGN	161	1	0	0.00
CONT_ASSIGN	162	1	0	0.00
ALWAYS	233	15	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	310	1	0	0.00
CONT_ASSIGN	311	1	0	0.00
CONT_ASSIGN	313	1	0	0.00
CONT_ASSIGN	314	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	316	1	0	0.00
CONT_ASSIGN	317	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	353	1	0	0.00
CONT_ASSIGN	355	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' or '../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	0	1
137	0	1
139	0	1
143	0	1
144	0	1
146	0	1
150	0	1
151	0	1
152	0	1
153	0	1
154	0	1
155	0	1
157	0	1
158	0	1
159	0	1
160	0	1
161	0	1
162	0	1
233	0	1
234	0	1
235	0	1
239	0	1
240	0	1
241	0	1
242	0	1
243	0	1
244	0	1
247	0	1
248	0	1
249	0	1
250	0	1
252	0	1
253	0	1
267	0	1
268	0	1
307	0	1
308	0	1
309	0	1
310	0	1
311	0	1
313	0	1
314	0	1
315	0	1
316	0	1
317	0	1
347	0	1
348	0	1
350	0	1
352	0	1
353	0	1
355	0	1

---

Cond Coverage for Module : prim_ram_2p_async_adv

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (a_req_q & ((~a_write_q)))
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       146
 EXPRESSION (b_req_q & ((~b_write_q)))
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_ram_2p_async_adv

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	136	2	0	0.00
IF	143	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv' or '../src/lowrisc_prim_ram_2p_async_adv_0.1/rtl/prim_ram_2p_async_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	136	if ((!rst_a_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	143	if ((!rst_b_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered