Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
19.21	0.00	0.00	76.82		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	19.21	0.00	0.00	76.82		0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
19.21	0.00	0.00	76.82		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.61	71.17	76.17	75.34	0.00	77.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	33.33	0.00				0.00	100.00
u_clk_csb_buf	0.00	0.00
u_clk_csb_edge_0	0.00	0.00	0.00			0.00
u_clk_csb_mux	0.00	0.00	0.00
u_clk_spi	0.00	0.00	0.00
u_clk_spi_in_buf	0.00	0.00
u_clk_spi_in_mux	0.00	0.00	0.00
u_clk_spi_out_buf	0.00	0.00
u_clk_spi_out_mux	0.00	0.00	0.00
u_cmdparse	0.00	0.00	0.00		0.00	0.00
u_csb_buf	0.00	0.00
u_csb_edge_spiclk	0.00	0.00	0.00			0.00
u_csb_edge_sysclk	0.00	0.00	0.00			0.00
u_csb_rst_scan_mux	0.00	0.00	0.00
u_flash_readbuf_flip_pulse_sync	0.00	0.00	0.00			0.00
u_flash_readbuf_watermark_pulse_sync	0.00	0.00	0.00			0.00
u_fwmode	0.00	0.00	0.00		0.00	0.00
u_intr_cmdfifo_not_empty	0.00	0.00	0.00			0.00
u_intr_payload_not_empty	0.00	0.00	0.00			0.00
u_intr_payload_overflow	0.00	0.00	0.00			0.00
u_intr_readbuf_flip	0.00	0.00	0.00			0.00
u_intr_readbuf_watermark	0.00	0.00	0.00			0.00
u_intr_rxerr	0.00	0.00	0.00			0.00
u_intr_rxf	0.00	0.00	0.00			0.00
u_intr_rxlvl	0.00	0.00	0.00			0.00
u_intr_rxoverflow	0.00	0.00	0.00			0.00
u_intr_tpm_cmdaddr_notempty	0.00	0.00	0.00			0.00
u_intr_txlvl	0.00	0.00	0.00			0.00
u_intr_txunderflow	0.00	0.00	0.00			0.00
u_intr_upload_edge	0.00	0.00				0.00
u_jedec	0.00	0.00	0.00		0.00	0.00
u_memory_2p	0.00	0.00	0.00			0.00
u_p2s	0.00	0.00	0.00			0.00
u_passthrough	0.00	0.00	0.00		0.00	0.00
u_readcmd	0.00	0.00	0.00		0.00	0.00
u_reg	94.29	99.49	99.52	73.13		99.32	100.00
u_rx_rst_scan_mux	0.00	0.00	0.00
u_rxf_overflow	0.00	0.00	0.00			0.00
u_s2p	0.00	0.00	0.00			0.00
u_sck_csb_edge	0.00	0.00	0.00			0.00
u_sck_tog_edge	0.00	0.00	0.00			0.00
u_spi_tpm	0.00	0.00	0.00		0.00	0.00
u_spid_addr_4b	0.00	0.00	0.00			0.00
u_spid_status	0.00	0.00	0.00		0.00	0.00
u_sram_clk_cg	0.00	0.00	0.00			0.00
u_sram_clk_scan	0.00	0.00	0.00
u_sram_clk_sel	0.00	0.00	0.00
u_sram_rst_scanmux	0.00	0.00	0.00
u_sram_rst_sel	0.00	0.00	0.00
u_sync_rxf	0.00	0.00				0.00
u_sync_txe	0.00	0.00				0.00
u_sys_sram_arbiter	0.00	0.00	0.00			0.00
u_sys_tpm_csb_sync	0.00	0.00				0.00
u_tlul2sram	0.00	0.00	0.00			0.00
u_tpm_csb_buf	0.00	0.00
u_tpm_csb_rst_scan_mux	0.00	0.00	0.00
u_tpm_csb_rst_sync	0.00	0.00	0.00			0.00
u_tx_rst_scan_mux	0.00	0.00	0.00
u_txf_underflow	0.00	0.00	0.00			0.00
u_upload	0.00	0.00	0.00		0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		244	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	341	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	402	1	0	0.00
CONT_ASSIGN	403	1	0	0.00
CONT_ASSIGN	405	1	0	0.00
CONT_ASSIGN	406	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	410	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	417	1	0	0.00
CONT_ASSIGN	419	1	0	0.00
CONT_ASSIGN	420	1	0	0.00
CONT_ASSIGN	423	1	0	0.00
CONT_ASSIGN	424	1	0	0.00
CONT_ASSIGN	427	1	0	0.00
CONT_ASSIGN	430	1	0	0.00
CONT_ASSIGN	431	1	0	0.00
CONT_ASSIGN	434	1	0	0.00
CONT_ASSIGN	435	1	0	0.00
CONT_ASSIGN	438	1	0	0.00
CONT_ASSIGN	439	1	0	0.00
ALWAYS	443	3	0	0.00
ALWAYS	447	3	0	0.00
CONT_ASSIGN	463	1	0	0.00
CONT_ASSIGN	467	1	0	0.00
CONT_ASSIGN	468	1	0	0.00
ALWAYS	480	5	0	0.00
CONT_ASSIGN	490	1	0	0.00
CONT_ASSIGN	491	0	0
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	494	1	0	0.00
ALWAYS	497	5	0	0.00
CONT_ASSIGN	505	1	0	0.00
CONT_ASSIGN	506	1	0	0.00
CONT_ASSIGN	623	1	0	0.00
CONT_ASSIGN	725	1	0	0.00
CONT_ASSIGN	732	1	0	0.00
CONT_ASSIGN	734	1	0	0.00
ALWAYS	737	4	0	0.00
CONT_ASSIGN	745	1	0	0.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	754	1	0	0.00
CONT_ASSIGN	755	1	0	0.00
CONT_ASSIGN	759	1	0	0.00
ALWAYS	764	0	0
ALWAYS	764	2	0	0.00
CONT_ASSIGN	769	1	0	0.00
CONT_ASSIGN	770	1	0	0.00
ALWAYS	778	0	0
ALWAYS	778	12	0	0.00
CONT_ASSIGN	844	1	0	0.00
CONT_ASSIGN	845	1	0	0.00
CONT_ASSIGN	846	1	0	0.00
ALWAYS	1095	6	0	0.00
ALWAYS	1121	4	0	0.00
CONT_ASSIGN	1140	1	0	0.00
ALWAYS	1164	3	0	0.00
ALWAYS	1170	8	0	0.00
ALWAYS	1208	35	0	0.00
ALWAYS	1301	13	0	0.00
ALWAYS	1338	3	0	0.00
CONT_ASSIGN	1540	1	0	0.00
CONT_ASSIGN	1542	1	0	0.00
CONT_ASSIGN	1545	1	0	0.00
CONT_ASSIGN	1546	1	0	0.00
CONT_ASSIGN	1548	1	0	0.00
CONT_ASSIGN	1549	1	0	0.00
CONT_ASSIGN	1588	1	0	0.00
CONT_ASSIGN	1618	1	0	0.00
CONT_ASSIGN	1702	1	0	0.00
CONT_ASSIGN	1703	1	0	0.00
CONT_ASSIGN	1705	1	0	0.00
CONT_ASSIGN	1707	1	0	0.00
CONT_ASSIGN	1708	1	0	0.00
CONT_ASSIGN	1710	1	0	0.00
CONT_ASSIGN	1714	1	0	0.00
CONT_ASSIGN	1717	1	0	0.00
CONT_ASSIGN	1720	1	0	0.00
CONT_ASSIGN	1723	1	0	0.00
CONT_ASSIGN	1726	1	0	0.00
CONT_ASSIGN	1729	1	0	0.00
CONT_ASSIGN	1736	1	0	0.00
CONT_ASSIGN	1737	1	0	0.00
CONT_ASSIGN	1779	1	0	0.00
CONT_ASSIGN	1881	1	0	0.00
CONT_ASSIGN	1889	1	0	0.00
CONT_ASSIGN	1890	1	0	0.00
CONT_ASSIGN	1891	1	0	0.00
CONT_ASSIGN	1892	1	0	0.00
CONT_ASSIGN	1893	1	0	0.00
CONT_ASSIGN	1896	1	0	0.00
CONT_ASSIGN	1905	1	0	0.00
CONT_ASSIGN	1905	1	0	0.00
CONT_ASSIGN	1905	1	0	0.00
CONT_ASSIGN	1905	1	0	0.00
CONT_ASSIGN	1905	1	0	0.00
CONT_ASSIGN	1908	1	0	0.00
CONT_ASSIGN	1909	1	0	0.00
CONT_ASSIGN	1910	1	0	0.00
CONT_ASSIGN	1911	1	0	0.00
CONT_ASSIGN	1912	1	0	0.00
CONT_ASSIGN	1913	1	0	0.00
CONT_ASSIGN	1915	1	0	0.00
CONT_ASSIGN	1919	1	0	0.00
CONT_ASSIGN	1921	1	0	0.00
CONT_ASSIGN	1922	1	0	0.00
CONT_ASSIGN	1929	1	0	0.00
CONT_ASSIGN	1931	1	0	0.00
CONT_ASSIGN	1933	1	0	0.00
CONT_ASSIGN	1937	1	0	0.00
CONT_ASSIGN	1939	1	0	0.00
CONT_ASSIGN	1940	1	0	0.00
CONT_ASSIGN	1976	1	0	0.00
ALWAYS	1983	6	0	0.00
CONT_ASSIGN	1994	1	0	0.00
CONT_ASSIGN	1994	1	0	0.00
CONT_ASSIGN	1996	1	0	0.00
CONT_ASSIGN	1996	1	0	0.00
CONT_ASSIGN	1996	1	0	0.00
CONT_ASSIGN	1997	1	0	0.00
CONT_ASSIGN	1997	1	0	0.00
CONT_ASSIGN	1997	1	0	0.00
CONT_ASSIGN	1998	1	0	0.00
CONT_ASSIGN	1998	1	0	0.00
CONT_ASSIGN	1998	1	0	0.00
CONT_ASSIGN	1999	1	0	0.00
CONT_ASSIGN	1999	1	0	0.00
CONT_ASSIGN	1999	1	0	0.00
CONT_ASSIGN	2001	1	0	0.00
CONT_ASSIGN	2001	1	0	0.00
CONT_ASSIGN	2001	1	0	0.00
CONT_ASSIGN	2002	1	0	0.00
CONT_ASSIGN	2002	1	0	0.00
CONT_ASSIGN	2002	1	0	0.00
CONT_ASSIGN	2003	1	0	0.00
CONT_ASSIGN	2003	1	0	0.00
CONT_ASSIGN	2003	1	0	0.00
CONT_ASSIGN	2046	1	0	0.00
CONT_ASSIGN	2047	1	0	0.00
CONT_ASSIGN	2048	1	0	0.00
CONT_ASSIGN	2049	1	0	0.00
CONT_ASSIGN	2050	1	0	0.00
CONT_ASSIGN	2052	1	0	0.00
CONT_ASSIGN	2053	1	0	0.00
CONT_ASSIGN	2054	1	0	0.00
CONT_ASSIGN	2114	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
191	0	1
341	0	1
400	0	1
401	0	1
402	0	1
403	0	1
405	0	1
406	0	1
408	0	1
410	0	1
414	0	1
415	0	1
416	0	1
417	0	1
419	0	1
420	0	1
423	0	1
424	0	1
427	0	1
430	0	1
431	0	1
434	0	1
435	0	1
438	0	1
439	0	1
443	0	2
444	0	1
447	0	2
448	0	1
463	0	1
467	0	1
468	0	1
480	0	1
481	0	1
482	0	1
484	0	1
485	0	1
490	0	1
491		unreachable
493	0	1
494	0	1
497	0	1
498	0	1
499	0	1
501	0	1
502	0	1
505	0	1
506	0	1
623	0	1
725	0	1
732	0	1
734	0	1
737	0	1
738	0	1
739	0	1
740	0	1
			==> MISSING_ELSE
745	0	1
751	0	1
754	0	1
755	0	1
759	0	1
764	0	1
765	0	1
769	0	1
770	0	1
778	0	1
779	0	1
797	0	1
798	0	1
802	0	1
803	0	1
805	0	1
806	0	1
808	0	1
809	0	1
811	0	1
812	0	1
844	0	1
845	0	1
846	0	1
1095	0	2
1096	0	1
1097	0	1
1098	0	1
1099	0	1
			==> MISSING_ELSE
1121	0	2
1122	0	1
1123	0	1
			==> MISSING_ELSE
1140	0	1
1164	0	2
1165	0	1
1170	0	1
1172	0	1
1173	0	1
1180	0	1
1184	0	1
1185	0	1
1189	0	1
1190	0	1
1208	0	1
1209	0	1
1210	0	1
1211	0	1
1213	0	1
1215	0	1
1221	0	1
1227	0	1
1229	0	1
1231	0	1
1232	0	1
1233	0	1
1237	0	1
1238	0	1
1243	0	1
1244	0	1
1246	0	1
1248	0	1
1250	0	1
1254	0	1
1256	0	1
1257	0	1
1258	0	1
1261	0	1
1263	0	1
1264	0	1
1265	0	1
1270	0	1
1272	0	1
1273	0	1
1274	0	1
1278	0	1
1280	0	1
1281	0	1
1282	0	1
1301	0	1
1302	0	1
1304	0	1
1306	0	1
1307	0	1
1311	0	1
1313	0	1
1314	0	1
1318	0	1
1319	0	1
1320	0	1
1322	0	1
1323	0	1
1338	0	2
1339	0	1
1540	0	1
1542	0	1
1545	0	1
1546	0	1
1548	0	1
1549	0	1
1588	0	1
1618	0	1
1702	0	1
1703	0	1
1705	0	1
1707	0	1
1708	0	1
1710	0	1
1714	0	1
1717	0	1
1720	0	1
1723	0	1
1726	0	1
1729	0	1
1736	0	1
1737	0	1
1779	0	1
1881	0	1
1889	0	1
1890	0	1
1891	0	1
1892	0	1
1893	0	1
1896	0	1
1905	0	5
1908	0	1
1909	0	1
1910	0	1
1911	0	1
1912	0	1
1913	0	1
1915	0	1
1919	0	1
1921	0	1
1922	0	1
1929	0	1
1931	0	1
1933	0	1
1937	0	1
1939	0	1
1940	0	1
1976	0	1
1983	0	1
1984	0	1
1985	0	1
1986	0	1
1987	0	1
1989	0	1
			==> MISSING_ELSE
1994	0	2
1996	0	3
1997	0	3
1998	0	3
1999	0	3
2001	0	3
2002	0	3
2003	0	3
2046	0	1
2047	0	1
2048	0	1
2049	0	1
2050	0	1
2052	0	1
2053	0	1
2054	0	1
2114	0	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	67	0	0.00
Logical	67	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       191
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       490
 EXPRESSION (((~sram_rxf_full_q)) & sram_rxf_full)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       491
 EXPRESSION (((~fwm_rxerr_q)) & fwm_rxerr)
             --------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       505
 EXPRESSION (((~rxlvl)) && rxlvl_d)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       506
 EXPRESSION (((~txlvl)) && txlvl_d)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       845
 EXPRESSION ((cpha ^ cpol) ? sck_n : cio_sck_i)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       845
 SUB-EXPRESSION (cpha ^ cpol)
                 --1-   --2-

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       846
 EXPRESSION ((cpha ^ cpol) ? cio_sck_i : sck_n)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       846
 SUB-EXPRESSION (cpha ^ cpol)
                 --1-   --2-

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       899
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       908
 EXPRESSION (rst_ni & ((~rst_txfifo_reg)))
             ---1--   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       917
 EXPRESSION (rst_ni & ((~rst_rxfifo_reg)))
             ---1--   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       928
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       976
 EXPRESSION (spi_mode == FwMode)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1003
 EXPRESSION (spi_mode == FwMode)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1140
 EXPRESSION (spi_clk_pos_edge | spi_clk_neg_edge)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       1194
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1304
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1540
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1548
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1549
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1736
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1737
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1986
 EXPRESSION ((0 != j) && sys_sram_l2m[j].req)
             ----1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1986
 SUB-EXPRESSION (0 != j)
                ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       2114
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	63	39	61.90
Total Bits	466	358	76.82
Total Bits 0->1	233	179	76.82
Total Bits 1->0	233	179	76.82

Ports	63	39	61.90
Port Bits	466	358	76.82
Port Bits 0->1	233	179	76.82
Port Bits 1->0	233	179	76.82

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T7,T8	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T9	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T9,T4	Yes	T2,T9,T4	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	OUTPUT
cio_sck_i	No	No		No		INPUT
cio_csb_i	No	No		No		INPUT
cio_sd_o[3:0]	No	No		No		OUTPUT
cio_sd_en_o[3:0]	No	No		No		OUTPUT
cio_sd_i[3:0]	No	No		No		INPUT
cio_tpm_csb_i	No	No		No		INPUT
passthrough_o.s_en[3:0]	No	No		No		OUTPUT
passthrough_o.s[3:0]	No	No		No		OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	No	No		No		OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	No	No		No		OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T5,T10,T12	Yes	T5,T10,T12	OUTPUT
passthrough_i.s[3:0]	No	No		No		INPUT
intr_generic_rx_full_o	Yes	Yes	T3,T8,T13	Yes	T3,T8,T13	OUTPUT
intr_generic_rx_watermark_o	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
intr_generic_tx_watermark_o	Yes	Yes	T3,T7,T13	Yes	T3,T7,T13	OUTPUT
intr_generic_rx_error_o	Yes	Yes	T7,T8,T13	Yes	T7,T8,T13	OUTPUT
intr_generic_rx_overflow_o	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
intr_generic_tx_underflow_o	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T3,T8,T13	Yes	T3,T8,T13	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T3,T8,T14	Yes	T3,T8,T14	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T3,T8,T13	Yes	T3,T8,T13	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T3,T8,T13	Yes	T3,T8,T13	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T3,T8,T13	Yes	T3,T8,T13	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
sck_monitor_o	No	No		No		OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		45	0	0.00
TERNARY	845	2	0	0.00
TERNARY	846	2	0	0.00
IF	443	2	0	0.00
IF	447	2	0	0.00
IF	480	2	0	0.00
IF	497	2	0	0.00
IF	737	3	0	0.00
IF	1095	4	0	0.00
IF	1121	3	0	0.00
IF	1164	2	0	0.00
CASE	1180	4	0	0.00
CASE	1227	8	0	0.00
IF	1304	5	0	0.00
IF	1338	2	0	0.00
IF	1986	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	845	((cpha ^ cpol)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	846	((cpha ^ cpol)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	443	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	447	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	497	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	737	if ((!rst_ni))
-2-:	739	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1095	if ((!tpm_rst_n))
-2-:	1096	if (spi_clk_csb_rst_pulse)
-3-:	1098	if (spi_clk_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	1121	if ((!rst_ni))
-2-:	1122	if (sys_csb_pos_pulse_stretch)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1164	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1180	case (cmd_dp_sel)
-2-:	1194	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Not Covered
DpUpload	-	Not Covered
default	1	Not Covered
default	0	Not Covered

	LineNo.	Expression
-1-:	1227	case (spi_mode)
-2-:	1246	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FwMode	-	Not Covered
FlashMode PassThrough	DpNone	Not Covered
FlashMode PassThrough	DpReadCmd DpReadSFDP	Not Covered
FlashMode PassThrough	DpReadStatus	Not Covered
FlashMode PassThrough	DpReadJEDEC	Not Covered
FlashMode PassThrough	DpUpload	Not Covered
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1304	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1311	case (spi_mode)
-3-:	1318	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	FwMode FlashMode	-	Not Covered
0	PassThrough	1	Not Covered
0	PassThrough	0	Not Covered
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1338	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1986	if (((0 != j) && sys_sram_l2m[j].req))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered