Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

162530346

1

T4

3939

T1

3

T5

8

full_word

19204216

1

T4

4230

T1

15

T5

37

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	181734122	1			T4	8169		T1	18		T5	45
auto[TlIntgErrCmd]	160	1			T117	12		T118	9		T119	10
auto[TlIntgErrData]	152	1			T117	10		T118	11		T119	7
auto[TlIntgErrBoth]	128	1			T117	8		T118	10		T119	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169540574

1

T4

5678

T1

5

T5

1

auto[1]

12193988

1

T4

2491

T1

13

T5

44

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	162172381	1			T4	3663		T1	3		T5	1
auto[TlIntgErrNone]	partial	auto[1]	357561	1			T4	276		T5	7		T2	3
auto[TlIntgErrNone]	full_word	auto[0]	7368000	1			T4	2015		T1	2		T2	12522
auto[TlIntgErrNone]	full_word	auto[1]	11836180	1			T4	2215		T1	13		T5	37
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T117	6		T118	5		T119	6
auto[TlIntgErrCmd]	partial	auto[1]	90	1			T117	4		T118	3		T119	4
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T117	2		T152	2		T201	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T118	1		T152	1		T201	2
auto[TlIntgErrData]	partial	auto[0]	66	1			T117	4		T118	6		T119	3
auto[TlIntgErrData]	partial	auto[1]	75	1			T117	6		T118	5		T119	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T200	1		T202	1		T203	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T145	1		T201	1		T200	2
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T117	6		T118	5		T119	1
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T117	2		T118	5		T119	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T199	1		T200	2		T202	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T199	1		T204	1		T198	1