Line Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 62 | 62 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 214 | 1 | 1 | 100.00 |
| ROUTINE | 230 | 7 | 7 | 100.00 |
| ROUTINE | 251 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 267 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 53 |
1 |
1 |
| 56 |
1 |
1 |
| 59 |
1 |
1 |
| 60 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 68 |
1 |
1 |
| 69 |
1 |
1 |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 86 |
1 |
1 |
| 89 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 94 |
1 |
1 |
| 95 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 101 |
1 |
1 |
| 102 |
1 |
1 |
| 103 |
1 |
1 |
| 104 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 120 |
1 |
1 |
| 130 |
1 |
1 |
| 131 |
1 |
1 |
| 132 |
1 |
1 |
| 142 |
1 |
1 |
| 143 |
1 |
1 |
| 144 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 159 |
1 |
1 |
| 160 |
1 |
1 |
| 171 |
1 |
1 |
| 172 |
1 |
1 |
| 182 |
1 |
1 |
| 183 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 187 |
1 |
1 |
| 214 |
1 |
1 |
| 230 |
1 |
1 |
| 232 |
1 |
1 |
| 235 |
1 |
1 |
| 236 |
1 |
1 |
| 239 |
1 |
1 |
| 240 |
1 |
1 |
| 243 |
1 |
1 |
| 251 |
1 |
1 |
| 252 |
1 |
1 |
| 253 |
1 |
1 |
| 255 |
1 |
1 |
| 256 |
1 |
1 |
| 257 |
1 |
1 |
| 259 |
1 |
1 |
| 260 |
1 |
1 |
| 262 |
1 |
1 |
| 267 |
1 |
1 |
| 269 |
1 |
1 |
| 271 |
1 |
1 |
| 272 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo
| Total | Covered | Percent |
|---|
| Conditions | 30 | 29 | 96.67 |
| Logical | 30 | 29 | 96.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T5 |
| 1 | 0 | Covered | T15,T37,T8 |
| 1 | 1 | Covered | T2,T3,T9 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T6,T15,T37 |
| 1 | 1 | Covered | T2,T3,T9 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T15,T37,T8 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T15,T37,T8 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T1,T5 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (4'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T15,T37,T8 |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T9 |
| 1 | Covered | T4,T1,T5 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T9 |
| 1 | Covered | T4,T1,T5 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (4'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T15,T37,T8 |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T9 |
| 1 | Covered | T4,T1,T5 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T9 |
| 1 | Covered | T4,T1,T5 |
LINE 232
EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T2,T3,T9 |
LINE 253
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T5 |
| 0 | 1 | Covered | T2,T3,T9 |
| 1 | 0 | Covered | T2,T3,T9 |
| 1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
26 |
26 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
160 |
3 |
3 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
| TERNARY |
232 |
2 |
2 |
100.00 |
| IF |
256 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 146 (full_wclk) ?
-2-: 146 ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T15,T37,T8 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T2,T3,T9 |
LineNo. Expression
-1-: 160 (full_rclk) ?
-2-: 160 ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T15,T37,T8 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T2,T3,T9 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T2,T3,T9 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T2,T3,T9 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T2,T3,T9 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T2,T3,T9 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 182 if (fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T9 |
| 0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 232 (decval[(PTR_WIDTH - 1)]) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T9 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 256 if (grayval[(PTR_WIDTH - 1)])
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T9 |
| 0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1506466077 |
1506459201 |
0 |
0 |
| T1 |
1455 |
1454 |
0 |
0 |
| T2 |
111894 |
111894 |
0 |
0 |
| T3 |
552889 |
552888 |
0 |
0 |
| T4 |
417115 |
417114 |
0 |
0 |
| T5 |
1314 |
1313 |
0 |
0 |
| T9 |
414742 |
414742 |
0 |
0 |
| T10 |
18303 |
18302 |
0 |
0 |
| T12 |
51690 |
51689 |
0 |
0 |
| T13 |
14966 |
14965 |
0 |
0 |
| T16 |
126670 |
126669 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
379241653 |
379240089 |
0 |
0 |
| T2 |
590170 |
590169 |
0 |
0 |
| T3 |
262881 |
262880 |
0 |
0 |
| T4 |
417115 |
417114 |
0 |
0 |
| T5 |
1314 |
1313 |
0 |
0 |
| T9 |
774846 |
774845 |
0 |
0 |
| T10 |
18303 |
18302 |
0 |
0 |
| T12 |
51690 |
51689 |
0 |
0 |
| T13 |
2847 |
2846 |
0 |
0 |
| T14 |
33 |
32 |
0 |
0 |
| T16 |
126670 |
126669 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1616 |
1616 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T39 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 62 | 62 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 214 | 1 | 1 | 100.00 |
| ROUTINE | 230 | 7 | 7 | 100.00 |
| ROUTINE | 251 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 267 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 53 |
1 |
1 |
| 56 |
1 |
1 |
| 59 |
1 |
1 |
| 60 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 68 |
1 |
1 |
| 69 |
1 |
1 |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 86 |
1 |
1 |
| 89 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 94 |
1 |
1 |
| 95 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 101 |
1 |
1 |
| 102 |
1 |
1 |
| 103 |
1 |
1 |
| 104 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 120 |
1 |
1 |
| 130 |
1 |
1 |
| 131 |
1 |
1 |
| 132 |
1 |
1 |
| 142 |
1 |
1 |
| 143 |
1 |
1 |
| 144 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 159 |
1 |
1 |
| 160 |
1 |
1 |
| 171 |
1 |
1 |
| 172 |
1 |
1 |
| 182 |
1 |
1 |
| 183 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 187 |
1 |
1 |
| 214 |
1 |
1 |
| 230 |
1 |
1 |
| 232 |
1 |
1 |
| 235 |
1 |
1 |
| 236 |
1 |
1 |
| 239 |
1 |
1 |
| 240 |
1 |
1 |
| 243 |
1 |
1 |
| 251 |
1 |
1 |
| 252 |
1 |
1 |
| 253 |
1 |
1 |
| 255 |
1 |
1 |
| 256 |
1 |
1 |
| 257 |
1 |
1 |
| 259 |
1 |
1 |
| 260 |
1 |
1 |
| 262 |
1 |
1 |
| 267 |
1 |
1 |
| 269 |
1 |
1 |
| 271 |
1 |
1 |
| 272 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo
| Total | Covered | Percent |
|---|
| Conditions | 30 | 29 | 96.67 |
| Logical | 30 | 29 | 96.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T15,T37,T8 |
| 1 | 0 | Covered | T2,T3,T9 |
| 1 | 1 | Covered | T2,T3,T9 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T2,T3,T9 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T1,T5 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (4'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T9 |
| 1 | Covered | T4,T1,T5 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T1,T5 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (4'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T2,T3,T9 |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T9 |
| 1 | Covered | T4,T1,T5 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T9 |
| 1 | Covered | T4,T1,T5 |
LINE 232
EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 253
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T5 |
| 0 | 1 | Covered | T2,T3,T9 |
| 1 | 0 | Covered | T2,T3,T9 |
| 1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
26 |
26 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
160 |
3 |
3 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
| TERNARY |
232 |
2 |
2 |
100.00 |
| IF |
256 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 146 (full_wclk) ?
-2-: 146 ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T2,T3,T9 |
LineNo. Expression
-1-: 160 (full_rclk) ?
-2-: 160 ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T2,T3,T9 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T2,T3,T9 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T2,T3,T9 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T2,T3,T9 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 182 if (fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 232 (decval[(PTR_WIDTH - 1)]) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 256 if (grayval[(PTR_WIDTH - 1)])
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T9 |
| 0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
379242896 |
379239785 |
0 |
0 |
| T1 |
1 |
0 |
0 |
0 |
| T2 |
590170 |
590168 |
0 |
0 |
| T3 |
262882 |
262880 |
0 |
0 |
| T4 |
417116 |
417114 |
0 |
0 |
| T5 |
1315 |
1313 |
0 |
0 |
| T9 |
774846 |
774844 |
0 |
0 |
| T10 |
0 |
18302 |
0 |
0 |
| T12 |
51691 |
51689 |
0 |
0 |
| T13 |
2847 |
2845 |
0 |
0 |
| T14 |
0 |
32 |
0 |
0 |
| T16 |
126670 |
126668 |
0 |
0 |
| T39 |
1 |
0 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1506466077 |
1506459169 |
0 |
0 |
| T1 |
1455 |
1454 |
0 |
0 |
| T2 |
111894 |
111894 |
0 |
0 |
| T3 |
552889 |
552888 |
0 |
0 |
| T4 |
417115 |
417114 |
0 |
0 |
| T5 |
1314 |
1313 |
0 |
0 |
| T9 |
414742 |
414742 |
0 |
0 |
| T10 |
18303 |
18302 |
0 |
0 |
| T12 |
51690 |
51689 |
0 |
0 |
| T13 |
14966 |
14965 |
0 |
0 |
| T16 |
126670 |
126669 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1616 |
1616 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T39 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 276 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 53 |
1 |
1 |
| 56 |
1 |
1 |
| 59 |
1 |
1 |
| 60 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 68 |
1 |
1 |
| 69 |
1 |
1 |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 86 |
1 |
1 |
| 89 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 94 |
1 |
1 |
| 95 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 101 |
1 |
1 |
| 102 |
1 |
1 |
| 103 |
1 |
1 |
| 104 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 120 |
1 |
1 |
| 130 |
1 |
1 |
| 131 |
1 |
1 |
| 132 |
1 |
1 |
| 142 |
1 |
1 |
| 143 |
1 |
1 |
| 144 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 159 |
1 |
1 |
| 160 |
1 |
1 |
| 171 |
1 |
1 |
| 172 |
1 |
1 |
| 182 |
1 |
1 |
| 183 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 187 |
1 |
1 |
| 207 |
1 |
1 |
| 276 |
1 |
1 |
| 277 |
1 |
1 |
| 279 |
1 |
1 |
| 280 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
| Total | Covered | Percent |
|---|
| Conditions | 25 | 20 | 80.00 |
| Logical | 25 | 20 | 80.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T12,T10,T6 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T5 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T12,T10,T6 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Not Covered | |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Not Covered | |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T1,T5 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Not Covered | |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T12,T10,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T12,T10,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Not Covered | |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T12,T10,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T12,T10,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T12,T10,T6 |
| 1 | Covered | T4,T1,T5 |
Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
24 |
22 |
91.67 |
| TERNARY |
146 |
3 |
2 |
66.67 |
| TERNARY |
160 |
3 |
2 |
66.67 |
| TERNARY |
207 |
2 |
2 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 146 (full_wclk) ?
-2-: 146 ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T12,T10,T6 |
LineNo. Expression
-1-: 160 (full_rclk) ?
-2-: 160 ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T12,T10,T6 |
LineNo. Expression
-1-: 207 (empty_rclk) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T12,T10,T6 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T12,T10,T6 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T12,T10,T6 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T12,T10,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T12,T10,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 182 if (fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T10,T6 |
| 0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
379241653 |
379240139 |
0 |
0 |
| T2 |
590170 |
590169 |
0 |
0 |
| T3 |
262881 |
262880 |
0 |
0 |
| T4 |
417115 |
417114 |
0 |
0 |
| T5 |
1314 |
1313 |
0 |
0 |
| T9 |
774846 |
774845 |
0 |
0 |
| T10 |
18303 |
18302 |
0 |
0 |
| T12 |
51690 |
51689 |
0 |
0 |
| T13 |
2847 |
2846 |
0 |
0 |
| T14 |
33 |
32 |
0 |
0 |
| T16 |
126670 |
126669 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1904520999 |
1904384551 |
0 |
0 |
| T1 |
1539 |
1473 |
0 |
0 |
| T2 |
111904 |
111896 |
0 |
0 |
| T3 |
552958 |
552902 |
0 |
0 |
| T4 |
154900 |
154823 |
0 |
0 |
| T5 |
6076 |
6013 |
0 |
0 |
| T9 |
414748 |
414743 |
0 |
0 |
| T12 |
55894 |
55810 |
0 |
0 |
| T13 |
15082 |
14982 |
0 |
0 |
| T16 |
545562 |
545505 |
0 |
0 |
| T39 |
1620 |
1540 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1616 |
1616 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T39 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 276 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 53 |
1 |
1 |
| 56 |
1 |
1 |
| 59 |
1 |
1 |
| 60 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 68 |
1 |
1 |
| 69 |
1 |
1 |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 86 |
1 |
1 |
| 89 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 94 |
1 |
1 |
| 95 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 101 |
1 |
1 |
| 102 |
1 |
1 |
| 103 |
1 |
1 |
| 104 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 120 |
1 |
1 |
| 130 |
1 |
1 |
| 131 |
1 |
1 |
| 132 |
1 |
1 |
| 142 |
1 |
1 |
| 143 |
1 |
1 |
| 144 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 159 |
1 |
1 |
| 160 |
1 |
1 |
| 171 |
1 |
1 |
| 172 |
1 |
1 |
| 182 |
1 |
1 |
| 183 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 187 |
1 |
1 |
| 207 |
1 |
1 |
| 276 |
1 |
1 |
| 277 |
1 |
1 |
| 279 |
1 |
1 |
| 280 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
| Total | Covered | Percent |
|---|
| Conditions | 26 | 24 | 92.31 |
| Logical | 26 | 24 | 92.31 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T4,T16,T6 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T4,T16,T6 |
| 1 | 1 | Covered | T4,T16,T6 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T1,T5 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
| Line No. | Total | Covered | Percent |
| Branches |
|
24 |
24 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
160 |
3 |
3 |
100.00 |
| TERNARY |
207 |
2 |
2 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 146 (full_wclk) ?
-2-: 146 ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T16,T6 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 160 (full_rclk) ?
-2-: 160 ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T16,T6 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 207 (empty_rclk) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 182 if (fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T16,T6 |
| 0 |
Covered |
T4,T5,T2 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1904520999 |
1904384551 |
0 |
0 |
| T1 |
1539 |
1473 |
0 |
0 |
| T2 |
111904 |
111896 |
0 |
0 |
| T3 |
552958 |
552902 |
0 |
0 |
| T4 |
154900 |
154823 |
0 |
0 |
| T5 |
6076 |
6013 |
0 |
0 |
| T9 |
414748 |
414743 |
0 |
0 |
| T12 |
55894 |
55810 |
0 |
0 |
| T13 |
15082 |
14982 |
0 |
0 |
| T16 |
545562 |
545505 |
0 |
0 |
| T39 |
1620 |
1540 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
379241653 |
379240139 |
0 |
0 |
| T2 |
590170 |
590169 |
0 |
0 |
| T3 |
262881 |
262880 |
0 |
0 |
| T4 |
417115 |
417114 |
0 |
0 |
| T5 |
1314 |
1313 |
0 |
0 |
| T9 |
774846 |
774845 |
0 |
0 |
| T10 |
18303 |
18302 |
0 |
0 |
| T12 |
51690 |
51689 |
0 |
0 |
| T13 |
2847 |
2846 |
0 |
0 |
| T14 |
33 |
32 |
0 |
0 |
| T16 |
126670 |
126669 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1616 |
1616 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T39 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 62 | 62 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
| ROUTINE | 230 | 7 | 7 | 100.00 |
| ROUTINE | 251 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 267 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 53 |
1 |
1 |
| 56 |
1 |
1 |
| 59 |
1 |
1 |
| 60 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 68 |
1 |
1 |
| 69 |
1 |
1 |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 86 |
1 |
1 |
| 89 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 94 |
1 |
1 |
| 95 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 101 |
1 |
1 |
| 102 |
1 |
1 |
| 103 |
1 |
1 |
| 104 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 120 |
1 |
1 |
| 130 |
1 |
1 |
| 131 |
1 |
1 |
| 132 |
1 |
1 |
| 142 |
1 |
1 |
| 143 |
1 |
1 |
| 144 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 159 |
1 |
1 |
| 160 |
1 |
1 |
| 171 |
1 |
1 |
| 172 |
1 |
1 |
| 182 |
1 |
1 |
| 183 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 187 |
1 |
1 |
| 207 |
1 |
1 |
| 230 |
1 |
1 |
| 232 |
1 |
1 |
| 235 |
1 |
1 |
| 236 |
1 |
1 |
| 239 |
1 |
1 |
| 240 |
1 |
1 |
| 243 |
1 |
1 |
| 251 |
1 |
1 |
| 252 |
1 |
1 |
| 253 |
1 |
1 |
| 255 |
1 |
1 |
| 256 |
1 |
1 |
| 257 |
1 |
1 |
| 259 |
1 |
1 |
| 260 |
1 |
1 |
| 262 |
1 |
1 |
| 267 |
1 |
1 |
| 269 |
1 |
1 |
| 271 |
1 |
1 |
| 272 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo
| Total | Covered | Percent |
|---|
| Conditions | 32 | 30 | 93.75 |
| Logical | 32 | 30 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T4,T16,T6 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T4,T16,T6 |
| 1 | 1 | Covered | T4,T16,T6 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T6,T43 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T6,T43 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T1,T5 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (7'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T6,T43 |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (7'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T6,T43 |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 232
EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 253
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T5 |
| 0 | 1 | Covered | T4,T16,T6 |
| 1 | 0 | Covered | T4,T16,T6 |
| 1 | 1 | Covered | T4,T16,T6 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
28 |
28 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
160 |
3 |
3 |
100.00 |
| TERNARY |
207 |
2 |
2 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
| TERNARY |
232 |
2 |
2 |
100.00 |
| IF |
256 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 146 (full_wclk) ?
-2-: 146 ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T6,T43 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 160 (full_rclk) ?
-2-: 160 ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T6,T43 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 207 (empty_rclk) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 182 if (fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T16,T6 |
| 0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 232 (decval[(PTR_WIDTH - 1)]) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T16,T6 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 256 if (grayval[(PTR_WIDTH - 1)])
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T16,T6 |
| 0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1904520999 |
1904384551 |
0 |
0 |
| T1 |
1539 |
1473 |
0 |
0 |
| T2 |
111904 |
111896 |
0 |
0 |
| T3 |
552958 |
552902 |
0 |
0 |
| T4 |
154900 |
154823 |
0 |
0 |
| T5 |
6076 |
6013 |
0 |
0 |
| T9 |
414748 |
414743 |
0 |
0 |
| T12 |
55894 |
55810 |
0 |
0 |
| T13 |
15082 |
14982 |
0 |
0 |
| T16 |
545562 |
545505 |
0 |
0 |
| T39 |
1620 |
1540 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
379241653 |
379240139 |
0 |
0 |
| T2 |
590170 |
590169 |
0 |
0 |
| T3 |
262881 |
262880 |
0 |
0 |
| T4 |
417115 |
417114 |
0 |
0 |
| T5 |
1314 |
1313 |
0 |
0 |
| T9 |
774846 |
774845 |
0 |
0 |
| T10 |
18303 |
18302 |
0 |
0 |
| T12 |
51690 |
51689 |
0 |
0 |
| T13 |
2847 |
2846 |
0 |
0 |
| T14 |
33 |
32 |
0 |
0 |
| T16 |
126670 |
126669 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1616 |
1616 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T39 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 62 | 62 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
| ROUTINE | 230 | 7 | 7 | 100.00 |
| ROUTINE | 251 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 267 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 53 |
1 |
1 |
| 56 |
1 |
1 |
| 59 |
1 |
1 |
| 60 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 68 |
1 |
1 |
| 69 |
1 |
1 |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 86 |
1 |
1 |
| 89 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 94 |
1 |
1 |
| 95 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 101 |
1 |
1 |
| 102 |
1 |
1 |
| 103 |
1 |
1 |
| 104 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 120 |
1 |
1 |
| 130 |
1 |
1 |
| 131 |
1 |
1 |
| 132 |
1 |
1 |
| 142 |
1 |
1 |
| 143 |
1 |
1 |
| 144 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 159 |
1 |
1 |
| 160 |
1 |
1 |
| 171 |
1 |
1 |
| 172 |
1 |
1 |
| 182 |
1 |
1 |
| 183 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 187 |
1 |
1 |
| 207 |
1 |
1 |
| 230 |
1 |
1 |
| 232 |
1 |
1 |
| 235 |
1 |
1 |
| 236 |
1 |
1 |
| 239 |
1 |
1 |
| 240 |
1 |
1 |
| 243 |
1 |
1 |
| 251 |
1 |
1 |
| 252 |
1 |
1 |
| 253 |
1 |
1 |
| 255 |
1 |
1 |
| 256 |
1 |
1 |
| 257 |
1 |
1 |
| 259 |
1 |
1 |
| 260 |
1 |
1 |
| 262 |
1 |
1 |
| 267 |
1 |
1 |
| 269 |
1 |
1 |
| 271 |
1 |
1 |
| 272 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo
| Total | Covered | Percent |
|---|
| Conditions | 32 | 30 | 93.75 |
| Logical | 32 | 30 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T5 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T4,T16,T6 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T4,T16,T6 |
| 1 | 1 | Covered | T4,T16,T6 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T1,T5 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (5'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (5'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T16,T6 |
| 1 | Covered | T4,T1,T5 |
LINE 232
EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T5 |
| 1 | Covered | T4,T16,T6 |
LINE 253
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T1,T5 |
| 0 | 1 | Covered | T4,T16,T6 |
| 1 | 0 | Covered | T4,T16,T6 |
| 1 | 1 | Covered | T4,T16,T6 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
28 |
28 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
160 |
3 |
3 |
100.00 |
| TERNARY |
207 |
2 |
2 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
| TERNARY |
232 |
2 |
2 |
100.00 |
| IF |
256 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 146 (full_wclk) ?
-2-: 146 ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T16,T6 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 160 (full_rclk) ?
-2-: 160 ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T16,T6 |
| 0 |
1 |
Covered |
T4,T1,T5 |
| 0 |
0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 207 (empty_rclk) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T16,T6 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T16 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T1,T5 |
| 0 |
1 |
Covered |
T4,T16,T6 |
| 0 |
0 |
Covered |
T4,T5,T16 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T1,T5 |
| 0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 182 if (fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T16,T6 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 232 (decval[(PTR_WIDTH - 1)]) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T16,T6 |
| 0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 256 if (grayval[(PTR_WIDTH - 1)])
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T16,T6 |
| 0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
379242896 |
35145536 |
0 |
0 |
| T1 |
1 |
0 |
0 |
0 |
| T2 |
590170 |
0 |
0 |
0 |
| T3 |
262882 |
0 |
0 |
0 |
| T4 |
417116 |
411917 |
0 |
0 |
| T5 |
1315 |
994 |
0 |
0 |
| T6 |
0 |
692876 |
0 |
0 |
| T7 |
0 |
67298 |
0 |
0 |
| T8 |
0 |
100749 |
0 |
0 |
| T9 |
774846 |
0 |
0 |
0 |
| T12 |
51691 |
0 |
0 |
0 |
| T13 |
2847 |
0 |
0 |
0 |
| T16 |
126670 |
121149 |
0 |
0 |
| T33 |
0 |
1136 |
0 |
0 |
| T34 |
0 |
2367 |
0 |
0 |
| T39 |
1 |
0 |
0 |
0 |
| T42 |
0 |
150212 |
0 |
0 |
| T43 |
0 |
323765 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1904520999 |
94229523 |
0 |
0 |
| T1 |
1539 |
0 |
0 |
0 |
| T2 |
111904 |
3378 |
0 |
0 |
| T3 |
552958 |
0 |
0 |
0 |
| T4 |
154900 |
136600 |
0 |
0 |
| T5 |
6076 |
3010 |
0 |
0 |
| T6 |
0 |
969729 |
0 |
0 |
| T9 |
414748 |
5381 |
0 |
0 |
| T12 |
55894 |
0 |
0 |
0 |
| T13 |
15082 |
0 |
0 |
0 |
| T16 |
545562 |
486258 |
0 |
0 |
| T33 |
0 |
256 |
0 |
0 |
| T39 |
1620 |
0 |
0 |
0 |
| T40 |
0 |
281 |
0 |
0 |
| T41 |
0 |
60 |
0 |
0 |
| T111 |
0 |
338 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1616 |
1616 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T39 |
1 |
1 |
0 |
0 |