Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T2 |
0 | 1 | Covered | T10,T15,T35 |
1 | 0 | Covered | T10,T15,T35 |
1 | 1 | Covered | T10,T15,T35 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T10,T15,T35 |
1 | 0 | Covered | T10,T15,T35 |
1 | 1 | Covered | T10,T15,T35 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2922 |
0 |
0 |
T6 |
1708635 |
11 |
0 |
0 |
T7 |
645015 |
8 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T10 |
44680 |
7 |
0 |
0 |
T14 |
3196 |
0 |
0 |
0 |
T17 |
3222 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
22 |
0 |
0 |
T23 |
300568 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T28 |
0 |
11 |
0 |
0 |
T35 |
113298 |
7 |
0 |
0 |
T36 |
44508 |
0 |
0 |
0 |
T37 |
2525001 |
0 |
0 |
0 |
T38 |
497337 |
0 |
0 |
0 |
T40 |
3414 |
0 |
0 |
0 |
T41 |
2550 |
0 |
0 |
0 |
T42 |
0 |
12 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
7 |
0 |
0 |
T48 |
0 |
15 |
0 |
0 |
T49 |
13011 |
0 |
0 |
0 |
T64 |
929 |
0 |
0 |
0 |
T65 |
926 |
0 |
0 |
0 |
T171 |
0 |
7 |
0 |
0 |
T172 |
0 |
7 |
0 |
0 |
T173 |
0 |
4 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T175 |
0 |
7 |
0 |
0 |
T176 |
0 |
7 |
0 |
0 |
T177 |
0 |
11 |
0 |
0 |
T178 |
0 |
9 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1467766662 |
2922 |
0 |
0 |
T6 |
337407 |
11 |
0 |
0 |
T7 |
921396 |
8 |
0 |
0 |
T8 |
165610 |
6 |
0 |
0 |
T10 |
36606 |
7 |
0 |
0 |
T14 |
66 |
0 |
0 |
0 |
T17 |
2 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
22 |
0 |
0 |
T23 |
110859 |
0 |
0 |
0 |
T24 |
48652 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T28 |
0 |
11 |
0 |
0 |
T35 |
51366 |
7 |
0 |
0 |
T36 |
7107 |
0 |
0 |
0 |
T37 |
659136 |
0 |
0 |
0 |
T38 |
1052742 |
0 |
0 |
0 |
T42 |
0 |
12 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
7 |
0 |
0 |
T48 |
0 |
15 |
0 |
0 |
T49 |
10197 |
0 |
0 |
0 |
T171 |
0 |
7 |
0 |
0 |
T172 |
0 |
7 |
0 |
0 |
T173 |
0 |
4 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T175 |
0 |
7 |
0 |
0 |
T176 |
0 |
7 |
0 |
0 |
T177 |
0 |
11 |
0 |
0 |
T178 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_rxf_overflow
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_rxf_overflow
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T2 |
0 | 1 | Covered | T15,T37,T8 |
1 | 0 | Covered | T15,T37,T8 |
1 | 1 | Covered | T15,T37,T8 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T15,T37,T8 |
1 | 0 | Covered | T15,T37,T8 |
1 | 1 | Covered | T15,T37,T8 |
Branch Coverage for Instance : tb.dut.u_rxf_overflow
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_rxf_overflow
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
568087148 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165020134 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_txf_underflow
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_txf_underflow
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T2 |
0 | 1 | Covered | T15,T37,T8 |
1 | 0 | Covered | T15,T37,T8 |
1 | 1 | Covered | T15,T37,T8 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T15,T37,T8 |
1 | 0 | Covered | T15,T37,T8 |
1 | 1 | Covered | T15,T37,T8 |
Branch Coverage for Instance : tb.dut.u_txf_underflow
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_txf_underflow
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
568087148 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165021569 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T2 |
0 | 1 | Covered | T10,T35,T44 |
1 | 0 | Covered | T10,T35,T44 |
1 | 1 | Covered | T10,T35,T44 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T10,T35,T44 |
1 | 0 | Covered | T10,T35,T44 |
1 | 1 | Covered | T10,T35,T44 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1904520999 |
319 |
0 |
0 |
T6 |
569545 |
0 |
0 |
0 |
T10 |
22340 |
2 |
0 |
0 |
T14 |
1598 |
0 |
0 |
0 |
T17 |
1611 |
0 |
0 |
0 |
T35 |
37766 |
2 |
0 |
0 |
T36 |
14836 |
0 |
0 |
0 |
T37 |
841667 |
0 |
0 |
0 |
T38 |
165779 |
0 |
0 |
0 |
T40 |
1707 |
0 |
0 |
0 |
T41 |
1275 |
0 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T171 |
0 |
2 |
0 |
0 |
T172 |
0 |
2 |
0 |
0 |
T173 |
0 |
2 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
2 |
0 |
0 |
T176 |
0 |
2 |
0 |
0 |
T178 |
0 |
9 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
379241653 |
319 |
0 |
0 |
T6 |
112469 |
0 |
0 |
0 |
T10 |
18303 |
2 |
0 |
0 |
T14 |
33 |
0 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T23 |
36953 |
0 |
0 |
0 |
T35 |
17122 |
2 |
0 |
0 |
T36 |
2369 |
0 |
0 |
0 |
T37 |
219712 |
0 |
0 |
0 |
T38 |
350914 |
0 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T49 |
3399 |
0 |
0 |
0 |
T171 |
0 |
2 |
0 |
0 |
T172 |
0 |
2 |
0 |
0 |
T173 |
0 |
2 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
2 |
0 |
0 |
T176 |
0 |
2 |
0 |
0 |
T178 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T2 |
0 | 1 | Covered | T10,T35,T44 |
1 | 0 | Covered | T10,T35,T44 |
1 | 1 | Covered | T10,T35,T44 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T10,T35,T44 |
1 | 0 | Covered | T10,T35,T44 |
1 | 1 | Covered | T10,T35,T44 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1904520999 |
520 |
0 |
0 |
T6 |
569545 |
0 |
0 |
0 |
T10 |
22340 |
5 |
0 |
0 |
T14 |
1598 |
0 |
0 |
0 |
T17 |
1611 |
0 |
0 |
0 |
T35 |
37766 |
5 |
0 |
0 |
T36 |
14836 |
0 |
0 |
0 |
T37 |
841667 |
0 |
0 |
0 |
T38 |
165779 |
0 |
0 |
0 |
T40 |
1707 |
0 |
0 |
0 |
T41 |
1275 |
0 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
T171 |
0 |
5 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
T173 |
0 |
2 |
0 |
0 |
T174 |
0 |
5 |
0 |
0 |
T175 |
0 |
5 |
0 |
0 |
T176 |
0 |
5 |
0 |
0 |
T177 |
0 |
11 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
379241653 |
520 |
0 |
0 |
T6 |
112469 |
0 |
0 |
0 |
T10 |
18303 |
5 |
0 |
0 |
T14 |
33 |
0 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T23 |
36953 |
0 |
0 |
0 |
T35 |
17122 |
5 |
0 |
0 |
T36 |
2369 |
0 |
0 |
0 |
T37 |
219712 |
0 |
0 |
0 |
T38 |
350914 |
0 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
T49 |
3399 |
0 |
0 |
0 |
T171 |
0 |
5 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
T173 |
0 |
2 |
0 |
0 |
T174 |
0 |
5 |
0 |
0 |
T175 |
0 |
5 |
0 |
0 |
T176 |
0 |
5 |
0 |
0 |
T177 |
0 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T2 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T5,T2 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T5 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1904520999 |
2083 |
0 |
0 |
T6 |
569545 |
11 |
0 |
0 |
T7 |
645015 |
8 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
22 |
0 |
0 |
T23 |
300568 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T28 |
0 |
11 |
0 |
0 |
T35 |
37766 |
0 |
0 |
0 |
T36 |
14836 |
0 |
0 |
0 |
T37 |
841667 |
0 |
0 |
0 |
T38 |
165779 |
0 |
0 |
0 |
T42 |
0 |
12 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T48 |
0 |
15 |
0 |
0 |
T49 |
13011 |
0 |
0 |
0 |
T64 |
929 |
0 |
0 |
0 |
T65 |
926 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
379241653 |
2083 |
0 |
0 |
T6 |
112469 |
11 |
0 |
0 |
T7 |
921396 |
8 |
0 |
0 |
T8 |
165610 |
6 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
22 |
0 |
0 |
T23 |
36953 |
0 |
0 |
0 |
T24 |
48652 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
T28 |
0 |
11 |
0 |
0 |
T35 |
17122 |
0 |
0 |
0 |
T36 |
2369 |
0 |
0 |
0 |
T37 |
219712 |
0 |
0 |
0 |
T38 |
350914 |
0 |
0 |
0 |
T42 |
0 |
12 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T48 |
0 |
15 |
0 |
0 |
T49 |
3399 |
0 |
0 |
0 |