Unified Coverage Report :: Module Instance :: tb.dut.u_sys_sram_arbiter.u_req_fifo

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.85	100.00	65.38			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	17	65.38
Logical	26	17	65.38
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T1,T5
0	0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T5
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1904520999	4800939	0	0
DepthKnown_A	1904520999	1904386347	0	0
RvalidKnown_A	1904520999	1904386347	0	0
WreadyKnown_A	1904520999	1904386347	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1904520999	4800939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	4800939	0	0
T2	111904	12521	0	0
T3	552958	8215	0	0
T6	0	2200	0	0
T7	0	250	0	0
T9	414748	20297	0	0
T10	22340	0	0	0
T12	55894	0	0	0
T13	15082	80	0	0
T15	0	20422	0	0
T16	545562	0	0	0
T36	0	74	0	0
T37	0	6859	0	0
T38	0	10966	0	0
T39	1620	0	0	0
T40	1707	0	0	0
T41	1275	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	1904386347	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	1904386347	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	1904386347	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	4800939	0	0
T2	111904	12521	0	0
T3	552958	8215	0	0
T6	0	2200	0	0
T7	0	250	0	0
T9	414748	20297	0	0
T10	22340	0	0	0
T12	55894	0	0	0
T13	15082	80	0	0
T15	0	20422	0	0
T16	545562	0	0	0
T36	0	74	0	0
T37	0	6859	0	0
T38	0	10966	0	0
T39	1620	0	0	0
T40	1707	0	0	0
T41	1275	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1907094280	239915220	0	0
DepthKnown_A	1907094280	1906911297	0	0
RvalidKnown_A	1907094280	1906911297	0	0
WreadyKnown_A	1907094280	1906911297	0	0
gen_passthru_fifo.paramCheckPass	1791	1791	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	239915220	0	0
T1	1539	18	0	0
T2	111904	569933	0	0
T3	552958	94052	0	0
T4	154900	8489	0	0
T5	6076	45	0	0
T9	414748	531988	0	0
T12	55894	2154	0	0
T13	15082	505	0	0
T16	545562	19354	0	0
T39	1620	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791	1791	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1907094280	272538363	0	0
DepthKnown_A	1907094280	1906911297	0	0
RvalidKnown_A	1907094280	1906911297	0	0
WreadyKnown_A	1907094280	1906911297	0	0
gen_passthru_fifo.paramCheckPass	1791	1791	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	272538363	0	0
T1	1539	88	0	0
T2	111904	488349	0	0
T3	552958	87562	0	0
T4	154900	25345	0	0
T5	6076	45	0	0
T9	414748	180903	0	0
T12	55894	1370	0	0
T13	15082	505	0	0
T16	545562	19326	0	0
T39	1620	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791	1791	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1907094280	13376724	0	0
DepthKnown_A	1907094280	1906911297	0	0
RvalidKnown_A	1907094280	1906911297	0	0
WreadyKnown_A	1907094280	1906911297	0	0
gen_passthru_fifo.paramCheckPass	1791	1791	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	13376724	0	0
T1	1539	2	0	0
T2	111904	26578	0	0
T3	552958	16929	0	0
T5	6076	0	0	0
T6	0	20828	0	0
T9	414748	46011	0	0
T10	22340	2052	0	0
T12	55894	2047	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791	1791	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1907094280	22036059	0	0
DepthKnown_A	1907094280	1906911297	0	0
RvalidKnown_A	1907094280	1906911297	0	0
WreadyKnown_A	1907094280	1906911297	0	0
gen_passthru_fifo.paramCheckPass	1791	1791	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	22036059	0	0
T1	1539	13	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	32180	0	0
T9	414748	191699	0	0
T10	22340	1029	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791	1791	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1907094280	222148753	0	0
DepthKnown_A	1907094280	1906911297	0	0
RvalidKnown_A	1907094280	1906911297	0	0
WreadyKnown_A	1907094280	1906911297	0	0
gen_passthru_fifo.paramCheckPass	1791	1791	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	222148753	0	0
T1	1539	16	0	0
T2	111904	523961	0	0
T3	552958	75459	0	0
T4	154900	8489	0	0
T5	6076	45	0	0
T9	414748	437325	0	0
T12	55894	107	0	0
T13	15082	345	0	0
T16	545562	19354	0	0
T39	1620	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791	1791	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1907094280	250502304	0	0
DepthKnown_A	1907094280	1906911297	0	0
RvalidKnown_A	1907094280	1906911297	0	0
WreadyKnown_A	1907094280	1906911297	0	0
gen_passthru_fifo.paramCheckPass	1791	1791	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	250502304	0	0
T1	1539	75	0	0
T2	111904	463307	0	0
T3	552958	71132	0	0
T4	154900	25345	0	0
T5	6076	45	0	0
T9	414748	161733	0	0
T12	55894	346	0	0
T13	15082	345	0	0
T16	545562	19326	0	0
T39	1620	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907094280	1906911297	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791	1791	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0