Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.53	100.00

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	4848	4848	0	0
GntImpliesReady_A	2147483647	21458286	0	0
GntImpliesValid_A	2147483647	21458286	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	21458286	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	0	0	0
ReadyAndValidImplyGrant_A	2147483647	21458286	0	0
ReqAndReadyImplyGrant_A	2147483647	21458286	0	0
ReqImpliesValid_A	2147483647	21458286	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	1051	0	2337
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	21458286	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2994	2929	0	0
T2	813968	624462	0	0
T3	1368728	1368672	0	0
T4	154900	154824	0	0
T5	7390	6014	0	0
T6	112469	841823	0	0
T9	1604336	1478989	0	0
T10	36606	36528	0	0
T11	0	190020	0	0
T12	159274	159191	0	0
T13	32895	32786	0	0
T14	1529	1528	0	0
T15	0	523945	0	0
T16	798902	545506	0	0
T17	1	1515	0	0
T39	1620	1541	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4848	4848	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T9	3	3	0	0
T12	3	3	0	0
T13	3	3	0	0
T16	3	3	0	0
T39	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21458286	0	0
T1	2994	4	0	0
T2	223798	50084	0	0
T3	1105847	32860	0	0
T5	7390	0	0	0
T6	112469	19867	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T9	829490	81188	0	0
T10	40643	1024	0	0
T12	107584	1024	0	0
T13	30048	320	0	0
T14	1496	5	0	0
T15	0	38900	0	0
T16	672232	0	0	0
T17	0	6	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	148	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T39	1620	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21458286	0	0
T1	2994	4	0	0
T2	223798	50084	0	0
T3	1105847	32860	0	0
T5	7390	0	0	0
T6	112469	19867	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T9	829490	81188	0	0
T10	40643	1024	0	0
T12	107584	1024	0	0
T13	30048	320	0	0
T14	1496	5	0	0
T15	0	38900	0	0
T16	672232	0	0	0
T17	0	6	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	148	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T39	1620	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2994	2929	0	0
T2	813968	624462	0	0
T3	1368728	1368672	0	0
T4	154900	154824	0	0
T5	7390	6014	0	0
T6	112469	841823	0	0
T9	1604336	1478989	0	0
T10	36606	36528	0	0
T11	0	190020	0	0
T12	159274	159191	0	0
T13	32895	32786	0	0
T14	1529	1528	0	0
T15	0	523945	0	0
T16	798902	545506	0	0
T17	1	1515	0	0
T39	1620	1541	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2994	2929	0	0
T2	813968	624462	0	0
T3	1368728	1368672	0	0
T4	154900	154824	0	0
T5	7390	6014	0	0
T6	112469	841823	0	0
T9	1604336	1478989	0	0
T10	36606	36528	0	0
T11	0	190020	0	0
T12	159274	159191	0	0
T13	32895	32786	0	0
T14	1529	1528	0	0
T15	0	523945	0	0
T16	798902	545506	0	0
T17	1	1515	0	0
T39	1620	1541	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21458286	0	0
T1	2994	4	0	0
T2	223798	50084	0	0
T3	1105847	32860	0	0
T5	7390	0	0	0
T6	112469	19867	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T9	829490	81188	0	0
T10	40643	1024	0	0
T12	107584	1024	0	0
T13	30048	320	0	0
T14	1496	5	0	0
T15	0	38900	0	0
T16	672232	0	0	0
T17	0	6	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	148	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T39	1620	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21458286	0	0
T1	2994	4	0	0
T2	223798	50084	0	0
T3	1105847	32860	0	0
T5	7390	0	0	0
T6	112469	19867	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T9	829490	81188	0	0
T10	40643	1024	0	0
T12	107584	1024	0	0
T13	30048	320	0	0
T14	1496	5	0	0
T15	0	38900	0	0
T16	672232	0	0	0
T17	0	6	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	148	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T39	1620	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21458286	0	0
T1	2994	4	0	0
T2	223798	50084	0	0
T3	1105847	32860	0	0
T5	7390	0	0	0
T6	112469	19867	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T9	829490	81188	0	0
T10	40643	1024	0	0
T12	107584	1024	0	0
T13	30048	320	0	0
T14	1496	5	0	0
T15	0	38900	0	0
T16	672232	0	0	0
T17	0	6	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	148	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T39	1620	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21458286	0	0
T1	2994	4	0	0
T2	223798	50084	0	0
T3	1105847	32860	0	0
T5	7390	0	0	0
T6	112469	19867	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T9	829490	81188	0	0
T10	40643	1024	0	0
T12	107584	1024	0	0
T13	30048	320	0	0
T14	1496	5	0	0
T15	0	38900	0	0
T16	672232	0	0	0
T17	0	6	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	148	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T39	1620	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1051	0	2337
T6	498389	3	0	1
T7	921396	0	0	0
T8	0	5	0	0
T11	190220	0	0	0
T15	868852	9	0	1
T18	5189	0	0	0
T19	220957	0	0	0
T23	0	0	0	0
T33	1152	0	0	0
T34	2467	0	0	0
T35	17122	0	0	0
T36	14761	0	0	1
T37	0	0	0	1
T38	0	0	0	1
T49	0	0	0	1
T50	0	299	0	1
T51	0	10	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	0	0	1
T58	0	0	0	1
T59	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2994	2929	0	0
T2	813968	624462	0	0
T3	1368728	1368672	0	0
T4	154900	154824	0	0
T5	7390	6014	0	0
T6	112469	841823	0	0
T9	1604336	1478989	0	0
T10	36606	36528	0	0
T11	0	190020	0	0
T12	159274	159191	0	0
T13	32895	32786	0	0
T14	1529	1528	0	0
T15	0	523945	0	0
T16	798902	545506	0	0
T17	1	1515	0	0
T39	1620	1541	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21458286	0	0
T1	2994	4	0	0
T2	223798	50084	0	0
T3	1105847	32860	0	0
T5	7390	0	0	0
T6	112469	19867	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T9	829490	81188	0	0
T10	40643	1024	0	0
T12	107584	1024	0	0
T13	30048	320	0	0
T14	1496	5	0	0
T15	0	38900	0	0
T16	672232	0	0	0
T17	0	6	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	148	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T39	1620	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Unreachable
1	1	Covered	T6,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T6,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379241653	327189221	0	0
CheckNGreaterZero_A	1616	1616	0	0
GntImpliesReady_A	379241653	559158	0	0
GntImpliesValid_A	379241653	559158	0	0
GrantKnown_A	379241653	327189221	0	0
IdxKnown_A	379241653	327189221	0	0
IndexIsCorrect_A	379241653	559158	0	0
LockArbDecision_A	379241653	0	0	0
NoReadyValidNoGrant_A	379241653	0	0	0
ReadyAndValidImplyGrant_A	379241653	559158	0	0
ReqAndReadyImplyGrant_A	379241653	559158	0	0
ReqImpliesValid_A	379241653	559158	0	0
ReqStaysHighUntilGranted0_M	379241653	0	0	0
RoundRobin_A	379241653	0	0	0
ValidKnown_A	379241653	327189221	0	0
gen_data_port_assertion.DataFlow_A	379241653	559158	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	327189221	0	0
T2	590170	400672	0	0
T3	262881	262880	0	0
T6	112469	414458	0	0
T9	774846	649504	0	0
T10	18303	18264	0	0
T11	0	190020	0	0
T12	51690	51690	0	0
T13	2847	2837	0	0
T14	33	32	0	0
T15	0	523945	0	0
T16	126670	0	0	0
T17	1	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616	1616	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	559158	0	0
T6	112469	1940	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	0	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	559158	0	0
T6	112469	1940	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	0	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	327189221	0	0
T2	590170	400672	0	0
T3	262881	262880	0	0
T6	112469	414458	0	0
T9	774846	649504	0	0
T10	18303	18264	0	0
T11	0	190020	0	0
T12	51690	51690	0	0
T13	2847	2837	0	0
T14	33	32	0	0
T15	0	523945	0	0
T16	126670	0	0	0
T17	1	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	327189221	0	0
T2	590170	400672	0	0
T3	262881	262880	0	0
T6	112469	414458	0	0
T9	774846	649504	0	0
T10	18303	18264	0	0
T11	0	190020	0	0
T12	51690	51690	0	0
T13	2847	2837	0	0
T14	33	32	0	0
T15	0	523945	0	0
T16	126670	0	0	0
T17	1	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	559158	0	0
T6	112469	1940	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	0	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	559158	0	0
T6	112469	1940	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	0	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	559158	0	0
T6	112469	1940	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	0	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	559158	0	0
T6	112469	1940	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	0	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	327189221	0	0
T2	590170	400672	0	0
T3	262881	262880	0	0
T6	112469	414458	0	0
T9	774846	649504	0	0
T10	18303	18264	0	0
T11	0	190020	0	0
T12	51690	51690	0	0
T13	2847	2837	0	0
T14	33	32	0	0
T15	0	523945	0	0
T16	126670	0	0	0
T17	1	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379241653	559158	0	0
T6	112469	1940	0	0
T7	921396	1217	0	0
T8	165610	8623	0	0
T20	0	514	0	0
T21	0	9765	0	0
T23	36953	0	0	0
T24	48652	0	0	0
T27	0	2828	0	0
T28	0	4045	0	0
T35	17122	0	0	0
T36	2369	0	0	0
T37	219712	0	0	0
T38	350914	0	0	0
T42	0	3750	0	0
T43	0	138	0	0
T48	0	1486	0	0
T49	3399	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1904520999	1904386347	0	0
CheckNGreaterZero_A	1616	1616	0	0
GntImpliesReady_A	1904520999	11632478	0	0
GntImpliesValid_A	1904520999	11632478	0	0
GrantKnown_A	1904520999	1904386347	0	0
IdxKnown_A	1904520999	1904386347	0	0
IndexIsCorrect_A	1904520999	11632478	0	0
LockArbDecision_A	1904520999	0	0	0
NoReadyValidNoGrant_A	1904520999	0	0	0
ReadyAndValidImplyGrant_A	1904520999	11632478	0	0
ReqAndReadyImplyGrant_A	1904520999	11632478	0	0
ReqImpliesValid_A	1904520999	11632478	0	0
ReqStaysHighUntilGranted0_M	1904520999	0	0	0
RoundRobin_A	1904520999	0	0	1616
ValidKnown_A	1904520999	1904386347	0	0
gen_data_port_assertion.DataFlow_A	1904520999	11632478	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	1904386347	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616	1616	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	11632478	0	0
T1	1539	2	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	14269	0	0
T9	414748	40594	0	0
T10	22340	1024	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	11632478	0	0
T1	1539	2	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	14269	0	0
T9	414748	40594	0	0
T10	22340	1024	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	1904386347	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	1904386347	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	11632478	0	0
T1	1539	2	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	14269	0	0
T9	414748	40594	0	0
T10	22340	1024	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	11632478	0	0
T1	1539	2	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	14269	0	0
T9	414748	40594	0	0
T10	22340	1024	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	11632478	0	0
T1	1539	2	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	14269	0	0
T9	414748	40594	0	0
T10	22340	1024	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	11632478	0	0
T1	1539	2	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	14269	0	0
T9	414748	40594	0	0
T10	22340	1024	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	0	0	1616

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	1904386347	0	0
T1	1539	1474	0	0
T2	111904	111896	0	0
T3	552958	552903	0	0
T4	154900	154824	0	0
T5	6076	6014	0	0
T9	414748	414743	0	0
T12	55894	55811	0	0
T13	15082	14983	0	0
T16	545562	545506	0	0
T39	1620	1541	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904520999	11632478	0	0
T1	1539	2	0	0
T2	111904	25042	0	0
T3	552958	16430	0	0
T5	6076	0	0	0
T6	0	14269	0	0
T9	414748	40594	0	0
T10	22340	1024	0	0
T12	55894	1024	0	0
T13	15082	160	0	0
T14	0	2	0	0
T16	545562	0	0	0
T17	0	4	0	0
T39	1620	0	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1506466077	1469520783	0	0
CheckNGreaterZero_A	1616	1616	0	0
GntImpliesReady_A	1506466077	9266650	0	0
GntImpliesValid_A	1506466077	9266650	0	0
GrantKnown_A	1506466077	1469520783	0	0
IdxKnown_A	1506466077	1469520783	0	0
IndexIsCorrect_A	1506466077	9266650	0	0
LockArbDecision_A	1506466077	0	0	0
NoReadyValidNoGrant_A	1506466077	0	0	0
ReadyAndValidImplyGrant_A	1506466077	9266650	0	0
ReqAndReadyImplyGrant_A	1506466077	9266650	0	0
ReqImpliesValid_A	1506466077	9266650	0	0
ReqStaysHighUntilGranted0_M	1506466077	0	0	0
RoundRobin_A	1506466077	1051	0	721
ValidKnown_A	1506466077	1469520783	0	0
gen_data_port_assertion.DataFlow_A	1506466077	9266650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	1469520783	0	0
T1	1455	1455	0	0
T2	111894	111894	0	0
T3	552889	552889	0	0
T5	1314	0	0	0
T6	0	427365	0	0
T9	414742	414742	0	0
T10	18303	18264	0	0
T12	51690	51690	0	0
T13	14966	14966	0	0
T14	1496	1496	0	0
T16	126670	0	0	0
T17	0	1515	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616	1616	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	9266650	0	0
T1	1455	2	0	0
T2	111894	25042	0	0
T3	552889	16430	0	0
T5	1314	0	0	0
T6	0	3658	0	0
T9	414742	40594	0	0
T10	18303	0	0	0
T12	51690	0	0	0
T13	14966	160	0	0
T14	1496	3	0	0
T15	0	38900	0	0
T16	126670	0	0	0
T17	0	2	0	0
T36	0	148	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	9266650	0	0
T1	1455	2	0	0
T2	111894	25042	0	0
T3	552889	16430	0	0
T5	1314	0	0	0
T6	0	3658	0	0
T9	414742	40594	0	0
T10	18303	0	0	0
T12	51690	0	0	0
T13	14966	160	0	0
T14	1496	3	0	0
T15	0	38900	0	0
T16	126670	0	0	0
T17	0	2	0	0
T36	0	148	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	1469520783	0	0
T1	1455	1455	0	0
T2	111894	111894	0	0
T3	552889	552889	0	0
T5	1314	0	0	0
T6	0	427365	0	0
T9	414742	414742	0	0
T10	18303	18264	0	0
T12	51690	51690	0	0
T13	14966	14966	0	0
T14	1496	1496	0	0
T16	126670	0	0	0
T17	0	1515	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	1469520783	0	0
T1	1455	1455	0	0
T2	111894	111894	0	0
T3	552889	552889	0	0
T5	1314	0	0	0
T6	0	427365	0	0
T9	414742	414742	0	0
T10	18303	18264	0	0
T12	51690	51690	0	0
T13	14966	14966	0	0
T14	1496	1496	0	0
T16	126670	0	0	0
T17	0	1515	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	9266650	0	0
T1	1455	2	0	0
T2	111894	25042	0	0
T3	552889	16430	0	0
T5	1314	0	0	0
T6	0	3658	0	0
T9	414742	40594	0	0
T10	18303	0	0	0
T12	51690	0	0	0
T13	14966	160	0	0
T14	1496	3	0	0
T15	0	38900	0	0
T16	126670	0	0	0
T17	0	2	0	0
T36	0	148	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	9266650	0	0
T1	1455	2	0	0
T2	111894	25042	0	0
T3	552889	16430	0	0
T5	1314	0	0	0
T6	0	3658	0	0
T9	414742	40594	0	0
T10	18303	0	0	0
T12	51690	0	0	0
T13	14966	160	0	0
T14	1496	3	0	0
T15	0	38900	0	0
T16	126670	0	0	0
T17	0	2	0	0
T36	0	148	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	9266650	0	0
T1	1455	2	0	0
T2	111894	25042	0	0
T3	552889	16430	0	0
T5	1314	0	0	0
T6	0	3658	0	0
T9	414742	40594	0	0
T10	18303	0	0	0
T12	51690	0	0	0
T13	14966	160	0	0
T14	1496	3	0	0
T15	0	38900	0	0
T16	126670	0	0	0
T17	0	2	0	0
T36	0	148	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	9266650	0	0
T1	1455	2	0	0
T2	111894	25042	0	0
T3	552889	16430	0	0
T5	1314	0	0	0
T6	0	3658	0	0
T9	414742	40594	0	0
T10	18303	0	0	0
T12	51690	0	0	0
T13	14966	160	0	0
T14	1496	3	0	0
T15	0	38900	0	0
T16	126670	0	0	0
T17	0	2	0	0
T36	0	148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	1051	0	721
T6	498389	3	0	1
T7	921396	0	0	0
T8	0	5	0	0
T11	190220	0	0	0
T15	868852	9	0	1
T18	5189	0	0	0
T19	220957	0	0	0
T23	0	0	0	0
T33	1152	0	0	0
T34	2467	0	0	0
T35	17122	0	0	0
T36	14761	0	0	1
T37	0	0	0	1
T38	0	0	0	1
T49	0	0	0	1
T50	0	299	0	1
T51	0	10	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	0	0	1
T58	0	0	0	1
T59	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	1469520783	0	0
T1	1455	1455	0	0
T2	111894	111894	0	0
T3	552889	552889	0	0
T5	1314	0	0	0
T6	0	427365	0	0
T9	414742	414742	0	0
T10	18303	18264	0	0
T12	51690	51690	0	0
T13	14966	14966	0	0
T14	1496	1496	0	0
T16	126670	0	0	0
T17	0	1515	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506466077	9266650	0	0
T1	1455	2	0	0
T2	111894	25042	0	0
T3	552889	16430	0	0
T5	1314	0	0	0
T6	0	3658	0	0
T9	414742	40594	0	0
T10	18303	0	0	0
T12	51690	0	0	0
T13	14966	160	0	0
T14	1496	3	0	0
T15	0	38900	0	0
T16	126670	0	0	0
T17	0	2	0	0
T36	0	148	0	0