Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.10 99.01 96.35 98.63 92.06 98.05 95.86 99.76


Total test records in report: 1791
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T1754 /workspace/coverage/default/6.spi_device_alert_test.2026791104 Dec 24 01:54:19 PM PST 23 Dec 24 01:54:27 PM PST 23 57191679 ps
T329 /workspace/coverage/default/44.spi_device_flash_all.439358538 Dec 24 01:57:53 PM PST 23 Dec 24 01:59:14 PM PST 23 47511217280 ps
T1755 /workspace/coverage/default/42.spi_device_flash_and_tpm.4153657408 Dec 24 01:57:36 PM PST 23 Dec 24 02:06:08 PM PST 23 187015137396 ps
T1756 /workspace/coverage/default/49.spi_device_abort.3599492123 Dec 24 01:58:20 PM PST 23 Dec 24 01:58:23 PM PST 23 42095829 ps
T1757 /workspace/coverage/default/30.spi_device_intercept.3773365246 Dec 24 01:56:39 PM PST 23 Dec 24 01:56:48 PM PST 23 1181527363 ps
T1758 /workspace/coverage/default/34.spi_device_alert_test.3985138367 Dec 24 01:56:58 PM PST 23 Dec 24 01:57:11 PM PST 23 14704471 ps
T1759 /workspace/coverage/default/27.spi_device_intercept.4222836598 Dec 24 01:56:20 PM PST 23 Dec 24 01:56:28 PM PST 23 7733773345 ps
T1760 /workspace/coverage/default/34.spi_device_csb_read.1030093365 Dec 24 01:56:57 PM PST 23 Dec 24 01:57:07 PM PST 23 17655690 ps
T1761 /workspace/coverage/default/25.spi_device_dummy_item_extra_dly.4161905203 Dec 24 01:58:46 PM PST 23 Dec 24 02:00:44 PM PST 23 84625570790 ps
T1762 /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.410350238 Dec 24 01:57:14 PM PST 23 Dec 24 01:57:22 PM PST 23 19195631 ps
T1763 /workspace/coverage/default/1.spi_device_upload.620669958 Dec 24 01:53:56 PM PST 23 Dec 24 01:54:02 PM PST 23 515190088 ps
T1764 /workspace/coverage/default/37.spi_device_alert_test.509597650 Dec 24 01:57:14 PM PST 23 Dec 24 01:57:22 PM PST 23 161326315 ps
T1765 /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1284760170 Dec 24 01:56:55 PM PST 23 Dec 24 01:57:30 PM PST 23 136630719759 ps
T1766 /workspace/coverage/default/23.spi_device_intercept.383075881 Dec 24 01:56:03 PM PST 23 Dec 24 01:56:10 PM PST 23 356593731 ps
T1767 /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1213758774 Dec 24 01:56:28 PM PST 23 Dec 24 01:57:16 PM PST 23 59269497859 ps
T1768 /workspace/coverage/default/24.spi_device_extreme_fifo_size.880304099 Dec 24 01:55:59 PM PST 23 Dec 24 02:26:52 PM PST 23 57616138414 ps
T1769 /workspace/coverage/default/21.spi_device_abort.3368280671 Dec 24 01:56:14 PM PST 23 Dec 24 01:56:18 PM PST 23 49526759 ps
T1770 /workspace/coverage/default/16.spi_device_intercept.3993616820 Dec 24 01:55:41 PM PST 23 Dec 24 01:55:48 PM PST 23 603745226 ps
T1771 /workspace/coverage/default/43.spi_device_perf.3848202020 Dec 24 01:57:37 PM PST 23 Dec 24 02:01:15 PM PST 23 38971543316 ps
T1772 /workspace/coverage/default/22.spi_device_perf.107101823 Dec 24 01:55:59 PM PST 23 Dec 24 02:17:04 PM PST 23 19749419826 ps
T228 /workspace/coverage/default/35.spi_device_stress_all.126111648 Dec 24 01:56:55 PM PST 23 Dec 24 02:21:25 PM PST 23 225820175303 ps
T1773 /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3338753338 Dec 24 01:57:20 PM PST 23 Dec 24 01:58:58 PM PST 23 47689356020 ps
T1774 /workspace/coverage/default/48.spi_device_fifo_full.1260443773 Dec 24 01:58:23 PM PST 23 Dec 24 02:09:26 PM PST 23 28841540787 ps
T1775 /workspace/coverage/default/39.spi_device_mailbox.826795288 Dec 24 01:57:16 PM PST 23 Dec 24 01:57:40 PM PST 23 10890920697 ps
T1776 /workspace/coverage/default/31.spi_device_cfg_cmd.1610342333 Dec 24 01:56:40 PM PST 23 Dec 24 01:56:48 PM PST 23 172921767 ps
T330 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.840851834 Dec 24 01:54:57 PM PST 23 Dec 24 02:00:47 PM PST 23 243543020295 ps
T1777 /workspace/coverage/default/28.spi_device_smoke.563276822 Dec 24 01:56:24 PM PST 23 Dec 24 01:56:28 PM PST 23 165936069 ps
T1778 /workspace/coverage/default/10.spi_device_bit_transfer.568542396 Dec 24 01:54:29 PM PST 23 Dec 24 01:54:36 PM PST 23 1152525183 ps
T1779 /workspace/coverage/default/23.spi_device_txrx.1205724052 Dec 24 01:56:06 PM PST 23 Dec 24 01:59:12 PM PST 23 182535286895 ps
T1780 /workspace/coverage/default/28.spi_device_bit_transfer.524733405 Dec 24 01:56:20 PM PST 23 Dec 24 01:56:26 PM PST 23 656301258 ps
T1781 /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2623164860 Dec 24 01:55:54 PM PST 23 Dec 24 01:56:17 PM PST 23 12775042995 ps
T1782 /workspace/coverage/default/1.spi_device_cfg_cmd.1278765199 Dec 24 01:54:08 PM PST 23 Dec 24 01:54:24 PM PST 23 3990738593 ps
T1783 /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.571074811 Dec 24 01:55:39 PM PST 23 Dec 24 01:55:45 PM PST 23 730614617 ps
T1784 /workspace/coverage/default/38.spi_device_bit_transfer.461881562 Dec 24 01:57:15 PM PST 23 Dec 24 01:57:25 PM PST 23 375071300 ps
T1785 /workspace/coverage/default/21.spi_device_flash_mode.2027868104 Dec 24 01:56:26 PM PST 23 Dec 24 01:57:17 PM PST 23 10707445704 ps
T1786 /workspace/coverage/default/46.spi_device_stress_all.4207579542 Dec 24 01:58:35 PM PST 23 Dec 24 02:24:46 PM PST 23 161910940497 ps
T1787 /workspace/coverage/default/14.spi_device_fifo_full.3729308577 Dec 24 01:54:56 PM PST 23 Dec 24 02:24:39 PM PST 23 85923313945 ps
T1788 /workspace/coverage/default/49.spi_device_pass_cmd_filtering.275313384 Dec 24 01:58:33 PM PST 23 Dec 24 01:58:40 PM PST 23 1840505920 ps
T1789 /workspace/coverage/default/18.spi_device_intercept.2326992246 Dec 24 01:55:15 PM PST 23 Dec 24 01:55:23 PM PST 23 2649326215 ps
T1790 /workspace/coverage/default/40.spi_device_upload.1532120083 Dec 24 01:57:21 PM PST 23 Dec 24 01:57:43 PM PST 23 25878920559 ps
T1791 /workspace/coverage/default/34.spi_device_perf.4112751723 Dec 24 01:56:54 PM PST 23 Dec 24 02:00:45 PM PST 23 117566221663 ps

Test location /workspace/coverage/default/44.spi_device_intercept.4125603867
Short name T12
Test name
Test status
Simulation time 2329004048 ps
CPU time 7.14 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 01:57:59 PM PST 23
Peak memory 241528 kb
Host smart-cb8ae785-733f-40a5-bbb7-5163442bb201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125603867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4125603867
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2665658553
Short name T6
Test name
Test status
Simulation time 227818118126 ps
CPU time 710.03 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 02:06:19 PM PST 23
Peak memory 253604 kb
Host smart-e1ace621-f351-4f4f-9f64-d934cc36168f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665658553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2665658553
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2601943189
Short name T21
Test name
Test status
Simulation time 5929776905 ps
CPU time 104.09 seconds
Started Dec 24 01:56:37 PM PST 23
Finished Dec 24 01:58:26 PM PST 23
Peak memory 274188 kb
Host smart-cbc35416-ac1e-4d0e-bd85-805099c0c181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601943189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2601943189
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1279510558
Short name T117
Test name
Test status
Simulation time 1000368626 ps
CPU time 22.66 seconds
Started Dec 24 12:32:13 PM PST 23
Finished Dec 24 12:33:00 PM PST 23
Peak memory 215740 kb
Host smart-2f556257-2d38-4dab-83f0-0208245810b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279510558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1279510558
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2008910139
Short name T68
Test name
Test status
Simulation time 29188846 ps
CPU time 0.72 seconds
Started Dec 24 12:32:48 PM PST 23
Finished Dec 24 12:33:16 PM PST 23
Peak memory 204876 kb
Host smart-bfedd4ce-8f32-425c-b525-500f751b0ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008910139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2008910139
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4045566891
Short name T62
Test name
Test status
Simulation time 191377022053 ps
CPU time 622.62 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 02:07:05 PM PST 23
Peak memory 323600 kb
Host smart-89c754a1-f786-4ef8-87e5-54082563de91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045566891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4045566891
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.412483827
Short name T27
Test name
Test status
Simulation time 23293749986 ps
CPU time 122.09 seconds
Started Dec 24 01:58:31 PM PST 23
Finished Dec 24 02:00:36 PM PST 23
Peak memory 254812 kb
Host smart-d9f69900-3d16-4293-8340-127166589ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412483827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.412483827
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2368618786
Short name T981
Test name
Test status
Simulation time 18938373 ps
CPU time 0.73 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 216624 kb
Host smart-21ee392f-2763-4a85-9ea1-8c27c468c93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368618786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2368618786
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2433283491
Short name T10
Test name
Test status
Simulation time 893643878 ps
CPU time 4.56 seconds
Started Dec 24 01:57:34 PM PST 23
Finished Dec 24 01:57:40 PM PST 23
Peak memory 235408 kb
Host smart-f8805cca-d8e3-4673-bf5e-2f5eafdc766f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2433283491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2433283491
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2791830397
Short name T217
Test name
Test status
Simulation time 34394955308 ps
CPU time 197.97 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:57:33 PM PST 23
Peak memory 267072 kb
Host smart-9a59cbb5-663d-4f3c-ab41-95384cd03cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791830397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2791830397
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1627061296
Short name T143
Test name
Test status
Simulation time 495985901773 ps
CPU time 1078.66 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:14:10 PM PST 23
Peak memory 307192 kb
Host smart-603ad1a3-fdc0-4928-8ae0-89f3b88e8753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627061296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1627061296
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4092649759
Short name T30
Test name
Test status
Simulation time 58624746689 ps
CPU time 204.85 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 02:01:07 PM PST 23
Peak memory 273964 kb
Host smart-ac3a9b63-829a-4516-8ad0-2309b8cc76f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092649759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4092649759
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_rx_timeout.701415235
Short name T112
Test name
Test status
Simulation time 898430570 ps
CPU time 5.62 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:24 PM PST 23
Peak memory 216716 kb
Host smart-52225824-b1c2-4861-9ec8-f11c534823fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701415235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_timeout.701415235
Directory /workspace/0.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1125155524
Short name T8
Test name
Test status
Simulation time 243460693131 ps
CPU time 617.88 seconds
Started Dec 24 01:57:01 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 462892 kb
Host smart-5e6b8c4e-f723-43da-9625-ca2e0d2e6985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125155524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1125155524
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3668416576
Short name T84
Test name
Test status
Simulation time 66441318 ps
CPU time 4.44 seconds
Started Dec 24 12:32:40 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 215928 kb
Host smart-7014120a-e7b1-4d4c-bb94-8f25fd6602fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668416576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3668416576
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2725846467
Short name T208
Test name
Test status
Simulation time 408412011132 ps
CPU time 700.63 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:07:52 PM PST 23
Peak memory 274324 kb
Host smart-fe17e1af-83ba-4f70-a140-13c5dbfef137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725846467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2725846467
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2022010999
Short name T105
Test name
Test status
Simulation time 623284640446 ps
CPU time 1077.92 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 02:13:57 PM PST 23
Peak memory 334908 kb
Host smart-774e80c4-4bba-4361-a2f7-ec157d09c902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022010999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2022010999
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2109885147
Short name T70
Test name
Test status
Simulation time 36990367 ps
CPU time 1.18 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:10 PM PST 23
Peak memory 215584 kb
Host smart-89b7047e-4631-4f73-97b7-93562072bf4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109885147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2109885147
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2348787328
Short name T180
Test name
Test status
Simulation time 17104464 ps
CPU time 0.73 seconds
Started Dec 24 12:32:39 PM PST 23
Finished Dec 24 12:33:05 PM PST 23
Peak memory 204816 kb
Host smart-460283da-9974-4dd6-ac5a-1a1429a85e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348787328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2348787328
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1858322402
Short name T243
Test name
Test status
Simulation time 209846463898 ps
CPU time 1755.76 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 02:26:02 PM PST 23
Peak memory 331068 kb
Host smart-764d6ea0-0818-4fbb-924f-0ec729d5e0c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858322402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1858322402
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3879475640
Short name T92
Test name
Test status
Simulation time 166210649 ps
CPU time 0.99 seconds
Started Dec 24 01:53:53 PM PST 23
Finished Dec 24 01:53:55 PM PST 23
Peak memory 238172 kb
Host smart-db35de2e-3ef7-41d9-b874-13a958e1e226
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879475640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3879475640
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1530506169
Short name T32
Test name
Test status
Simulation time 94006084092 ps
CPU time 694.57 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 02:05:55 PM PST 23
Peak memory 258032 kb
Host smart-4cb27f13-ecdd-4566-af2d-eb074b5fe60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530506169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1530506169
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_bit_transfer.484093887
Short name T13
Test name
Test status
Simulation time 655736234 ps
CPU time 2.55 seconds
Started Dec 24 01:56:44 PM PST 23
Finished Dec 24 01:56:53 PM PST 23
Peak memory 216860 kb
Host smart-facd476f-84cf-48b1-a79e-b05bd43b6749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484093887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_bit_transfer.484093887
Directory /workspace/30.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1202590026
Short name T248
Test name
Test status
Simulation time 30965025739 ps
CPU time 263.69 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 02:00:24 PM PST 23
Peak memory 269404 kb
Host smart-34090b49-8e9a-4171-8f35-395d48d797d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202590026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1202590026
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2447936147
Short name T128
Test name
Test status
Simulation time 321901866955 ps
CPU time 3331.8 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 02:53:10 PM PST 23
Peak memory 323396 kb
Host smart-23c15271-405e-4eec-aaa1-16e2c3106a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447936147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2447936147
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2176632216
Short name T348
Test name
Test status
Simulation time 4389238882 ps
CPU time 17.52 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:18 PM PST 23
Peak memory 243584 kb
Host smart-6a4ce746-1727-475b-94cb-28b45b3f20fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176632216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2176632216
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2214323424
Short name T233
Test name
Test status
Simulation time 27641652143 ps
CPU time 173.76 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:57:14 PM PST 23
Peak memory 282308 kb
Host smart-63ad4181-49a0-4a23-8428-efa80c467d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214323424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2214323424
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2765122897
Short name T200
Test name
Test status
Simulation time 216081135 ps
CPU time 13.09 seconds
Started Dec 24 12:32:04 PM PST 23
Finished Dec 24 12:32:44 PM PST 23
Peak memory 215632 kb
Host smart-f74bc8a0-c470-4b7b-b7c5-efb02b5d5640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765122897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2765122897
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4254114365
Short name T341
Test name
Test status
Simulation time 98379475819 ps
CPU time 446.34 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 02:03:24 PM PST 23
Peak memory 273508 kb
Host smart-23996847-3cd2-4843-94d4-eb0edce2dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254114365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4254114365
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.994123273
Short name T271
Test name
Test status
Simulation time 21159601064 ps
CPU time 104.72 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:56:17 PM PST 23
Peak memory 257736 kb
Host smart-3e7037fc-e761-4ce3-bab7-187b9dd869af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994123273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.994123273
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1316317022
Short name T674
Test name
Test status
Simulation time 18238865 ps
CPU time 1.02 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 218780 kb
Host smart-be9e888c-c10a-4a90-aa11-5bab83505d31
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316317022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1316317022
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4034155570
Short name T72
Test name
Test status
Simulation time 204738017121 ps
CPU time 1431.33 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 02:19:50 PM PST 23
Peak memory 432884 kb
Host smart-d6af131d-21f0-4da9-a2ed-c21a2a7102cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034155570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4034155570
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1890029492
Short name T127
Test name
Test status
Simulation time 106059552113 ps
CPU time 989.37 seconds
Started Dec 24 01:58:30 PM PST 23
Finished Dec 24 02:15:03 PM PST 23
Peak memory 406908 kb
Host smart-658b4ec7-566a-4147-9dd0-ba46d13737d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890029492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1890029492
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1935349442
Short name T122
Test name
Test status
Simulation time 141127510 ps
CPU time 5.19 seconds
Started Dec 24 12:32:12 PM PST 23
Finished Dec 24 12:32:42 PM PST 23
Peak memory 215916 kb
Host smart-e7c00842-d395-4cd9-bb38-05e8cbab2e65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935349442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1935349442
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4038011387
Short name T146
Test name
Test status
Simulation time 34888630 ps
CPU time 0.7 seconds
Started Dec 24 12:32:40 PM PST 23
Finished Dec 24 12:33:06 PM PST 23
Peak memory 204852 kb
Host smart-2c656301-2231-43b2-94c6-4c59db165b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038011387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4038011387
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/default/0.spi_device_extreme_fifo_size.2062515622
Short name T50
Test name
Test status
Simulation time 284445538139 ps
CPU time 4206.44 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 03:03:27 PM PST 23
Peak memory 218040 kb
Host smart-7e38b596-b794-4700-9c63-7eecfcaf88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062515622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_extreme_fifo_size.2062515622
Directory /workspace/0.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1182737048
Short name T318
Test name
Test status
Simulation time 11383378138 ps
CPU time 99.37 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:58:46 PM PST 23
Peak memory 256736 kb
Host smart-22249585-0128-4fbf-979a-66f17371c281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182737048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1182737048
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1610820716
Short name T118
Test name
Test status
Simulation time 3003695894 ps
CPU time 20.99 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:41 PM PST 23
Peak memory 215832 kb
Host smart-3c80fb6b-f639-4827-bf33-c130a6fea344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610820716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1610820716
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2772157837
Short name T322
Test name
Test status
Simulation time 27293866162 ps
CPU time 148.33 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 01:56:39 PM PST 23
Peak memory 260444 kb
Host smart-a3261a57-26f0-4d81-9af8-f962fdcaec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772157837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2772157837
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1262533897
Short name T28
Test name
Test status
Simulation time 632375722263 ps
CPU time 2056.47 seconds
Started Dec 24 01:53:39 PM PST 23
Finished Dec 24 02:27:57 PM PST 23
Peak memory 410800 kb
Host smart-50c4311f-4edf-405c-9ca8-2f5abd4a4e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262533897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1262533897
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1774247418
Short name T325
Test name
Test status
Simulation time 92949717035 ps
CPU time 1265.56 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 02:15:40 PM PST 23
Peak memory 380084 kb
Host smart-b3bd0a4b-1042-46ed-bb7a-9390b47930ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774247418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1774247418
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2192589653
Short name T60
Test name
Test status
Simulation time 11342268445 ps
CPU time 159.88 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:58:48 PM PST 23
Peak memory 266804 kb
Host smart-89460b9d-236d-4585-a254-714db2ccf91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192589653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2192589653
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_fifo_underflow_overflow.2999589667
Short name T189
Test name
Test status
Simulation time 154925318060 ps
CPU time 408.69 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 02:00:55 PM PST 23
Peak memory 355316 kb
Host smart-891fca01-de4a-4359-a73b-12b439534684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999589667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_underflow_overfl
ow.2999589667
Directory /workspace/2.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2210212651
Short name T213
Test name
Test status
Simulation time 44169072505 ps
CPU time 161.22 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 01:59:48 PM PST 23
Peak memory 249816 kb
Host smart-b18514b9-e9a9-412a-92fb-de21e8185a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210212651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2210212651
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1313039884
Short name T942
Test name
Test status
Simulation time 2097851514 ps
CPU time 21.34 seconds
Started Dec 24 01:57:08 PM PST 23
Finished Dec 24 01:57:38 PM PST 23
Peak memory 237944 kb
Host smart-ad38a2bc-792c-42bd-b78a-fcc1ef0886ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313039884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1313039884
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4055318614
Short name T343
Test name
Test status
Simulation time 4873044349 ps
CPU time 57.39 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:59:20 PM PST 23
Peak memory 265724 kb
Host smart-2d24f547-15e5-48ce-bb79-575f4ec788dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055318614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4055318614
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3533123495
Short name T337
Test name
Test status
Simulation time 3937599437 ps
CPU time 102.31 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:56:15 PM PST 23
Peak memory 264580 kb
Host smart-b2f537e4-414f-4cdd-9c31-51aa692a2b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533123495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3533123495
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2341196010
Short name T11
Test name
Test status
Simulation time 1103376327 ps
CPU time 13.07 seconds
Started Dec 24 01:53:56 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 229296 kb
Host smart-9f6b06d8-248f-4b3b-b71a-4b0d100153da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341196010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2341196010
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_fifo_underflow_overflow.2869177605
Short name T52
Test name
Test status
Simulation time 72460179078 ps
CPU time 500.19 seconds
Started Dec 24 01:55:55 PM PST 23
Finished Dec 24 02:04:16 PM PST 23
Peak memory 642412 kb
Host smart-4e6bed63-9203-4382-bbb7-1c3bde104732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869177605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_underflow_overf
low.2869177605
Directory /workspace/22.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3564057931
Short name T81
Test name
Test status
Simulation time 67744144 ps
CPU time 2.08 seconds
Started Dec 24 12:32:01 PM PST 23
Finished Dec 24 12:32:29 PM PST 23
Peak memory 218332 kb
Host smart-edb2690e-62ba-4591-a49e-b2aa61de1b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564057931 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3564057931
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.309823752
Short name T468
Test name
Test status
Simulation time 1190261900 ps
CPU time 19.66 seconds
Started Dec 24 12:32:03 PM PST 23
Finished Dec 24 12:32:49 PM PST 23
Peak memory 215764 kb
Host smart-1d0fd960-c337-4444-aab3-3b5ae76a7dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309823752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.309823752
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_dummy_item_extra_dly.2120249700
Short name T1574
Test name
Test status
Simulation time 68034228114 ps
CPU time 615.42 seconds
Started Dec 24 01:54:53 PM PST 23
Finished Dec 24 02:05:09 PM PST 23
Peak memory 257484 kb
Host smart-3f68b540-d5ce-478d-bb91-98a35aec70dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120249700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_dummy_item_extra_dly.2120249700
Directory /workspace/12.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.207226732
Short name T287
Test name
Test status
Simulation time 96088426989 ps
CPU time 294.05 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 02:00:33 PM PST 23
Peak memory 265208 kb
Host smart-05a0988e-b59f-467e-bff1-da7d03c8c4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207226732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.207226732
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.840851834
Short name T330
Test name
Test status
Simulation time 243543020295 ps
CPU time 347.02 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 02:00:47 PM PST 23
Peak memory 272024 kb
Host smart-b78b81bd-f4b1-4e22-9446-8426174eb512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840851834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.840851834
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3386151488
Short name T26
Test name
Test status
Simulation time 1199956879 ps
CPU time 5.38 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 01:56:34 PM PST 23
Peak memory 219504 kb
Host smart-e2770617-84ed-4b29-bff6-165e2bd6503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386151488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3386151488
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.881046196
Short name T298
Test name
Test status
Simulation time 4653323140 ps
CPU time 72.86 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:57:37 PM PST 23
Peak memory 249820 kb
Host smart-95f428cc-83a3-412b-8ca8-bcfe25482e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881046196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.881046196
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_intr.1057581536
Short name T144
Test name
Test status
Simulation time 67378206747 ps
CPU time 74.38 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:55:29 PM PST 23
Peak memory 237528 kb
Host smart-d0614978-37c8-452e-8722-2f8bfc20e7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057581536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intr.1057581536
Directory /workspace/3.spi_device_intr/latest

Test location /workspace/coverage/default/25.spi_device_abort.378835574
Short name T558
Test name
Test status
Simulation time 219202226 ps
CPU time 0.78 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 205616 kb
Host smart-a1d0a14a-6e7d-411c-a843-2812260a22c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378835574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_abort.378835574
Directory /workspace/25.spi_device_abort/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.249474167
Short name T65
Test name
Test status
Simulation time 154705088 ps
CPU time 0.7 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 206400 kb
Host smart-a860123a-7336-42ba-bde1-0e219e00723a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249474167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.249474167
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2443995470
Short name T124
Test name
Test status
Simulation time 599573462 ps
CPU time 4.37 seconds
Started Dec 24 12:31:40 PM PST 23
Finished Dec 24 12:32:12 PM PST 23
Peak memory 215836 kb
Host smart-47915da0-0b9a-489d-85b3-8ab823372525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443995470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
443995470
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_rx_async_fifo_reset.1600426701
Short name T604
Test name
Test status
Simulation time 22870179 ps
CPU time 0.91 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 208420 kb
Host smart-02143110-01fc-441f-b7bd-a20b0c3abaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600426701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_async_fifo_reset.1600426701
Directory /workspace/10.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_tx_async_fifo_reset.4149256541
Short name T136
Test name
Test status
Simulation time 14041774 ps
CPU time 0.79 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:01 PM PST 23
Peak memory 208476 kb
Host smart-04077d57-58af-47d7-91fe-4214e0c80652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149256541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tx_async_fifo_reset.4149256541
Directory /workspace/13.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2642931566
Short name T61
Test name
Test status
Simulation time 24688623100 ps
CPU time 74.12 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:59:39 PM PST 23
Peak memory 254356 kb
Host smart-6f4de99d-67e9-4dc1-8c8b-f4e3317362f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642931566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2642931566
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2885763582
Short name T403
Test name
Test status
Simulation time 6073553475 ps
CPU time 18.18 seconds
Started Dec 24 12:31:55 PM PST 23
Finished Dec 24 12:32:42 PM PST 23
Peak memory 216880 kb
Host smart-3bfd14f5-9bbc-479f-9c41-01ba3fbe842b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885763582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2885763582
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.196423160
Short name T151
Test name
Test status
Simulation time 9080420665 ps
CPU time 39.05 seconds
Started Dec 24 12:32:27 PM PST 23
Finished Dec 24 12:33:32 PM PST 23
Peak memory 207668 kb
Host smart-32b7049c-5242-48c0-bfec-daa5e4b604cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196423160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.196423160
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.905518853
Short name T397
Test name
Test status
Simulation time 17914167 ps
CPU time 1.02 seconds
Started Dec 24 12:32:13 PM PST 23
Finished Dec 24 12:32:39 PM PST 23
Peak memory 207320 kb
Host smart-3c844e9b-8c55-4304-963d-95cd053eac71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905518853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.905518853
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4104994074
Short name T442
Test name
Test status
Simulation time 244616175 ps
CPU time 2.54 seconds
Started Dec 24 12:31:34 PM PST 23
Finished Dec 24 12:32:02 PM PST 23
Peak memory 219180 kb
Host smart-8c926d70-8366-44ec-b5d3-40d71593b6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104994074 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4104994074
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1828547328
Short name T434
Test name
Test status
Simulation time 63658888 ps
CPU time 1.16 seconds
Started Dec 24 12:31:38 PM PST 23
Finished Dec 24 12:32:05 PM PST 23
Peak memory 215716 kb
Host smart-15b124e2-becb-43f5-a97c-bd45ed2a3ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828547328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
828547328
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3472827875
Short name T385
Test name
Test status
Simulation time 15068740 ps
CPU time 0.7 seconds
Started Dec 24 12:31:57 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 204860 kb
Host smart-c5ce13a8-7419-4c84-a9eb-d602e3aade1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472827875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
472827875
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1750554705
Short name T159
Test name
Test status
Simulation time 234632519 ps
CPU time 4.79 seconds
Started Dec 24 12:31:40 PM PST 23
Finished Dec 24 12:32:12 PM PST 23
Peak memory 215696 kb
Host smart-c6181b70-9883-491a-a932-7d3636bb8122
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750554705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1750554705
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2053121636
Short name T380
Test name
Test status
Simulation time 229812902 ps
CPU time 5.09 seconds
Started Dec 24 12:31:43 PM PST 23
Finished Dec 24 12:32:15 PM PST 23
Peak memory 215688 kb
Host smart-183ea2af-805e-47cd-911c-148fc5cf657f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053121636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2053121636
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.474651928
Short name T69
Test name
Test status
Simulation time 124917493 ps
CPU time 1.66 seconds
Started Dec 24 12:31:43 PM PST 23
Finished Dec 24 12:32:12 PM PST 23
Peak memory 215672 kb
Host smart-2037cfdb-68f1-487c-805b-2cbbbfa224f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474651928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.474651928
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4057022915
Short name T125
Test name
Test status
Simulation time 591600483 ps
CPU time 2.15 seconds
Started Dec 24 12:31:52 PM PST 23
Finished Dec 24 12:32:23 PM PST 23
Peak memory 215936 kb
Host smart-c106465b-1589-4acb-ae5c-b0964d487847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057022915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
057022915
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3022120568
Short name T161
Test name
Test status
Simulation time 894538178 ps
CPU time 18.91 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:28 PM PST 23
Peak memory 215660 kb
Host smart-51b1f939-86ad-4152-84b5-cda8030bef4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022120568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3022120568
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.787136393
Short name T360
Test name
Test status
Simulation time 2680013072 ps
CPU time 12.91 seconds
Started Dec 24 12:31:55 PM PST 23
Finished Dec 24 12:32:36 PM PST 23
Peak memory 207596 kb
Host smart-3dcafab3-ef2a-4965-80c0-55cb7a79af07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787136393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.787136393
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2812694176
Short name T463
Test name
Test status
Simulation time 50781233 ps
CPU time 1.45 seconds
Started Dec 24 12:31:43 PM PST 23
Finished Dec 24 12:32:12 PM PST 23
Peak memory 207500 kb
Host smart-523491bb-146c-4267-8d45-bc66a4bdb83d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812694176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2812694176
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2488935764
Short name T456
Test name
Test status
Simulation time 136050183 ps
CPU time 2.08 seconds
Started Dec 24 12:31:40 PM PST 23
Finished Dec 24 12:32:09 PM PST 23
Peak memory 218000 kb
Host smart-c1c79d4c-a77c-46ee-8de8-0b534ddba7c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488935764 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2488935764
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2751755661
Short name T461
Test name
Test status
Simulation time 1656845007 ps
CPU time 2.52 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:18 PM PST 23
Peak memory 215776 kb
Host smart-b22322bb-0294-4846-b76d-00a16d007757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751755661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
751755661
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2423004565
Short name T459
Test name
Test status
Simulation time 17705295 ps
CPU time 0.74 seconds
Started Dec 24 12:32:11 PM PST 23
Finished Dec 24 12:32:37 PM PST 23
Peak memory 204708 kb
Host smart-bb868e3e-851d-48aa-901b-e28a00100364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423004565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
423004565
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2193329546
Short name T154
Test name
Test status
Simulation time 930081398 ps
CPU time 6.52 seconds
Started Dec 24 12:31:59 PM PST 23
Finished Dec 24 12:32:32 PM PST 23
Peak memory 215604 kb
Host smart-58b07737-abe8-4f92-a7bf-9b94ecd7b7e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193329546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2193329546
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3323989316
Short name T369
Test name
Test status
Simulation time 3555623863 ps
CPU time 13.52 seconds
Started Dec 24 12:31:58 PM PST 23
Finished Dec 24 12:32:38 PM PST 23
Peak memory 215704 kb
Host smart-31054694-f3a6-44c6-ac35-198ed2b02a10
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323989316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3323989316
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1033344863
Short name T383
Test name
Test status
Simulation time 102918026 ps
CPU time 1.84 seconds
Started Dec 24 12:31:38 PM PST 23
Finished Dec 24 12:32:06 PM PST 23
Peak memory 215748 kb
Host smart-5df68345-3036-4812-8cf9-a354c8fc076b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033344863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1033344863
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.608691507
Short name T145
Test name
Test status
Simulation time 580476992 ps
CPU time 7.09 seconds
Started Dec 24 12:32:03 PM PST 23
Finished Dec 24 12:32:37 PM PST 23
Peak memory 215760 kb
Host smart-fec2f20f-2f0f-4a56-8a53-4024251df75f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608691507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.608691507
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1430242372
Short name T413
Test name
Test status
Simulation time 78564375 ps
CPU time 2.46 seconds
Started Dec 24 12:32:38 PM PST 23
Finished Dec 24 12:33:06 PM PST 23
Peak memory 215776 kb
Host smart-48f66a01-aeb1-4349-be44-55abdc6896e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430242372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1430242372
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3684579798
Short name T414
Test name
Test status
Simulation time 15892787 ps
CPU time 0.73 seconds
Started Dec 24 12:32:15 PM PST 23
Finished Dec 24 12:32:40 PM PST 23
Peak memory 204756 kb
Host smart-cfcbbb88-1aa1-4df6-8225-70911dad0792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684579798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3684579798
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.505946456
Short name T364
Test name
Test status
Simulation time 334957738 ps
CPU time 4.28 seconds
Started Dec 24 12:32:04 PM PST 23
Finished Dec 24 12:32:35 PM PST 23
Peak memory 215760 kb
Host smart-8d58167d-18dc-4b6d-bbf3-0caa1f0a7723
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505946456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.505946456
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2562207420
Short name T409
Test name
Test status
Simulation time 132861600 ps
CPU time 3.9 seconds
Started Dec 24 12:32:06 PM PST 23
Finished Dec 24 12:32:36 PM PST 23
Peak memory 215896 kb
Host smart-fdc6502f-9d60-41fe-aae1-9d406eb8b520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562207420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2562207420
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3412952465
Short name T152
Test name
Test status
Simulation time 5988828261 ps
CPU time 19.78 seconds
Started Dec 24 12:32:18 PM PST 23
Finished Dec 24 12:33:03 PM PST 23
Peak memory 215816 kb
Host smart-cac8e701-d964-424e-948a-9a6ec5297339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412952465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3412952465
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4042528284
Short name T368
Test name
Test status
Simulation time 130022022 ps
CPU time 2.39 seconds
Started Dec 24 12:32:15 PM PST 23
Finished Dec 24 12:32:42 PM PST 23
Peak memory 218668 kb
Host smart-c57fd927-8190-4386-8168-232249c3a982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042528284 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4042528284
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1030357429
Short name T449
Test name
Test status
Simulation time 130223547 ps
CPU time 1.84 seconds
Started Dec 24 12:31:55 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 215792 kb
Host smart-3aa60534-9731-42a3-9c7b-3a8a0b3363db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030357429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1030357429
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4009563275
Short name T373
Test name
Test status
Simulation time 47432219 ps
CPU time 0.74 seconds
Started Dec 24 12:31:56 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 204832 kb
Host smart-78083b10-1406-42a6-8c9c-667464cfcae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009563275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4009563275
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3457997878
Short name T401
Test name
Test status
Simulation time 358241301 ps
CPU time 2.93 seconds
Started Dec 24 12:32:02 PM PST 23
Finished Dec 24 12:32:31 PM PST 23
Peak memory 215632 kb
Host smart-6fd994a0-75f1-4bee-b25d-82607ae6f0a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457997878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3457997878
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2430930950
Short name T420
Test name
Test status
Simulation time 131830247 ps
CPU time 2.42 seconds
Started Dec 24 12:32:15 PM PST 23
Finished Dec 24 12:32:43 PM PST 23
Peak memory 215884 kb
Host smart-717833de-9b12-4ade-890e-69786c4c4fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430930950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2430930950
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3265116773
Short name T392
Test name
Test status
Simulation time 2351236168 ps
CPU time 13.2 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:44 PM PST 23
Peak memory 215884 kb
Host smart-eaecdf14-a1ab-47a7-9800-3b1e9c4d6846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265116773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3265116773
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3456207547
Short name T428
Test name
Test status
Simulation time 61587976 ps
CPU time 1.76 seconds
Started Dec 24 12:32:41 PM PST 23
Finished Dec 24 12:33:11 PM PST 23
Peak memory 218072 kb
Host smart-75d9705a-6819-42c6-8e9f-e42279e97c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456207547 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3456207547
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.453843645
Short name T429
Test name
Test status
Simulation time 42221173 ps
CPU time 1.34 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:33:13 PM PST 23
Peak memory 207512 kb
Host smart-e6660681-85be-4a5c-b7bb-72aa75390878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453843645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.453843645
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1484624090
Short name T388
Test name
Test status
Simulation time 28160419 ps
CPU time 0.76 seconds
Started Dec 24 12:32:02 PM PST 23
Finished Dec 24 12:32:29 PM PST 23
Peak memory 204792 kb
Host smart-00bccdb8-1ffb-4f35-b287-1158503b4305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484624090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1484624090
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3488119035
Short name T436
Test name
Test status
Simulation time 27929795 ps
CPU time 1.77 seconds
Started Dec 24 12:32:18 PM PST 23
Finished Dec 24 12:32:45 PM PST 23
Peak memory 215736 kb
Host smart-fbefb36f-8d17-4e8b-b5f3-f5d26767a6be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488119035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3488119035
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2415296199
Short name T115
Test name
Test status
Simulation time 97095193 ps
CPU time 1.75 seconds
Started Dec 24 12:32:29 PM PST 23
Finished Dec 24 12:33:11 PM PST 23
Peak memory 216020 kb
Host smart-5bdbda6d-c501-45df-9974-f5b86edffd7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415296199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2415296199
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3014653773
Short name T408
Test name
Test status
Simulation time 212725297 ps
CPU time 12.3 seconds
Started Dec 24 12:32:26 PM PST 23
Finished Dec 24 12:33:05 PM PST 23
Peak memory 215560 kb
Host smart-328cf6ef-c831-48c8-bea6-b21d33b0e670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014653773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3014653773
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2353080336
Short name T395
Test name
Test status
Simulation time 21136618 ps
CPU time 1.28 seconds
Started Dec 24 12:31:57 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 217132 kb
Host smart-bea5cc64-03bd-4c51-8ed2-a8decc6964ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353080336 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2353080336
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3928454498
Short name T462
Test name
Test status
Simulation time 232949310 ps
CPU time 2.44 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:33 PM PST 23
Peak memory 215756 kb
Host smart-12165ac9-37a9-4519-9e57-47692031a861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928454498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3928454498
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3311482244
Short name T66
Test name
Test status
Simulation time 15025094 ps
CPU time 0.71 seconds
Started Dec 24 12:31:59 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 204888 kb
Host smart-143c742b-4f8b-4c24-b60c-c9fab7b8531d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311482244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3311482244
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1181346221
Short name T452
Test name
Test status
Simulation time 64590737 ps
CPU time 4.14 seconds
Started Dec 24 12:32:40 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 215636 kb
Host smart-d7c91f10-eaa7-47c2-8a1a-0f9f01de6cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181346221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1181346221
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4070033430
Short name T119
Test name
Test status
Simulation time 1182410392 ps
CPU time 14.98 seconds
Started Dec 24 12:32:29 PM PST 23
Finished Dec 24 12:33:11 PM PST 23
Peak memory 215592 kb
Host smart-6f23294c-0caa-40a6-ba69-a8080062cb1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070033430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4070033430
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2447828497
Short name T464
Test name
Test status
Simulation time 62362049 ps
CPU time 1.72 seconds
Started Dec 24 12:32:38 PM PST 23
Finished Dec 24 12:33:06 PM PST 23
Peak memory 217876 kb
Host smart-97e00d4d-cf09-42ea-97e9-950c4d12554f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447828497 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2447828497
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1869132783
Short name T402
Test name
Test status
Simulation time 62821008 ps
CPU time 1.23 seconds
Started Dec 24 12:32:50 PM PST 23
Finished Dec 24 12:33:25 PM PST 23
Peak memory 215776 kb
Host smart-a874c6ae-9158-488c-b673-46fc2610a81e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869132783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1869132783
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2055469067
Short name T431
Test name
Test status
Simulation time 14584103 ps
CPU time 0.7 seconds
Started Dec 24 12:32:28 PM PST 23
Finished Dec 24 12:32:56 PM PST 23
Peak memory 204788 kb
Host smart-ad2a0b20-fb69-48d9-b110-273afbf36630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055469067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2055469067
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1347378678
Short name T381
Test name
Test status
Simulation time 189272368 ps
CPU time 1.68 seconds
Started Dec 24 12:33:09 PM PST 23
Finished Dec 24 12:33:52 PM PST 23
Peak memory 215696 kb
Host smart-2617094f-7673-4615-b1be-67ba029e942d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347378678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1347378678
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2819522424
Short name T454
Test name
Test status
Simulation time 78961051 ps
CPU time 5.31 seconds
Started Dec 24 12:32:07 PM PST 23
Finished Dec 24 12:32:38 PM PST 23
Peak memory 215892 kb
Host smart-bc81a428-6195-4cc9-8e84-2f556c56d109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819522424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2819522424
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1391971627
Short name T375
Test name
Test status
Simulation time 26055321 ps
CPU time 1.23 seconds
Started Dec 24 12:33:01 PM PST 23
Finished Dec 24 12:33:44 PM PST 23
Peak memory 217116 kb
Host smart-c53b5b24-f833-413c-87ae-02a4cbee3e12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391971627 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1391971627
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.882546948
Short name T182
Test name
Test status
Simulation time 84544699 ps
CPU time 1.98 seconds
Started Dec 24 12:32:50 PM PST 23
Finished Dec 24 12:33:24 PM PST 23
Peak memory 215616 kb
Host smart-741bde36-505b-43c0-89a9-ecfcd1075979
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882546948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.882546948
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1872101028
Short name T370
Test name
Test status
Simulation time 86554404 ps
CPU time 0.68 seconds
Started Dec 24 12:32:56 PM PST 23
Finished Dec 24 12:33:38 PM PST 23
Peak memory 204776 kb
Host smart-393fe7d4-6c5c-4442-bcbe-b854a0608925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872101028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1872101028
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2104211580
Short name T458
Test name
Test status
Simulation time 92085427 ps
CPU time 1.97 seconds
Started Dec 24 12:32:49 PM PST 23
Finished Dec 24 12:33:19 PM PST 23
Peak memory 215604 kb
Host smart-a459f381-4e1b-45ad-98f1-d72754826f51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104211580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2104211580
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1743777807
Short name T466
Test name
Test status
Simulation time 182987582 ps
CPU time 4.38 seconds
Started Dec 24 12:32:38 PM PST 23
Finished Dec 24 12:33:09 PM PST 23
Peak memory 215932 kb
Host smart-8d5b3588-b993-4f68-a40b-7b7a113481b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743777807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1743777807
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3423241188
Short name T187
Test name
Test status
Simulation time 698116387 ps
CPU time 7.08 seconds
Started Dec 24 12:32:32 PM PST 23
Finished Dec 24 12:33:04 PM PST 23
Peak memory 215828 kb
Host smart-160920df-e2e9-4a0f-b7cc-23bc6b5c6fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423241188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3423241188
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.439332794
Short name T467
Test name
Test status
Simulation time 34248939 ps
CPU time 2.58 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:29 PM PST 23
Peak memory 218228 kb
Host smart-e5916cc0-cacd-488a-9bce-6872cc118ab0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439332794 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.439332794
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2133939047
Short name T165
Test name
Test status
Simulation time 22031821 ps
CPU time 1.27 seconds
Started Dec 24 12:32:29 PM PST 23
Finished Dec 24 12:32:57 PM PST 23
Peak memory 207536 kb
Host smart-46edad9e-9a99-4946-bdd2-1f475df63df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133939047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2133939047
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.790955350
Short name T445
Test name
Test status
Simulation time 16128387 ps
CPU time 0.75 seconds
Started Dec 24 12:32:23 PM PST 23
Finished Dec 24 12:32:51 PM PST 23
Peak memory 204844 kb
Host smart-8e636232-390a-43d2-9c48-94a64457b63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790955350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.790955350
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.669603791
Short name T460
Test name
Test status
Simulation time 1871501734 ps
CPU time 2.77 seconds
Started Dec 24 12:32:27 PM PST 23
Finished Dec 24 12:32:57 PM PST 23
Peak memory 217004 kb
Host smart-010679a2-9be1-404a-9944-5900d6a235f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669603791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.669603791
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.27374306
Short name T451
Test name
Test status
Simulation time 1163837259 ps
CPU time 4.93 seconds
Started Dec 24 12:32:46 PM PST 23
Finished Dec 24 12:33:19 PM PST 23
Peak memory 215944 kb
Host smart-2e5fec7a-1dc8-459b-975c-9227e8cc387f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27374306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.27374306
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4206425535
Short name T199
Test name
Test status
Simulation time 198714494 ps
CPU time 12.19 seconds
Started Dec 24 12:32:28 PM PST 23
Finished Dec 24 12:33:07 PM PST 23
Peak memory 215764 kb
Host smart-b738f28c-4b9d-43a0-a6a4-5a50f51a36b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206425535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4206425535
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2591938625
Short name T411
Test name
Test status
Simulation time 169319352 ps
CPU time 1.16 seconds
Started Dec 24 12:32:31 PM PST 23
Finished Dec 24 12:32:58 PM PST 23
Peak memory 216776 kb
Host smart-faccb43e-a6e0-4a29-a6a4-e7b79b001ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591938625 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2591938625
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.606302580
Short name T163
Test name
Test status
Simulation time 350978694 ps
CPU time 1.99 seconds
Started Dec 24 12:32:37 PM PST 23
Finished Dec 24 12:33:05 PM PST 23
Peak memory 220392 kb
Host smart-209daebb-e8c4-4f43-a74c-576d24dba333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606302580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.606302580
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.843805000
Short name T382
Test name
Test status
Simulation time 28723920 ps
CPU time 0.75 seconds
Started Dec 24 12:32:47 PM PST 23
Finished Dec 24 12:33:15 PM PST 23
Peak memory 204800 kb
Host smart-7c8f2838-1fd5-419c-947c-f3b3dc31e104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843805000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.843805000
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2290269035
Short name T398
Test name
Test status
Simulation time 651602833 ps
CPU time 4.14 seconds
Started Dec 24 12:32:26 PM PST 23
Finished Dec 24 12:32:57 PM PST 23
Peak memory 215644 kb
Host smart-5cde1eed-c001-4649-9a00-d5b75873e31f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290269035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2290269035
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3104050827
Short name T126
Test name
Test status
Simulation time 197592838 ps
CPU time 4.82 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:33:16 PM PST 23
Peak memory 215904 kb
Host smart-d30c0958-a238-4eca-9804-5a3424e8bad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104050827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3104050827
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.524743768
Short name T204
Test name
Test status
Simulation time 765368116 ps
CPU time 8.07 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:35 PM PST 23
Peak memory 215668 kb
Host smart-d4dbf45a-74f7-4200-89a9-0449c12a42d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524743768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.524743768
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1851368638
Short name T179
Test name
Test status
Simulation time 69824104 ps
CPU time 2.97 seconds
Started Dec 24 12:32:36 PM PST 23
Finished Dec 24 12:33:11 PM PST 23
Peak memory 218244 kb
Host smart-13dbe046-de7b-4cc1-b21e-67253678d2fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851368638 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1851368638
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2771265718
Short name T423
Test name
Test status
Simulation time 57091303 ps
CPU time 1.22 seconds
Started Dec 24 12:32:29 PM PST 23
Finished Dec 24 12:32:57 PM PST 23
Peak memory 215756 kb
Host smart-209c04c2-8b05-4800-8b87-60552eff3877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771265718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2771265718
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2433190872
Short name T186
Test name
Test status
Simulation time 43910748 ps
CPU time 0.77 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:33:13 PM PST 23
Peak memory 204840 kb
Host smart-449fb0ee-c484-4c08-843f-adc6930c1f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433190872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2433190872
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2776394928
Short name T440
Test name
Test status
Simulation time 144808880 ps
CPU time 4 seconds
Started Dec 24 12:32:41 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 215684 kb
Host smart-abdc3d88-dbe0-4e7b-a568-34ae71dbd2e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776394928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2776394928
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1964663494
Short name T441
Test name
Test status
Simulation time 246070032 ps
CPU time 3.39 seconds
Started Dec 24 12:33:58 PM PST 23
Finished Dec 24 12:34:39 PM PST 23
Peak memory 216852 kb
Host smart-d7e02dac-de9c-4556-8324-586156a66dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964663494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1964663494
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4286465273
Short name T457
Test name
Test status
Simulation time 303865693 ps
CPU time 17.82 seconds
Started Dec 24 12:32:36 PM PST 23
Finished Dec 24 12:33:20 PM PST 23
Peak memory 215696 kb
Host smart-4978aa1f-8e4b-4192-9b07-d6f17a2f9df8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286465273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4286465273
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3364895558
Short name T396
Test name
Test status
Simulation time 35669912 ps
CPU time 1.18 seconds
Started Dec 24 12:33:17 PM PST 23
Finished Dec 24 12:33:57 PM PST 23
Peak memory 217148 kb
Host smart-e8fa3d1b-38e5-4bdd-bcc5-3072aa73b963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364895558 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3364895558
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.660413256
Short name T88
Test name
Test status
Simulation time 11887175 ps
CPU time 0.68 seconds
Started Dec 24 12:32:53 PM PST 23
Finished Dec 24 12:33:31 PM PST 23
Peak memory 204936 kb
Host smart-05cc197f-179e-48fe-a143-f1c72c554eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660413256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.660413256
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.15541751
Short name T391
Test name
Test status
Simulation time 248287720 ps
CPU time 3.69 seconds
Started Dec 24 12:32:35 PM PST 23
Finished Dec 24 12:33:04 PM PST 23
Peak memory 216748 kb
Host smart-a8045fc6-e5c9-448b-8122-d148cc5fc594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sp
i_device_same_csr_outstanding.15541751
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1878860322
Short name T198
Test name
Test status
Simulation time 800277182 ps
CPU time 12.27 seconds
Started Dec 24 12:32:47 PM PST 23
Finished Dec 24 12:33:27 PM PST 23
Peak memory 215624 kb
Host smart-56c81fa2-2728-46ba-b81a-d81a41b45063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878860322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1878860322
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3519024440
Short name T389
Test name
Test status
Simulation time 246834265 ps
CPU time 15.94 seconds
Started Dec 24 12:32:30 PM PST 23
Finished Dec 24 12:33:31 PM PST 23
Peak memory 215736 kb
Host smart-54cf189a-2136-41f3-afdd-a551c309740d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519024440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3519024440
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1158154058
Short name T412
Test name
Test status
Simulation time 4800636882 ps
CPU time 34.21 seconds
Started Dec 24 12:32:00 PM PST 23
Finished Dec 24 12:33:00 PM PST 23
Peak memory 207544 kb
Host smart-370a4b57-c08e-495c-b83c-f388214ba3be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158154058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1158154058
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.992675833
Short name T416
Test name
Test status
Simulation time 110112761 ps
CPU time 0.99 seconds
Started Dec 24 12:31:41 PM PST 23
Finished Dec 24 12:32:10 PM PST 23
Peak memory 207384 kb
Host smart-868bf273-08b2-472c-a862-7a3af27f9a46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992675833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.992675833
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.401519899
Short name T184
Test name
Test status
Simulation time 29936308 ps
CPU time 1.91 seconds
Started Dec 24 12:31:59 PM PST 23
Finished Dec 24 12:32:27 PM PST 23
Peak memory 218372 kb
Host smart-04c2cb72-b689-4f3a-a253-c4b2094774ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401519899 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.401519899
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2515405204
Short name T438
Test name
Test status
Simulation time 112056169 ps
CPU time 2.59 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:33 PM PST 23
Peak memory 215776 kb
Host smart-29210b5d-efc3-463e-a690-176725bf9557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515405204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
515405204
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.395127404
Short name T448
Test name
Test status
Simulation time 12128542 ps
CPU time 0.72 seconds
Started Dec 24 12:31:35 PM PST 23
Finished Dec 24 12:32:01 PM PST 23
Peak memory 204708 kb
Host smart-b237b038-7c99-4893-bbea-e1a26fde0f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395127404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.395127404
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2634405651
Short name T155
Test name
Test status
Simulation time 825210060 ps
CPU time 4.77 seconds
Started Dec 24 12:31:52 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 215748 kb
Host smart-2f239ded-63a5-4368-905e-d9d8032e65dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634405651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2634405651
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2286328156
Short name T432
Test name
Test status
Simulation time 7334115774 ps
CPU time 9.38 seconds
Started Dec 24 12:31:41 PM PST 23
Finished Dec 24 12:32:18 PM PST 23
Peak memory 215776 kb
Host smart-63528ae3-5645-4947-b626-e5dee4d44ff2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286328156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2286328156
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2581336780
Short name T419
Test name
Test status
Simulation time 1156173170 ps
CPU time 4.39 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 215696 kb
Host smart-3c494137-d714-47c6-a043-0e6e183d3a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581336780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2581336780
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.240137054
Short name T386
Test name
Test status
Simulation time 51859223 ps
CPU time 3.49 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:34 PM PST 23
Peak memory 215988 kb
Host smart-d65533ea-1342-4d1e-b77b-2e1f936fe91c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240137054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.240137054
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1528251256
Short name T378
Test name
Test status
Simulation time 24363219 ps
CPU time 0.75 seconds
Started Dec 24 12:32:33 PM PST 23
Finished Dec 24 12:33:09 PM PST 23
Peak memory 204800 kb
Host smart-bbdce898-3d0a-4225-b1dc-f33210893b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528251256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1528251256
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1976477955
Short name T433
Test name
Test status
Simulation time 17646960 ps
CPU time 0.73 seconds
Started Dec 24 12:33:08 PM PST 23
Finished Dec 24 12:33:49 PM PST 23
Peak memory 204880 kb
Host smart-d2bb7be5-4d06-40c5-90a0-0a69af6a77cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976477955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1976477955
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3389557984
Short name T405
Test name
Test status
Simulation time 12791645 ps
CPU time 0.69 seconds
Started Dec 24 12:32:47 PM PST 23
Finished Dec 24 12:33:15 PM PST 23
Peak memory 204732 kb
Host smart-d97221b4-d095-43d6-b64d-f41c3c2bae45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389557984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3389557984
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3420165383
Short name T399
Test name
Test status
Simulation time 25059444 ps
CPU time 0.73 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:10 PM PST 23
Peak memory 204776 kb
Host smart-8eb09c0e-eeb3-4b26-95ca-9f99e37a124b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420165383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3420165383
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3779966235
Short name T377
Test name
Test status
Simulation time 75018010 ps
CPU time 0.7 seconds
Started Dec 24 12:32:26 PM PST 23
Finished Dec 24 12:32:53 PM PST 23
Peak memory 204876 kb
Host smart-5bba67a7-c29f-4726-8fd2-9fe91546ff8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779966235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3779966235
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1441088991
Short name T188
Test name
Test status
Simulation time 13250234 ps
CPU time 0.7 seconds
Started Dec 24 12:32:34 PM PST 23
Finished Dec 24 12:33:00 PM PST 23
Peak memory 204824 kb
Host smart-16a7ec45-d0e4-49c8-b1ce-c777bfe80a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441088991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1441088991
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1135059383
Short name T365
Test name
Test status
Simulation time 22490718 ps
CPU time 0.71 seconds
Started Dec 24 12:32:29 PM PST 23
Finished Dec 24 12:32:56 PM PST 23
Peak memory 204852 kb
Host smart-6477a1ff-b526-4a2a-a8b2-648b7bfaf90c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135059383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1135059383
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3145194021
Short name T421
Test name
Test status
Simulation time 14290673 ps
CPU time 0.75 seconds
Started Dec 24 12:32:40 PM PST 23
Finished Dec 24 12:33:08 PM PST 23
Peak memory 204828 kb
Host smart-a1cf6592-296c-4cb5-84ff-9407a2518036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145194021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3145194021
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.960678244
Short name T453
Test name
Test status
Simulation time 19693014 ps
CPU time 0.73 seconds
Started Dec 24 12:32:54 PM PST 23
Finished Dec 24 12:33:35 PM PST 23
Peak memory 204868 kb
Host smart-ac650452-fe25-4158-803d-b077fbda8848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960678244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.960678244
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1296598494
Short name T444
Test name
Test status
Simulation time 366643040 ps
CPU time 24.91 seconds
Started Dec 24 12:31:57 PM PST 23
Finished Dec 24 12:32:49 PM PST 23
Peak memory 216944 kb
Host smart-ff9651a1-afa5-4756-bdf5-faef83a5a012
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296598494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1296598494
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1380212347
Short name T425
Test name
Test status
Simulation time 7867769167 ps
CPU time 27.23 seconds
Started Dec 24 12:31:55 PM PST 23
Finished Dec 24 12:32:51 PM PST 23
Peak memory 215864 kb
Host smart-888693c1-0998-4606-af75-a8b1f23f4ac3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380212347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1380212347
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1209193527
Short name T183
Test name
Test status
Simulation time 147965063 ps
CPU time 1.14 seconds
Started Dec 24 12:32:10 PM PST 23
Finished Dec 24 12:32:36 PM PST 23
Peak memory 207352 kb
Host smart-29ea9bb4-7264-4306-81b6-dcb627c28ad1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209193527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1209193527
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1493149352
Short name T400
Test name
Test status
Simulation time 67735062 ps
CPU time 1.56 seconds
Started Dec 24 12:32:13 PM PST 23
Finished Dec 24 12:32:40 PM PST 23
Peak memory 217120 kb
Host smart-eecf746b-99a9-4005-b030-4809dd0c78e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493149352 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1493149352
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2662099996
Short name T162
Test name
Test status
Simulation time 41857922 ps
CPU time 1.32 seconds
Started Dec 24 12:32:04 PM PST 23
Finished Dec 24 12:32:32 PM PST 23
Peak memory 207536 kb
Host smart-188b657d-d6f1-496b-b41d-d1065a20f960
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662099996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
662099996
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1459627362
Short name T430
Test name
Test status
Simulation time 13327710 ps
CPU time 0.73 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:32 PM PST 23
Peak memory 204868 kb
Host smart-0f4ae2dd-9bf9-483b-a8d1-6694d9b593d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459627362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
459627362
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4256108349
Short name T167
Test name
Test status
Simulation time 401178329 ps
CPU time 6.89 seconds
Started Dec 24 12:32:06 PM PST 23
Finished Dec 24 12:32:46 PM PST 23
Peak memory 215816 kb
Host smart-e6c6cabf-a1f1-459e-bee4-667ad414b837
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256108349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4256108349
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2080476587
Short name T362
Test name
Test status
Simulation time 2840944009 ps
CPU time 13.08 seconds
Started Dec 24 12:31:50 PM PST 23
Finished Dec 24 12:32:33 PM PST 23
Peak memory 215724 kb
Host smart-cd9cad81-51cc-49a4-82ce-1d19f85b732e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080476587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2080476587
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.688766913
Short name T85
Test name
Test status
Simulation time 155642956 ps
CPU time 3.12 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:34 PM PST 23
Peak memory 215716 kb
Host smart-9d9815df-4714-4c43-a647-ba361358a1cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688766913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.688766913
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2469612119
Short name T83
Test name
Test status
Simulation time 363887638 ps
CPU time 2.48 seconds
Started Dec 24 12:32:15 PM PST 23
Finished Dec 24 12:32:42 PM PST 23
Peak memory 215808 kb
Host smart-b7f99540-51f2-4bb2-8607-6d5da6ff71f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469612119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
469612119
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1592742041
Short name T417
Test name
Test status
Simulation time 298525113 ps
CPU time 7.32 seconds
Started Dec 24 12:32:13 PM PST 23
Finished Dec 24 12:32:45 PM PST 23
Peak memory 215668 kb
Host smart-74aff008-e4b5-46be-9e42-034954bfe094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592742041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1592742041
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.27867881
Short name T387
Test name
Test status
Simulation time 41670964 ps
CPU time 0.71 seconds
Started Dec 24 12:32:39 PM PST 23
Finished Dec 24 12:33:06 PM PST 23
Peak memory 204860 kb
Host smart-88685944-ae23-45ea-85ea-6f0e6a92b651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.27867881
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.193516832
Short name T153
Test name
Test status
Simulation time 13194237 ps
CPU time 0.73 seconds
Started Dec 24 12:32:43 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 204844 kb
Host smart-93d634ee-3b9d-4964-b98d-1295ff880035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193516832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.193516832
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2415067488
Short name T185
Test name
Test status
Simulation time 17442873 ps
CPU time 0.72 seconds
Started Dec 24 12:32:39 PM PST 23
Finished Dec 24 12:33:06 PM PST 23
Peak memory 204868 kb
Host smart-8c5711e7-d7e3-49b3-a37a-4b78d94f3707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415067488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2415067488
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2186148823
Short name T410
Test name
Test status
Simulation time 12830226 ps
CPU time 0.69 seconds
Started Dec 24 12:32:15 PM PST 23
Finished Dec 24 12:32:40 PM PST 23
Peak memory 204784 kb
Host smart-b193b893-21ea-448a-8667-d22a654ffd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186148823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2186148823
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.845706011
Short name T427
Test name
Test status
Simulation time 21104537 ps
CPU time 0.71 seconds
Started Dec 24 12:32:25 PM PST 23
Finished Dec 24 12:32:52 PM PST 23
Peak memory 204860 kb
Host smart-9072b5d9-2d6b-4fbe-b076-2ea55450ab21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845706011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.845706011
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.835388187
Short name T149
Test name
Test status
Simulation time 15445259 ps
CPU time 0.69 seconds
Started Dec 24 12:33:07 PM PST 23
Finished Dec 24 12:33:49 PM PST 23
Peak memory 204744 kb
Host smart-57d42dda-f922-4f2f-b745-7b5d5d6e2c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835388187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.835388187
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4156351087
Short name T374
Test name
Test status
Simulation time 17544289 ps
CPU time 0.74 seconds
Started Dec 24 12:32:40 PM PST 23
Finished Dec 24 12:33:08 PM PST 23
Peak memory 204812 kb
Host smart-707cee93-2217-4d89-a29c-10cdbed7590c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156351087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4156351087
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1545282925
Short name T404
Test name
Test status
Simulation time 45922406 ps
CPU time 0.69 seconds
Started Dec 24 12:32:47 PM PST 23
Finished Dec 24 12:33:16 PM PST 23
Peak memory 204764 kb
Host smart-d6373232-57bf-45c1-869f-0ffd1723642e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545282925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1545282925
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2448459192
Short name T361
Test name
Test status
Simulation time 33106203 ps
CPU time 0.76 seconds
Started Dec 24 12:32:27 PM PST 23
Finished Dec 24 12:32:54 PM PST 23
Peak memory 204820 kb
Host smart-761a9f0a-84ad-48c2-8215-121d9bd24349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448459192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2448459192
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1560534456
Short name T443
Test name
Test status
Simulation time 1055899537 ps
CPU time 16.72 seconds
Started Dec 24 12:31:52 PM PST 23
Finished Dec 24 12:32:38 PM PST 23
Peak memory 215716 kb
Host smart-d301e2a1-c732-4045-a2a6-ddb0b0738ca5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560534456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1560534456
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2393903545
Short name T446
Test name
Test status
Simulation time 200662193 ps
CPU time 12.25 seconds
Started Dec 24 12:32:37 PM PST 23
Finished Dec 24 12:33:15 PM PST 23
Peak memory 207452 kb
Host smart-51ecac18-1a75-4750-ae7b-91ee425ae9f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393903545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2393903545
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1189864850
Short name T86
Test name
Test status
Simulation time 31942516 ps
CPU time 0.93 seconds
Started Dec 24 12:32:02 PM PST 23
Finished Dec 24 12:32:37 PM PST 23
Peak memory 207392 kb
Host smart-719b78c1-12b4-473f-9b49-146a93834e86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189864850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1189864850
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3770566968
Short name T376
Test name
Test status
Simulation time 27147597 ps
CPU time 2.57 seconds
Started Dec 24 12:32:09 PM PST 23
Finished Dec 24 12:32:37 PM PST 23
Peak memory 218636 kb
Host smart-bf369671-8630-4927-b871-38d1627f3814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770566968 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3770566968
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3512187298
Short name T164
Test name
Test status
Simulation time 215378505 ps
CPU time 2.66 seconds
Started Dec 24 12:32:38 PM PST 23
Finished Dec 24 12:33:06 PM PST 23
Peak memory 215752 kb
Host smart-03efe1cd-de63-4047-aa01-3245c536f967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512187298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
512187298
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2616839355
Short name T379
Test name
Test status
Simulation time 14295834 ps
CPU time 0.67 seconds
Started Dec 24 12:32:15 PM PST 23
Finished Dec 24 12:32:41 PM PST 23
Peak memory 204724 kb
Host smart-ec8c6985-0faf-475a-b550-04fcbfa6bf2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616839355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
616839355
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.892230362
Short name T455
Test name
Test status
Simulation time 225517431 ps
CPU time 4.18 seconds
Started Dec 24 12:32:36 PM PST 23
Finished Dec 24 12:33:06 PM PST 23
Peak memory 215768 kb
Host smart-df799181-e624-4bc9-9917-919ffd91a544
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892230362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.892230362
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1599959767
Short name T367
Test name
Test status
Simulation time 138667433 ps
CPU time 8.83 seconds
Started Dec 24 12:32:35 PM PST 23
Finished Dec 24 12:33:09 PM PST 23
Peak memory 215632 kb
Host smart-f1f15a40-d381-466f-a52b-6d7666ac146a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599959767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1599959767
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1895210890
Short name T390
Test name
Test status
Simulation time 127748722 ps
CPU time 3.77 seconds
Started Dec 24 12:32:11 PM PST 23
Finished Dec 24 12:32:40 PM PST 23
Peak memory 215720 kb
Host smart-c754a6d5-b436-415b-bb25-8998f3355b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895210890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1895210890
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3688998044
Short name T447
Test name
Test status
Simulation time 222067131 ps
CPU time 2.01 seconds
Started Dec 24 12:32:21 PM PST 23
Finished Dec 24 12:32:50 PM PST 23
Peak memory 215928 kb
Host smart-ff4287a1-1aec-41b2-aaac-3fe8bc4a48ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688998044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
688998044
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3024856063
Short name T202
Test name
Test status
Simulation time 1419531092 ps
CPU time 21.06 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:33:33 PM PST 23
Peak memory 215672 kb
Host smart-7802cb83-acce-4db8-8f1a-381b3e855c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024856063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3024856063
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2025799780
Short name T372
Test name
Test status
Simulation time 24198775 ps
CPU time 0.7 seconds
Started Dec 24 12:32:58 PM PST 23
Finished Dec 24 12:33:41 PM PST 23
Peak memory 204804 kb
Host smart-a9e93193-5dfb-48f9-9b11-26ecc5973b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025799780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2025799780
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.162121824
Short name T415
Test name
Test status
Simulation time 12791480 ps
CPU time 0.73 seconds
Started Dec 24 12:32:38 PM PST 23
Finished Dec 24 12:33:04 PM PST 23
Peak memory 204836 kb
Host smart-301d4d6d-766f-4325-8b1f-560a100c09d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162121824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.162121824
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.457717766
Short name T371
Test name
Test status
Simulation time 30121365 ps
CPU time 0.7 seconds
Started Dec 24 12:32:45 PM PST 23
Finished Dec 24 12:33:13 PM PST 23
Peak memory 204748 kb
Host smart-e7582222-fbad-45ac-af25-6b8832fb1f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457717766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.457717766
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2803617039
Short name T407
Test name
Test status
Simulation time 44608178 ps
CPU time 0.7 seconds
Started Dec 24 12:32:29 PM PST 23
Finished Dec 24 12:32:56 PM PST 23
Peak memory 204788 kb
Host smart-d398966e-8558-4bb8-bea4-a5fb1807409f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803617039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2803617039
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1142492498
Short name T148
Test name
Test status
Simulation time 98612962 ps
CPU time 0.71 seconds
Started Dec 24 12:32:22 PM PST 23
Finished Dec 24 12:32:49 PM PST 23
Peak memory 204852 kb
Host smart-48be423a-3ca6-4b8d-bf23-f491eeae5225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142492498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1142492498
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2120247654
Short name T450
Test name
Test status
Simulation time 16256338 ps
CPU time 0.71 seconds
Started Dec 24 12:32:42 PM PST 23
Finished Dec 24 12:33:10 PM PST 23
Peak memory 204936 kb
Host smart-cc8ea961-6ccc-4398-87eb-a0366d7a92fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120247654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2120247654
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.95154353
Short name T156
Test name
Test status
Simulation time 53579001 ps
CPU time 0.69 seconds
Started Dec 24 12:32:20 PM PST 23
Finished Dec 24 12:32:47 PM PST 23
Peak memory 204804 kb
Host smart-f9d17605-0594-41eb-91d1-3279b7165310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95154353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.95154353
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3532794846
Short name T435
Test name
Test status
Simulation time 56314323 ps
CPU time 0.8 seconds
Started Dec 24 12:32:51 PM PST 23
Finished Dec 24 12:33:25 PM PST 23
Peak memory 204872 kb
Host smart-b6d7c8a0-8726-420f-97a8-d3bc6ed9cf5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532794846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3532794846
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1854282416
Short name T439
Test name
Test status
Simulation time 15872954 ps
CPU time 0.68 seconds
Started Dec 24 12:33:01 PM PST 23
Finished Dec 24 12:33:44 PM PST 23
Peak memory 204844 kb
Host smart-1b6fd49a-89fd-4384-9b24-983f195fb613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854282416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1854282416
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3579094054
Short name T147
Test name
Test status
Simulation time 37938148 ps
CPU time 1.37 seconds
Started Dec 24 12:32:12 PM PST 23
Finished Dec 24 12:32:38 PM PST 23
Peak memory 216996 kb
Host smart-a938e82a-0865-4c9a-98b5-68de2bfa0e18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579094054 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3579094054
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3769083934
Short name T160
Test name
Test status
Simulation time 101510018 ps
CPU time 2.67 seconds
Started Dec 24 12:32:44 PM PST 23
Finished Dec 24 12:33:15 PM PST 23
Peak memory 215788 kb
Host smart-0758a95a-a95d-4176-9678-93de00b68912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769083934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
769083934
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1891872308
Short name T157
Test name
Test status
Simulation time 43072938 ps
CPU time 0.7 seconds
Started Dec 24 12:32:00 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 204832 kb
Host smart-44f20ac4-1c9b-4e36-925c-cf9e419d25ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891872308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
891872308
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1404344811
Short name T82
Test name
Test status
Simulation time 118102741 ps
CPU time 4.55 seconds
Started Dec 24 12:32:13 PM PST 23
Finished Dec 24 12:32:42 PM PST 23
Peak memory 215676 kb
Host smart-7f025b85-afd5-4379-a39d-f34ac5c11f0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404344811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1404344811
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2886019434
Short name T120
Test name
Test status
Simulation time 110807687 ps
CPU time 3.14 seconds
Started Dec 24 12:32:23 PM PST 23
Finished Dec 24 12:32:53 PM PST 23
Peak memory 215992 kb
Host smart-6d86e1e5-419a-43e9-96cf-0a0ce6c57383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886019434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
886019434
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2382783335
Short name T201
Test name
Test status
Simulation time 207953925 ps
CPU time 11.65 seconds
Started Dec 24 12:32:12 PM PST 23
Finished Dec 24 12:32:48 PM PST 23
Peak memory 215716 kb
Host smart-26504a83-16f7-47f7-b38d-8c5ca2fba579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382783335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2382783335
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3865475868
Short name T393
Test name
Test status
Simulation time 62165412 ps
CPU time 1.85 seconds
Started Dec 24 12:32:31 PM PST 23
Finished Dec 24 12:32:59 PM PST 23
Peak memory 219244 kb
Host smart-f8556664-b84b-4294-909e-3a9aba745782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865475868 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3865475868
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3475368163
Short name T384
Test name
Test status
Simulation time 72717068 ps
CPU time 2.05 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:23 PM PST 23
Peak memory 215744 kb
Host smart-5865995b-66c5-4178-b66b-9fbf49d225a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475368163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
475368163
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1184147777
Short name T67
Test name
Test status
Simulation time 50343069 ps
CPU time 0.75 seconds
Started Dec 24 12:32:14 PM PST 23
Finished Dec 24 12:32:40 PM PST 23
Peak memory 204844 kb
Host smart-3709e706-539a-42c8-8552-7ebcf5c9d8df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184147777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
184147777
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2305576156
Short name T418
Test name
Test status
Simulation time 671356614 ps
CPU time 4.15 seconds
Started Dec 24 12:32:17 PM PST 23
Finished Dec 24 12:32:47 PM PST 23
Peak memory 216928 kb
Host smart-3726ef84-0027-4948-84f3-543d479a9d59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305576156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2305576156
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3742646793
Short name T406
Test name
Test status
Simulation time 199903173 ps
CPU time 5.04 seconds
Started Dec 24 12:32:10 PM PST 23
Finished Dec 24 12:32:41 PM PST 23
Peak memory 215920 kb
Host smart-86675190-e766-4bb6-a62a-b9f7dd575f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742646793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
742646793
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3917172850
Short name T363
Test name
Test status
Simulation time 171617878 ps
CPU time 2.55 seconds
Started Dec 24 12:32:14 PM PST 23
Finished Dec 24 12:32:41 PM PST 23
Peak memory 219708 kb
Host smart-24a142d3-ca51-42ec-b516-b4f6cf7d330b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917172850 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3917172850
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1684561356
Short name T71
Test name
Test status
Simulation time 68415644 ps
CPU time 1.23 seconds
Started Dec 24 12:32:00 PM PST 23
Finished Dec 24 12:32:27 PM PST 23
Peak memory 207516 kb
Host smart-f2779cf2-b463-485b-9f13-bcd98737ddc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684561356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
684561356
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3015398648
Short name T87
Test name
Test status
Simulation time 22703470 ps
CPU time 0.72 seconds
Started Dec 24 12:32:38 PM PST 23
Finished Dec 24 12:33:04 PM PST 23
Peak memory 204860 kb
Host smart-7f9354ea-8d46-4e7d-91fb-6595619f4bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015398648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
015398648
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1135232107
Short name T366
Test name
Test status
Simulation time 240705930 ps
CPU time 2.85 seconds
Started Dec 24 12:32:24 PM PST 23
Finished Dec 24 12:32:54 PM PST 23
Peak memory 215560 kb
Host smart-6fe0aa86-4791-4d53-8898-451387aa7838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135232107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1135232107
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2305280700
Short name T121
Test name
Test status
Simulation time 150732727 ps
CPU time 4.01 seconds
Started Dec 24 12:32:26 PM PST 23
Finished Dec 24 12:32:57 PM PST 23
Peak memory 215964 kb
Host smart-3c440bad-fcc6-4be3-ab56-c05cd9522fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305280700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
305280700
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1467487554
Short name T422
Test name
Test status
Simulation time 6090357475 ps
CPU time 17.42 seconds
Started Dec 24 12:32:28 PM PST 23
Finished Dec 24 12:33:12 PM PST 23
Peak memory 216032 kb
Host smart-abaaa2f2-3ae2-42d2-8d75-6942a9b5867f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467487554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1467487554
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2064286729
Short name T150
Test name
Test status
Simulation time 57354508 ps
CPU time 2.74 seconds
Started Dec 24 12:32:32 PM PST 23
Finished Dec 24 12:33:00 PM PST 23
Peak memory 219600 kb
Host smart-2511bf8e-b905-4c52-8829-5d59d8519a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064286729 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2064286729
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.387122161
Short name T166
Test name
Test status
Simulation time 152102119 ps
CPU time 2.4 seconds
Started Dec 24 12:32:36 PM PST 23
Finished Dec 24 12:33:05 PM PST 23
Peak memory 215764 kb
Host smart-316ed4ce-14a9-4fb3-b787-543ccf3155a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387122161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.387122161
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1981888469
Short name T426
Test name
Test status
Simulation time 41804529 ps
CPU time 0.67 seconds
Started Dec 24 12:32:11 PM PST 23
Finished Dec 24 12:32:37 PM PST 23
Peak memory 204772 kb
Host smart-5d0d3822-9a7b-42bb-8b85-d27330e1006f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981888469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
981888469
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3273184500
Short name T168
Test name
Test status
Simulation time 762818449 ps
CPU time 2.05 seconds
Started Dec 24 12:32:22 PM PST 23
Finished Dec 24 12:32:51 PM PST 23
Peak memory 207416 kb
Host smart-26287451-2576-48e4-8fa8-0d4ead539e74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273184500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3273184500
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.927551116
Short name T123
Test name
Test status
Simulation time 27749549 ps
CPU time 1.91 seconds
Started Dec 24 12:32:08 PM PST 23
Finished Dec 24 12:32:36 PM PST 23
Peak memory 216072 kb
Host smart-8f6b8def-9c4d-4da6-9167-14e68a5c9e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927551116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.927551116
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2183168076
Short name T203
Test name
Test status
Simulation time 2273238305 ps
CPU time 13.18 seconds
Started Dec 24 12:32:01 PM PST 23
Finished Dec 24 12:32:40 PM PST 23
Peak memory 216068 kb
Host smart-37050fcc-7ab3-4670-8a6a-cb9dfa76f38f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183168076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2183168076
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2515643457
Short name T465
Test name
Test status
Simulation time 242015701 ps
CPU time 2.93 seconds
Started Dec 24 12:32:07 PM PST 23
Finished Dec 24 12:32:36 PM PST 23
Peak memory 219280 kb
Host smart-79e545db-d05c-4f77-b679-382e7f1929be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515643457 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2515643457
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3810964689
Short name T158
Test name
Test status
Simulation time 29082967 ps
CPU time 1.9 seconds
Started Dec 24 12:32:01 PM PST 23
Finished Dec 24 12:32:28 PM PST 23
Peak memory 215700 kb
Host smart-99b30879-a830-4fb0-887b-d9e17cc2139a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810964689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
810964689
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3120196474
Short name T181
Test name
Test status
Simulation time 41707539 ps
CPU time 0.72 seconds
Started Dec 24 12:32:49 PM PST 23
Finished Dec 24 12:33:18 PM PST 23
Peak memory 204836 kb
Host smart-7f466637-3bd5-4722-b115-75df265c4cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120196474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
120196474
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2321512974
Short name T437
Test name
Test status
Simulation time 48035009 ps
CPU time 2.85 seconds
Started Dec 24 12:32:08 PM PST 23
Finished Dec 24 12:32:37 PM PST 23
Peak memory 215708 kb
Host smart-8e939dab-f4fe-4360-b9b7-c8bf340a3ff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321512974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2321512974
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.683179109
Short name T424
Test name
Test status
Simulation time 900428501 ps
CPU time 5.43 seconds
Started Dec 24 12:32:21 PM PST 23
Finished Dec 24 12:32:53 PM PST 23
Peak memory 216028 kb
Host smart-92494f40-5936-471c-a491-32bed1211f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683179109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.683179109
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.252944441
Short name T394
Test name
Test status
Simulation time 1632161473 ps
CPU time 17.64 seconds
Started Dec 24 12:32:08 PM PST 23
Finished Dec 24 12:32:52 PM PST 23
Peak memory 216004 kb
Host smart-7a68aa8c-4352-4770-8428-0dff13859f96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252944441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.252944441
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_abort.4158078614
Short name T1384
Test name
Test status
Simulation time 16342547 ps
CPU time 0.71 seconds
Started Dec 24 01:53:27 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 206576 kb
Host smart-c26e470d-a2c1-44e6-8a08-23f5aeaa183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158078614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_abort.4158078614
Directory /workspace/0.spi_device_abort/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3357235408
Short name T1369
Test name
Test status
Simulation time 12793373 ps
CPU time 0.76 seconds
Started Dec 24 01:53:28 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 206536 kb
Host smart-7515cdbf-d06f-430d-b3ec-881d49efe6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357235408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
357235408
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_bit_transfer.1512663994
Short name T587
Test name
Test status
Simulation time 369429254 ps
CPU time 3.03 seconds
Started Dec 24 01:53:26 PM PST 23
Finished Dec 24 01:53:36 PM PST 23
Peak memory 216736 kb
Host smart-332ed16f-18bd-423c-9648-05b1c27f3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512663994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_bit_transfer.1512663994
Directory /workspace/0.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/0.spi_device_byte_transfer.3873258392
Short name T482
Test name
Test status
Simulation time 923592662 ps
CPU time 2.84 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 216908 kb
Host smart-3a136544-b336-4fd9-bd14-170f442a0c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873258392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_byte_transfer.3873258392
Directory /workspace/0.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.67849339
Short name T1013
Test name
Test status
Simulation time 2361245730 ps
CPU time 3.96 seconds
Started Dec 24 01:53:30 PM PST 23
Finished Dec 24 01:53:39 PM PST 23
Peak memory 219672 kb
Host smart-56e70725-4eb0-42ca-a57b-da07055b8eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67849339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.67849339
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.391589845
Short name T954
Test name
Test status
Simulation time 20210783 ps
CPU time 0.75 seconds
Started Dec 24 01:53:11 PM PST 23
Finished Dec 24 01:53:18 PM PST 23
Peak memory 207688 kb
Host smart-ff3ce3bf-b75f-4c3e-81c1-b7dac533b452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391589845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.391589845
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_dummy_item_extra_dly.4121662206
Short name T1559
Test name
Test status
Simulation time 37645044286 ps
CPU time 281.62 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:58:09 PM PST 23
Peak memory 283564 kb
Host smart-9c5bfca7-b67d-4264-bb95-1a12b8814f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121662206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_dummy_item_extra_dly.4121662206
Directory /workspace/0.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/0.spi_device_fifo_full.1331440485
Short name T749
Test name
Test status
Simulation time 53300424250 ps
CPU time 516.62 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 02:02:05 PM PST 23
Peak memory 274384 kb
Host smart-9c260a7f-a27c-481f-9c67-d01ed2939fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331440485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_full.1331440485
Directory /workspace/0.spi_device_fifo_full/latest

Test location /workspace/coverage/default/0.spi_device_fifo_underflow_overflow.2785760453
Short name T1103
Test name
Test status
Simulation time 142242248648 ps
CPU time 503.94 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 02:01:53 PM PST 23
Peak memory 474132 kb
Host smart-3835e006-8e14-48c0-affe-43db4c211b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785760453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_underflow_overfl
ow.2785760453
Directory /workspace/0.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2482547428
Short name T890
Test name
Test status
Simulation time 25578923676 ps
CPU time 28.36 seconds
Started Dec 24 01:53:35 PM PST 23
Finished Dec 24 01:54:05 PM PST 23
Peak memory 234300 kb
Host smart-e6315183-9ca5-4d0c-bd4d-d1d18718aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482547428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2482547428
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.144598003
Short name T1514
Test name
Test status
Simulation time 3405170772 ps
CPU time 66.19 seconds
Started Dec 24 01:53:30 PM PST 23
Finished Dec 24 01:54:41 PM PST 23
Peak memory 254088 kb
Host smart-ae418b23-6beb-416f-ba0e-b8ab9c7a2229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144598003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.144598003
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2033688135
Short name T321
Test name
Test status
Simulation time 216280515339 ps
CPU time 155.75 seconds
Started Dec 24 01:53:35 PM PST 23
Finished Dec 24 01:56:13 PM PST 23
Peak memory 249712 kb
Host smart-a4a5cd3b-f03c-4969-952e-89f9dfe84a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033688135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2033688135
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2616915662
Short name T1210
Test name
Test status
Simulation time 1802836084 ps
CPU time 11.09 seconds
Started Dec 24 01:53:25 PM PST 23
Finished Dec 24 01:53:44 PM PST 23
Peak memory 254868 kb
Host smart-bd2941f0-ab7b-4b72-b908-8991d276a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616915662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2616915662
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1602111652
Short name T1349
Test name
Test status
Simulation time 15651974442 ps
CPU time 12.08 seconds
Started Dec 24 01:53:25 PM PST 23
Finished Dec 24 01:53:45 PM PST 23
Peak memory 225200 kb
Host smart-0a6d686a-e0de-4482-8674-820ec03c5f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602111652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1602111652
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intr.2610584068
Short name T503
Test name
Test status
Simulation time 36345140315 ps
CPU time 29.16 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:54 PM PST 23
Peak memory 233560 kb
Host smart-9316e33b-e8e9-41bd-9156-5c828e81d4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610584068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intr.2610584068
Directory /workspace/0.spi_device_intr/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2750570569
Short name T1651
Test name
Test status
Simulation time 14202879213 ps
CPU time 42.94 seconds
Started Dec 24 01:53:29 PM PST 23
Finished Dec 24 01:54:17 PM PST 23
Peak memory 249732 kb
Host smart-fae0fb15-8152-4740-a47a-79d0fadd592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750570569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2750570569
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.211489256
Short name T1347
Test name
Test status
Simulation time 868928891 ps
CPU time 3.9 seconds
Started Dec 24 01:53:29 PM PST 23
Finished Dec 24 01:53:38 PM PST 23
Peak memory 218748 kb
Host smart-9987e120-dd6c-4d6b-959b-3644fd1393c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211489256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
211489256
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3548865542
Short name T238
Test name
Test status
Simulation time 7458434364 ps
CPU time 22.61 seconds
Started Dec 24 01:53:27 PM PST 23
Finished Dec 24 01:53:56 PM PST 23
Peak memory 230116 kb
Host smart-77d0ec80-bc92-40b9-9958-a44cb4041743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548865542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3548865542
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_perf.947417103
Short name T3
Test name
Test status
Simulation time 5700468144 ps
CPU time 178.22 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 257524 kb
Host smart-a9e6f3ba-c262-4a5b-8bcb-a50824328673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947417103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_perf.947417103
Directory /workspace/0.spi_device_perf/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1488120542
Short name T1411
Test name
Test status
Simulation time 25829137 ps
CPU time 0.75 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:31 PM PST 23
Peak memory 216644 kb
Host smart-abe548e1-d495-4e52-8f84-3f3d5aad1680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488120542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1488120542
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2344555853
Short name T809
Test name
Test status
Simulation time 400378239 ps
CPU time 4.11 seconds
Started Dec 24 01:53:25 PM PST 23
Finished Dec 24 01:53:37 PM PST 23
Peak memory 234336 kb
Host smart-0f7b5c04-0ae5-4ecf-84bd-833390726661
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2344555853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2344555853
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_rx_async_fifo_reset.3843276417
Short name T1261
Test name
Test status
Simulation time 57550675 ps
CPU time 0.86 seconds
Started Dec 24 01:53:28 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 208472 kb
Host smart-6f9616a9-52cc-4b3c-92db-fa65b9c07dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843276417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_async_fifo_reset.3843276417
Directory /workspace/0.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.22229532
Short name T95
Test name
Test status
Simulation time 243181767 ps
CPU time 1.09 seconds
Started Dec 24 01:53:27 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 235800 kb
Host smart-661bf998-3e0d-40f6-a5f6-a803d0009127
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22229532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.22229532
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_smoke.683443270
Short name T524
Test name
Test status
Simulation time 33890755 ps
CPU time 1.03 seconds
Started Dec 24 01:53:22 PM PST 23
Finished Dec 24 01:53:33 PM PST 23
Peak memory 207980 kb
Host smart-5a0a4539-2247-4231-b7f2-fae9232d4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683443270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_smoke.683443270
Directory /workspace/0.spi_device_smoke/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.137982609
Short name T802
Test name
Test status
Simulation time 3967282723 ps
CPU time 33.95 seconds
Started Dec 24 01:53:27 PM PST 23
Finished Dec 24 01:54:08 PM PST 23
Peak memory 220364 kb
Host smart-48db2210-7295-487a-b7ad-c5f2a4cb4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137982609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.137982609
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1556952448
Short name T554
Test name
Test status
Simulation time 2891911533 ps
CPU time 4.38 seconds
Started Dec 24 01:53:27 PM PST 23
Finished Dec 24 01:53:38 PM PST 23
Peak memory 216836 kb
Host smart-01c91a36-6dc3-41bb-a55b-7e105e82cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556952448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1556952448
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3662765121
Short name T1502
Test name
Test status
Simulation time 195809623 ps
CPU time 3.35 seconds
Started Dec 24 01:53:30 PM PST 23
Finished Dec 24 01:53:39 PM PST 23
Peak memory 216828 kb
Host smart-36861aa5-5d43-403a-9b39-f0a671db730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662765121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3662765121
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.447481722
Short name T33
Test name
Test status
Simulation time 38030874 ps
CPU time 0.89 seconds
Started Dec 24 01:53:29 PM PST 23
Finished Dec 24 01:53:36 PM PST 23
Peak memory 207408 kb
Host smart-682d4ce8-c362-4dd8-9c0d-e530974d01ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447481722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.447481722
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tx_async_fifo_reset.3034865944
Short name T550
Test name
Test status
Simulation time 196020919 ps
CPU time 0.84 seconds
Started Dec 24 01:53:29 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 208448 kb
Host smart-4fc6d0a4-ac7e-4b53-a720-0cc73561329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034865944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tx_async_fifo_reset.3034865944
Directory /workspace/0.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/0.spi_device_txrx.2349808792
Short name T946
Test name
Test status
Simulation time 81810014192 ps
CPU time 248.04 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:57:33 PM PST 23
Peak memory 295696 kb
Host smart-5d6c4bc2-e71e-4498-845f-ec858d1cd897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349808792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_txrx.2349808792
Directory /workspace/0.spi_device_txrx/latest

Test location /workspace/coverage/default/0.spi_device_upload.1599883733
Short name T1331
Test name
Test status
Simulation time 414063244 ps
CPU time 3.28 seconds
Started Dec 24 01:53:28 PM PST 23
Finished Dec 24 01:53:37 PM PST 23
Peak memory 238332 kb
Host smart-aea84771-0148-4315-aab5-0d95561867fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599883733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1599883733
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_abort.2123057519
Short name T681
Test name
Test status
Simulation time 62398958 ps
CPU time 0.74 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:06 PM PST 23
Peak memory 206632 kb
Host smart-5c9e4db6-3e5a-4f12-8e40-645794919135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123057519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_abort.2123057519
Directory /workspace/1.spi_device_abort/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.830719315
Short name T915
Test name
Test status
Simulation time 12452457 ps
CPU time 0.74 seconds
Started Dec 24 01:53:56 PM PST 23
Finished Dec 24 01:54:00 PM PST 23
Peak memory 206492 kb
Host smart-f3b756e5-fc58-458d-8460-573756a7ed93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830719315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.830719315
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_bit_transfer.3532964149
Short name T1002
Test name
Test status
Simulation time 547499881 ps
CPU time 2.51 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:08 PM PST 23
Peak memory 216676 kb
Host smart-947255fc-2079-4474-b8df-09f8ce8c639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532964149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_bit_transfer.3532964149
Directory /workspace/1.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/1.spi_device_byte_transfer.3415755054
Short name T623
Test name
Test status
Simulation time 151221124 ps
CPU time 2.97 seconds
Started Dec 24 01:53:27 PM PST 23
Finished Dec 24 01:53:37 PM PST 23
Peak memory 216796 kb
Host smart-88c96bc3-8485-4668-97e3-522edc694c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415755054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_byte_transfer.3415755054
Directory /workspace/1.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1278765199
Short name T1782
Test name
Test status
Simulation time 3990738593 ps
CPU time 12.77 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 241348 kb
Host smart-283ed15c-4634-4edf-aa4d-00b4cca6ab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278765199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1278765199
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1346843119
Short name T884
Test name
Test status
Simulation time 12473082 ps
CPU time 0.75 seconds
Started Dec 24 01:53:28 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 206472 kb
Host smart-578d80ac-780e-429a-b723-218ba8e3d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346843119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1346843119
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_dummy_item_extra_dly.2137118012
Short name T792
Test name
Test status
Simulation time 92418412983 ps
CPU time 726.34 seconds
Started Dec 24 01:53:29 PM PST 23
Finished Dec 24 02:05:41 PM PST 23
Peak memory 313748 kb
Host smart-aa2ecb9f-26e0-465f-b37b-f9c43889c53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137118012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_dummy_item_extra_dly.2137118012
Directory /workspace/1.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/1.spi_device_extreme_fifo_size.1183488582
Short name T1235
Test name
Test status
Simulation time 83260963039 ps
CPU time 4407.51 seconds
Started Dec 24 01:53:26 PM PST 23
Finished Dec 24 03:07:01 PM PST 23
Peak memory 217948 kb
Host smart-b3b25cd6-f77a-4f84-be37-3812c661b4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183488582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_extreme_fifo_size.1183488582
Directory /workspace/1.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/1.spi_device_fifo_full.1389562817
Short name T1485
Test name
Test status
Simulation time 17000326071 ps
CPU time 408.44 seconds
Started Dec 24 01:53:25 PM PST 23
Finished Dec 24 02:00:21 PM PST 23
Peak memory 270880 kb
Host smart-db9b606d-b67e-4046-92d4-4133d4b3addb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389562817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_full.1389562817
Directory /workspace/1.spi_device_fifo_full/latest

Test location /workspace/coverage/default/1.spi_device_fifo_underflow_overflow.4039020390
Short name T836
Test name
Test status
Simulation time 30896415717 ps
CPU time 192.19 seconds
Started Dec 24 01:53:26 PM PST 23
Finished Dec 24 01:56:46 PM PST 23
Peak memory 287660 kb
Host smart-e6752eb5-ba53-49ae-82b5-6b7f284e967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039020390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_underflow_overfl
ow.4039020390
Directory /workspace/1.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1607394455
Short name T234
Test name
Test status
Simulation time 8358798234 ps
CPU time 59.86 seconds
Started Dec 24 01:53:56 PM PST 23
Finished Dec 24 01:54:58 PM PST 23
Peak memory 254620 kb
Host smart-6d4e8ab2-cc64-432f-88ab-0b05dadd9e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607394455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1607394455
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1584563127
Short name T307
Test name
Test status
Simulation time 11597432677 ps
CPU time 108.74 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:55:54 PM PST 23
Peak memory 257508 kb
Host smart-10434d4f-61c7-4aeb-bcaf-8b4b679f935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584563127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1584563127
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3593085620
Short name T235
Test name
Test status
Simulation time 1688721466 ps
CPU time 11.59 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:17 PM PST 23
Peak memory 238488 kb
Host smart-4dbc1ff8-a196-4d4a-841c-bd004f97b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593085620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3593085620
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2677932687
Short name T1638
Test name
Test status
Simulation time 483783647 ps
CPU time 3.34 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:09 PM PST 23
Peak memory 233404 kb
Host smart-a4c3ee3e-e9b4-4444-91ca-53f3d946a3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677932687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2677932687
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intr.511454048
Short name T1048
Test name
Test status
Simulation time 59142784764 ps
CPU time 67.74 seconds
Started Dec 24 01:53:29 PM PST 23
Finished Dec 24 01:54:42 PM PST 23
Peak memory 232652 kb
Host smart-b6fcc834-d51a-4fa0-9951-6e86d22e9095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511454048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intr.511454048
Directory /workspace/1.spi_device_intr/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.617767956
Short name T230
Test name
Test status
Simulation time 38181162957 ps
CPU time 27.84 seconds
Started Dec 24 01:53:53 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 240180 kb
Host smart-e2b3ab08-2fde-4fe3-9cb2-1c0eb0f9c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617767956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.617767956
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1413370729
Short name T1481
Test name
Test status
Simulation time 155940883 ps
CPU time 1.04 seconds
Started Dec 24 01:53:55 PM PST 23
Finished Dec 24 01:53:59 PM PST 23
Peak memory 218956 kb
Host smart-bf34a3f0-c1cb-4acf-a66f-fe3b275fa5f4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413370729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1413370729
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3462594943
Short name T829
Test name
Test status
Simulation time 4664280017 ps
CPU time 13.32 seconds
Started Dec 24 01:53:56 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 239792 kb
Host smart-e106d5e2-02f8-407a-b5b7-6e7e4ecf3e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462594943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3462594943
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_perf.2570407211
Short name T686
Test name
Test status
Simulation time 10097856471 ps
CPU time 115.62 seconds
Started Dec 24 01:53:34 PM PST 23
Finished Dec 24 01:55:32 PM PST 23
Peak memory 249228 kb
Host smart-470641c5-17c7-4065-b3fe-37f4c6674385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570407211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_perf.2570407211
Directory /workspace/1.spi_device_perf/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.885016449
Short name T1680
Test name
Test status
Simulation time 41203191 ps
CPU time 0.73 seconds
Started Dec 24 01:54:03 PM PST 23
Finished Dec 24 01:54:05 PM PST 23
Peak memory 216700 kb
Host smart-6d1cce5e-d55e-4396-b5c5-597033c2fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885016449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.885016449
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.985877019
Short name T697
Test name
Test status
Simulation time 797547532 ps
CPU time 5.33 seconds
Started Dec 24 01:53:41 PM PST 23
Finished Dec 24 01:53:48 PM PST 23
Peak memory 218892 kb
Host smart-e5f811cc-2406-407e-85d2-9a334663fd19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=985877019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.985877019
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_rx_async_fifo_reset.734733939
Short name T1462
Test name
Test status
Simulation time 207558827 ps
CPU time 0.91 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:53:57 PM PST 23
Peak memory 208488 kb
Host smart-5c3095fc-4d70-46b8-b22a-68ec26effb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734733939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_async_fifo_reset.734733939
Directory /workspace/1.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_rx_timeout.3896657092
Short name T676
Test name
Test status
Simulation time 2321200019 ps
CPU time 5.61 seconds
Started Dec 24 01:53:36 PM PST 23
Finished Dec 24 01:53:43 PM PST 23
Peak memory 216884 kb
Host smart-c21c9aaf-eb38-433c-a2ea-db441a58d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896657092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_timeout.3896657092
Directory /workspace/1.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/1.spi_device_smoke.4099156204
Short name T1026
Test name
Test status
Simulation time 32156971 ps
CPU time 1.12 seconds
Started Dec 24 01:53:28 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 208340 kb
Host smart-bacb86a8-e77f-4d22-be67-3dd7448c8e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099156204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_smoke.4099156204
Directory /workspace/1.spi_device_smoke/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.161069459
Short name T1610
Test name
Test status
Simulation time 41718190931 ps
CPU time 150.25 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 222360 kb
Host smart-bf45206e-56aa-49ae-bc2d-a3b9c7b7ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161069459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.161069459
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1401245664
Short name T1663
Test name
Test status
Simulation time 509231546 ps
CPU time 3.43 seconds
Started Dec 24 01:53:53 PM PST 23
Finished Dec 24 01:53:57 PM PST 23
Peak memory 216776 kb
Host smart-978f0259-404b-4e73-8b60-58a11dff75c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401245664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1401245664
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3244472160
Short name T886
Test name
Test status
Simulation time 49413997 ps
CPU time 1.14 seconds
Started Dec 24 01:53:53 PM PST 23
Finished Dec 24 01:53:56 PM PST 23
Peak memory 208304 kb
Host smart-49966336-1de5-417c-8895-f4f9e2b8f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244472160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3244472160
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.210552700
Short name T654
Test name
Test status
Simulation time 122191728 ps
CPU time 0.9 seconds
Started Dec 24 01:54:06 PM PST 23
Finished Dec 24 01:54:10 PM PST 23
Peak memory 206956 kb
Host smart-b7377c87-57cb-4842-a56f-6c387af68d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210552700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.210552700
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3937679060
Short name T1489
Test name
Test status
Simulation time 14871235 ps
CPU time 0.79 seconds
Started Dec 24 01:53:56 PM PST 23
Finished Dec 24 01:53:59 PM PST 23
Peak memory 208440 kb
Host smart-b0968f2b-a517-4783-8ef5-4d04f09dc8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937679060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tx_async_fifo_reset.3937679060
Directory /workspace/1.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/1.spi_device_txrx.3208660443
Short name T1709
Test name
Test status
Simulation time 105016086368 ps
CPU time 1235.18 seconds
Started Dec 24 01:53:30 PM PST 23
Finished Dec 24 02:14:10 PM PST 23
Peak memory 290840 kb
Host smart-369b534d-b292-4a87-acdf-2bd99efe7e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208660443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_txrx.3208660443
Directory /workspace/1.spi_device_txrx/latest

Test location /workspace/coverage/default/1.spi_device_upload.620669958
Short name T1763
Test name
Test status
Simulation time 515190088 ps
CPU time 3.85 seconds
Started Dec 24 01:53:56 PM PST 23
Finished Dec 24 01:54:02 PM PST 23
Peak memory 239244 kb
Host smart-36004c9b-e7e5-46c7-8866-bb9290a0f0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620669958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.620669958
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_abort.3423334616
Short name T805
Test name
Test status
Simulation time 14644636 ps
CPU time 0.76 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 206608 kb
Host smart-47805262-e3db-40f6-be60-4147c50c8afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423334616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_abort.3423334616
Directory /workspace/10.spi_device_abort/latest

Test location /workspace/coverage/default/10.spi_device_bit_transfer.568542396
Short name T1778
Test name
Test status
Simulation time 1152525183 ps
CPU time 2.33 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 01:54:36 PM PST 23
Peak memory 216764 kb
Host smart-6fb7c655-da08-495c-a854-514ef76d96fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568542396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_bit_transfer.568542396
Directory /workspace/10.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/10.spi_device_byte_transfer.119242316
Short name T1063
Test name
Test status
Simulation time 586813202 ps
CPU time 2.53 seconds
Started Dec 24 01:54:45 PM PST 23
Finished Dec 24 01:54:49 PM PST 23
Peak memory 216732 kb
Host smart-26bcd366-7357-4730-8469-24ff39c5ae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119242316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_byte_transfer.119242316
Directory /workspace/10.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3963679930
Short name T1717
Test name
Test status
Simulation time 695681896 ps
CPU time 2.43 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 01:54:37 PM PST 23
Peak memory 218144 kb
Host smart-c90b7287-a04c-4e17-ab2e-147f7d4b6822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963679930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3963679930
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.296191160
Short name T785
Test name
Test status
Simulation time 21034078 ps
CPU time 0.74 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 207484 kb
Host smart-182698ab-0a9a-410b-9f58-a14512128278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296191160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.296191160
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_dummy_item_extra_dly.3218290241
Short name T1267
Test name
Test status
Simulation time 99824545139 ps
CPU time 192.1 seconds
Started Dec 24 01:54:28 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 239700 kb
Host smart-1881f4f7-cbe3-4167-8d8e-69ab6d344ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218290241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_dummy_item_extra_dly.3218290241
Directory /workspace/10.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/10.spi_device_extreme_fifo_size.4106069991
Short name T608
Test name
Test status
Simulation time 97762690787 ps
CPU time 987.64 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 02:11:01 PM PST 23
Peak memory 225088 kb
Host smart-ac744ff3-addb-4740-9ef2-cca2b459beab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106069991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_extreme_fifo_size.4106069991
Directory /workspace/10.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/10.spi_device_fifo_full.2101929225
Short name T1141
Test name
Test status
Simulation time 7694738558 ps
CPU time 449.29 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 02:02:02 PM PST 23
Peak memory 289608 kb
Host smart-2bcff474-77c3-44e7-ad68-081bc257ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101929225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_full.2101929225
Directory /workspace/10.spi_device_fifo_full/latest

Test location /workspace/coverage/default/10.spi_device_fifo_underflow_overflow.3667882274
Short name T1329
Test name
Test status
Simulation time 162855570819 ps
CPU time 679.29 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 02:05:53 PM PST 23
Peak memory 419124 kb
Host smart-909d1af3-4a21-4ed1-b20d-86b59cae9a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667882274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_underflow_overf
low.3667882274
Directory /workspace/10.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2982156778
Short name T814
Test name
Test status
Simulation time 9157641159 ps
CPU time 71.94 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:55:46 PM PST 23
Peak memory 266064 kb
Host smart-77e79afc-3bbd-47a9-914b-2e20aa5450c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982156778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2982156778
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1871587301
Short name T253
Test name
Test status
Simulation time 157583651943 ps
CPU time 274.76 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 01:59:09 PM PST 23
Peak memory 254008 kb
Host smart-ccf23239-d8a1-4477-af80-afb0bb7c149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871587301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1871587301
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.466637021
Short name T1265
Test name
Test status
Simulation time 48278679640 ps
CPU time 97.7 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:56:11 PM PST 23
Peak memory 251224 kb
Host smart-1b9ee82d-84fe-4fb0-b2e1-430c4cee4164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466637021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.466637021
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.971279753
Short name T1440
Test name
Test status
Simulation time 2026983204 ps
CPU time 15.32 seconds
Started Dec 24 01:54:28 PM PST 23
Finished Dec 24 01:54:49 PM PST 23
Peak memory 241468 kb
Host smart-b64d9ba6-a92b-4ea9-84e6-492bb219ed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971279753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.971279753
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.449707203
Short name T1294
Test name
Test status
Simulation time 2071868739 ps
CPU time 4.64 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 01:54:39 PM PST 23
Peak memory 220144 kb
Host smart-bb7cd851-0324-4d58-8d42-98ffecf78cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449707203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.449707203
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intr.3516194054
Short name T1298
Test name
Test status
Simulation time 10915201345 ps
CPU time 42.11 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:55:13 PM PST 23
Peak memory 221804 kb
Host smart-6c48abe6-0f3b-4ca1-8a4c-1283e219bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516194054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intr.3516194054
Directory /workspace/10.spi_device_intr/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4119466384
Short name T209
Test name
Test status
Simulation time 100179226 ps
CPU time 3.09 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:38 PM PST 23
Peak memory 234292 kb
Host smart-26a4daeb-a616-41b1-ab50-991fd8c6c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119466384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4119466384
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1754196393
Short name T1575
Test name
Test status
Simulation time 43765319 ps
CPU time 1.05 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 01:54:37 PM PST 23
Peak memory 218756 kb
Host smart-5ba1a011-9737-4e91-89a0-ea9dc24c540f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754196393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1754196393
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2065817415
Short name T1340
Test name
Test status
Simulation time 1772570322 ps
CPU time 18.51 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:49 PM PST 23
Peak memory 257692 kb
Host smart-af33d96e-d320-4410-82b1-55d38068bf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065817415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2065817415
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1298877299
Short name T973
Test name
Test status
Simulation time 615019265 ps
CPU time 8.23 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:43 PM PST 23
Peak memory 230312 kb
Host smart-e4d62fd8-1a8e-43e7-89d2-646ee67df057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298877299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1298877299
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_perf.3599276126
Short name T1296
Test name
Test status
Simulation time 19021693124 ps
CPU time 417.01 seconds
Started Dec 24 01:54:24 PM PST 23
Finished Dec 24 02:01:29 PM PST 23
Peak memory 273056 kb
Host smart-cd805660-d24d-4a8d-89b3-ee6f8d66c85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599276126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_perf.3599276126
Directory /workspace/10.spi_device_perf/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3678842773
Short name T176
Test name
Test status
Simulation time 7980617009 ps
CPU time 4.79 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:39 PM PST 23
Peak memory 234712 kb
Host smart-c0cd9862-aba1-4ff3-8c89-6ecbb975192a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3678842773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3678842773
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_rx_timeout.3381725674
Short name T812
Test name
Test status
Simulation time 1262624021 ps
CPU time 5.75 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:39 PM PST 23
Peak memory 216688 kb
Host smart-8c1505d4-8b50-427a-bc74-3fa2f4122aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381725674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_timeout.3381725674
Directory /workspace/10.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/10.spi_device_smoke.718854019
Short name T1368
Test name
Test status
Simulation time 27443937 ps
CPU time 1.01 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 208248 kb
Host smart-077af939-3383-45e2-b3ba-a8c8142c6bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718854019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_smoke.718854019
Directory /workspace/10.spi_device_smoke/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.102405125
Short name T1439
Test name
Test status
Simulation time 90581431442 ps
CPU time 657.8 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 02:05:32 PM PST 23
Peak memory 315360 kb
Host smart-fc589f69-856a-4816-9fa4-13bb547e14d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102405125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.102405125
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3336580444
Short name T1637
Test name
Test status
Simulation time 12189245898 ps
CPU time 110.16 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 01:56:24 PM PST 23
Peak memory 217088 kb
Host smart-0e53ff25-415b-4c71-a07b-e27092642886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336580444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3336580444
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2389508970
Short name T1125
Test name
Test status
Simulation time 7250950255 ps
CPU time 10.56 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:44 PM PST 23
Peak memory 216808 kb
Host smart-1914d597-0fd9-42d0-869c-359e73350ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389508970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2389508970
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3640622637
Short name T1490
Test name
Test status
Simulation time 231957138 ps
CPU time 7.5 seconds
Started Dec 24 01:54:44 PM PST 23
Finished Dec 24 01:54:52 PM PST 23
Peak memory 216472 kb
Host smart-0d8b1922-e9c6-4a4e-af7a-cf2dde7e1a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640622637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3640622637
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1278453920
Short name T606
Test name
Test status
Simulation time 49101949 ps
CPU time 0.79 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 206836 kb
Host smart-6374f295-ee87-4598-9463-a2b073552ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278453920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1278453920
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tx_async_fifo_reset.1194439931
Short name T1126
Test name
Test status
Simulation time 95758994 ps
CPU time 0.75 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 01:54:36 PM PST 23
Peak memory 208416 kb
Host smart-be2dd46c-9ced-42d6-854c-e4c16e083ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194439931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tx_async_fifo_reset.1194439931
Directory /workspace/10.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/10.spi_device_txrx.2292367542
Short name T990
Test name
Test status
Simulation time 72685008395 ps
CPU time 340.6 seconds
Started Dec 24 01:54:28 PM PST 23
Finished Dec 24 02:00:14 PM PST 23
Peak memory 277392 kb
Host smart-545bc60a-5573-4df7-af53-f41636a7ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292367542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_txrx.2292367542
Directory /workspace/10.spi_device_txrx/latest

Test location /workspace/coverage/default/10.spi_device_upload.136394540
Short name T819
Test name
Test status
Simulation time 6732015874 ps
CPU time 13.63 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:47 PM PST 23
Peak memory 230176 kb
Host smart-fc5f1709-f8d5-48e9-a615-50ebdbc67315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136394540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.136394540
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_abort.1207692227
Short name T1199
Test name
Test status
Simulation time 89394435 ps
CPU time 0.79 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 206620 kb
Host smart-5190f52f-c178-46b6-8c32-023f80c75cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207692227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_abort.1207692227
Directory /workspace/11.spi_device_abort/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.139708247
Short name T1686
Test name
Test status
Simulation time 22622954 ps
CPU time 0.75 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:54:59 PM PST 23
Peak memory 206364 kb
Host smart-9addb8f0-06c3-4ee0-92e6-468ae2b80963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139708247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.139708247
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_bit_transfer.1585112191
Short name T497
Test name
Test status
Simulation time 2127722404 ps
CPU time 2.84 seconds
Started Dec 24 01:54:25 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 216808 kb
Host smart-0f016d55-8f35-4a0c-a220-2010a063e3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585112191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_bit_transfer.1585112191
Directory /workspace/11.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/11.spi_device_byte_transfer.2566129245
Short name T1528
Test name
Test status
Simulation time 260796086 ps
CPU time 2.97 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:54:36 PM PST 23
Peak memory 216696 kb
Host smart-ba207e1d-36fe-439e-856e-7fe704b97a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566129245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_byte_transfer.2566129245
Directory /workspace/11.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1522903278
Short name T311
Test name
Test status
Simulation time 413894488 ps
CPU time 4.32 seconds
Started Dec 24 01:54:45 PM PST 23
Finished Dec 24 01:54:51 PM PST 23
Peak memory 238000 kb
Host smart-90bb47e4-91d4-4a6e-aa6a-477efa4c72eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522903278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1522903278
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.41261637
Short name T637
Test name
Test status
Simulation time 19496612 ps
CPU time 0.74 seconds
Started Dec 24 01:54:44 PM PST 23
Finished Dec 24 01:54:45 PM PST 23
Peak memory 206444 kb
Host smart-cc803b71-7fc4-4ac9-915b-8424e6ab0aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41261637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.41261637
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_dummy_item_extra_dly.3844688044
Short name T1120
Test name
Test status
Simulation time 21072451748 ps
CPU time 172.05 seconds
Started Dec 24 01:54:38 PM PST 23
Finished Dec 24 01:57:31 PM PST 23
Peak memory 228028 kb
Host smart-8bbf1f89-ba75-48d0-a28e-240f9450fb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844688044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_dummy_item_extra_dly.3844688044
Directory /workspace/11.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/11.spi_device_extreme_fifo_size.783415597
Short name T101
Test name
Test status
Simulation time 49198946816 ps
CPU time 44.87 seconds
Started Dec 24 01:54:45 PM PST 23
Finished Dec 24 01:55:31 PM PST 23
Peak memory 223736 kb
Host smart-68a85ea2-325c-4ede-aca0-2488b7fa720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783415597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_extreme_fifo_size.783415597
Directory /workspace/11.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/11.spi_device_fifo_full.4016805373
Short name T555
Test name
Test status
Simulation time 378378154473 ps
CPU time 2539.52 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 02:36:55 PM PST 23
Peak memory 307052 kb
Host smart-a13cbf97-8c36-4d3c-b05f-1d9c0c8200d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016805373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_full.4016805373
Directory /workspace/11.spi_device_fifo_full/latest

Test location /workspace/coverage/default/11.spi_device_fifo_underflow_overflow.4057241717
Short name T1229
Test name
Test status
Simulation time 46479629009 ps
CPU time 515.83 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 02:03:11 PM PST 23
Peak memory 450236 kb
Host smart-e6dbe585-d3a8-4cd8-8fef-8ba830bfaff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057241717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_underflow_overf
low.4057241717
Directory /workspace/11.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3213972185
Short name T356
Test name
Test status
Simulation time 20914403399 ps
CPU time 84.44 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:55:59 PM PST 23
Peak memory 249788 kb
Host smart-af42d2d2-170e-4d77-a580-6985b8a25758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213972185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3213972185
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2415646700
Short name T225
Test name
Test status
Simulation time 259562679914 ps
CPU time 324.58 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:59:59 PM PST 23
Peak memory 254500 kb
Host smart-5735a0b8-82b3-4ac0-bea5-6c2485516167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415646700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2415646700
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2612499528
Short name T1595
Test name
Test status
Simulation time 15775964410 ps
CPU time 20.53 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:54 PM PST 23
Peak memory 249680 kb
Host smart-69ae09f2-2296-4c0b-a3c8-51ae051e60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612499528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2612499528
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3838801054
Short name T1725
Test name
Test status
Simulation time 249224225 ps
CPU time 5.03 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:54:38 PM PST 23
Peak memory 241400 kb
Host smart-e183d004-7752-4a3f-bef6-3d802ece8700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838801054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3838801054
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intr.974861741
Short name T476
Test name
Test status
Simulation time 3949643433 ps
CPU time 24.33 seconds
Started Dec 24 01:54:38 PM PST 23
Finished Dec 24 01:55:03 PM PST 23
Peak memory 222488 kb
Host smart-a637058d-37ec-4784-beb2-c428e672b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974861741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intr.974861741
Directory /workspace/11.spi_device_intr/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1709691283
Short name T1015
Test name
Test status
Simulation time 77084832242 ps
CPU time 49.73 seconds
Started Dec 24 01:54:31 PM PST 23
Finished Dec 24 01:55:24 PM PST 23
Peak memory 249456 kb
Host smart-50c88dc1-96ec-48a8-81d1-358843357d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709691283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1709691283
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1604762121
Short name T1464
Test name
Test status
Simulation time 41521096 ps
CPU time 1.05 seconds
Started Dec 24 01:54:45 PM PST 23
Finished Dec 24 01:54:48 PM PST 23
Peak memory 218832 kb
Host smart-ce01e825-0192-43e0-ab04-d81ff7e9b13f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604762121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1604762121
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1736032291
Short name T1012
Test name
Test status
Simulation time 49502066950 ps
CPU time 14.32 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:47 PM PST 23
Peak memory 241268 kb
Host smart-e8dee9c1-4bc0-4381-874d-53d73a1ce3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736032291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1736032291
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1402569630
Short name T1570
Test name
Test status
Simulation time 1835456496 ps
CPU time 12.29 seconds
Started Dec 24 01:54:28 PM PST 23
Finished Dec 24 01:54:46 PM PST 23
Peak memory 239348 kb
Host smart-b2add4d4-e0d3-4fdc-a5fb-f086f5f54975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402569630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1402569630
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_perf.870511417
Short name T1154
Test name
Test status
Simulation time 42836877860 ps
CPU time 352.1 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 02:00:28 PM PST 23
Peak memory 274036 kb
Host smart-9b0fc18c-a144-44e7-9d4f-c9865600aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870511417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_perf.870511417
Directory /workspace/11.spi_device_perf/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.295033632
Short name T574
Test name
Test status
Simulation time 20982410 ps
CPU time 0.71 seconds
Started Dec 24 01:54:25 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 216700 kb
Host smart-7a4f963b-dbd1-41fd-ac2e-8026cbeb7d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295033632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.295033632
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2342040914
Short name T1517
Test name
Test status
Simulation time 1120650964 ps
CPU time 5.78 seconds
Started Dec 24 01:54:28 PM PST 23
Finished Dec 24 01:54:39 PM PST 23
Peak memory 218724 kb
Host smart-9c96be3c-87d9-45bc-9a0c-eba0f6305092
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2342040914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2342040914
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_rx_async_fifo_reset.2760553478
Short name T1081
Test name
Test status
Simulation time 49756383 ps
CPU time 0.93 seconds
Started Dec 24 01:54:39 PM PST 23
Finished Dec 24 01:54:41 PM PST 23
Peak memory 208508 kb
Host smart-b6fabfd1-cfe2-4428-8352-2f6cd152f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760553478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_async_fifo_reset.2760553478
Directory /workspace/11.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_rx_timeout.619185772
Short name T1316
Test name
Test status
Simulation time 653886554 ps
CPU time 5.17 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 01:54:40 PM PST 23
Peak memory 216740 kb
Host smart-5ecaad4b-9a20-4b4c-9904-bd7911b65f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619185772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_timeout.619185772
Directory /workspace/11.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/11.spi_device_smoke.615167715
Short name T717
Test name
Test status
Simulation time 97835834 ps
CPU time 1.03 seconds
Started Dec 24 01:54:30 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 216492 kb
Host smart-8c32a6a1-f591-470e-9791-f5d9eb9657eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615167715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_smoke.615167715
Directory /workspace/11.spi_device_smoke/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3311729521
Short name T1098
Test name
Test status
Simulation time 3621779022 ps
CPU time 42.26 seconds
Started Dec 24 01:54:39 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 221860 kb
Host smart-82878768-5ad2-40a0-af00-9cac88e52b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311729521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3311729521
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2382127395
Short name T601
Test name
Test status
Simulation time 3146670671 ps
CPU time 11.08 seconds
Started Dec 24 01:54:38 PM PST 23
Finished Dec 24 01:54:50 PM PST 23
Peak memory 216964 kb
Host smart-c31af294-f6fe-4edc-9873-fdfbc1e45aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382127395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2382127395
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3711160481
Short name T1130
Test name
Test status
Simulation time 204870238 ps
CPU time 2.11 seconds
Started Dec 24 01:54:44 PM PST 23
Finished Dec 24 01:54:47 PM PST 23
Peak memory 216728 kb
Host smart-b5031270-f10c-4006-80b8-f684bdca170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711160481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3711160481
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3847786725
Short name T1671
Test name
Test status
Simulation time 304078044 ps
CPU time 1.13 seconds
Started Dec 24 01:54:31 PM PST 23
Finished Dec 24 01:54:36 PM PST 23
Peak memory 208324 kb
Host smart-caba4e8e-441d-4774-8803-07a09d4b2d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847786725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3847786725
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tx_async_fifo_reset.880801445
Short name T715
Test name
Test status
Simulation time 13807652 ps
CPU time 0.79 seconds
Started Dec 24 01:54:37 PM PST 23
Finished Dec 24 01:54:39 PM PST 23
Peak memory 208464 kb
Host smart-ed7efd37-de14-4fd8-9625-0cac3a4e1149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880801445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tx_async_fifo_reset.880801445
Directory /workspace/11.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/11.spi_device_txrx.2830787134
Short name T901
Test name
Test status
Simulation time 28857264539 ps
CPU time 256.59 seconds
Started Dec 24 01:54:44 PM PST 23
Finished Dec 24 01:59:01 PM PST 23
Peak memory 284956 kb
Host smart-1e7cc49e-d583-4d3a-8ea5-c19704e20524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830787134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_txrx.2830787134
Directory /workspace/11.spi_device_txrx/latest

Test location /workspace/coverage/default/11.spi_device_upload.3666041485
Short name T255
Test name
Test status
Simulation time 2087027042 ps
CPU time 9.96 seconds
Started Dec 24 01:54:32 PM PST 23
Finished Dec 24 01:54:45 PM PST 23
Peak memory 238136 kb
Host smart-cfd44c12-5652-4856-905e-016b54e16438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666041485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3666041485
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_abort.2061048324
Short name T1370
Test name
Test status
Simulation time 40353659 ps
CPU time 0.72 seconds
Started Dec 24 01:55:54 PM PST 23
Finished Dec 24 01:55:56 PM PST 23
Peak memory 206664 kb
Host smart-c6e9c789-bad2-4734-b91e-b700d0aa1138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061048324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_abort.2061048324
Directory /workspace/12.spi_device_abort/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1472617718
Short name T760
Test name
Test status
Simulation time 14013229 ps
CPU time 0.74 seconds
Started Dec 24 01:55:56 PM PST 23
Finished Dec 24 01:55:58 PM PST 23
Peak memory 206496 kb
Host smart-30bd5d42-0ccb-4311-98dc-b16f799f1faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472617718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1472617718
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_bit_transfer.267036558
Short name T1171
Test name
Test status
Simulation time 1264528436 ps
CPU time 3.06 seconds
Started Dec 24 01:55:35 PM PST 23
Finished Dec 24 01:55:38 PM PST 23
Peak memory 216820 kb
Host smart-7f79d2b2-86a5-43fb-acaa-80cea64e5f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267036558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_bit_transfer.267036558
Directory /workspace/12.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/12.spi_device_byte_transfer.1758043749
Short name T1099
Test name
Test status
Simulation time 285364758 ps
CPU time 3.79 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 216760 kb
Host smart-2741a5e1-e624-40ba-8a6c-988b8636e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758043749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_byte_transfer.1758043749
Directory /workspace/12.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2260200693
Short name T279
Test name
Test status
Simulation time 234438490 ps
CPU time 4.92 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 239844 kb
Host smart-7de12e65-b68a-49f7-8650-148133b1dba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260200693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2260200693
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1463842229
Short name T720
Test name
Test status
Simulation time 19447627 ps
CPU time 0.79 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:00 PM PST 23
Peak memory 206568 kb
Host smart-19ba381b-6a78-477c-821d-b8e3133da88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463842229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1463842229
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_extreme_fifo_size.75774804
Short name T1714
Test name
Test status
Simulation time 20510805450 ps
CPU time 180.3 seconds
Started Dec 24 01:55:02 PM PST 23
Finished Dec 24 01:58:03 PM PST 23
Peak memory 222296 kb
Host smart-5bad3b69-4c05-4370-a46f-b235a72f4466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75774804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_extreme_fifo_size.75774804
Directory /workspace/12.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/12.spi_device_fifo_full.1939926617
Short name T705
Test name
Test status
Simulation time 31080087732 ps
CPU time 693.04 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 02:06:33 PM PST 23
Peak memory 290636 kb
Host smart-731dfd75-3fee-4214-8699-7ab6220148ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939926617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_full.1939926617
Directory /workspace/12.spi_device_fifo_full/latest

Test location /workspace/coverage/default/12.spi_device_fifo_underflow_overflow.3046065038
Short name T1743
Test name
Test status
Simulation time 55621018904 ps
CPU time 324.71 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 02:00:25 PM PST 23
Peak memory 521204 kb
Host smart-048012db-d88b-4139-93c1-84e63b2fe1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046065038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_underflow_overf
low.3046065038
Directory /workspace/12.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3858548607
Short name T7
Test name
Test status
Simulation time 113161565502 ps
CPU time 446.92 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 02:03:48 PM PST 23
Peak memory 257028 kb
Host smart-389cb0f7-6852-44cb-affc-d39421dd59af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858548607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3858548607
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3364665172
Short name T1527
Test name
Test status
Simulation time 30379218042 ps
CPU time 76.24 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:57:30 PM PST 23
Peak memory 249792 kb
Host smart-d3c9d597-33c0-49e9-98ed-3416db7e42db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364665172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3364665172
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2160864109
Short name T1494
Test name
Test status
Simulation time 114117779 ps
CPU time 2.75 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:41 PM PST 23
Peak memory 218304 kb
Host smart-12cc38ee-1968-4d8f-afea-b5687af9fd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160864109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2160864109
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intr.3449289593
Short name T1287
Test name
Test status
Simulation time 18713031080 ps
CPU time 37.68 seconds
Started Dec 24 01:55:11 PM PST 23
Finished Dec 24 01:55:49 PM PST 23
Peak memory 240340 kb
Host smart-665844dc-dd7f-443e-a395-df773250b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449289593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intr.3449289593
Directory /workspace/12.spi_device_intr/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1769933940
Short name T1244
Test name
Test status
Simulation time 1187645066 ps
CPU time 15.52 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:55 PM PST 23
Peak memory 241432 kb
Host smart-0fac3800-e23b-4ed9-a99e-c60c488549dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769933940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1769933940
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3703942397
Short name T45
Test name
Test status
Simulation time 31481674 ps
CPU time 1.06 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 218900 kb
Host smart-5a2a8cca-d856-4dc6-b16d-a16ab505cb27
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703942397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3703942397
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1701787518
Short name T250
Test name
Test status
Simulation time 4526477218 ps
CPU time 5.93 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:44 PM PST 23
Peak memory 219156 kb
Host smart-2bb9fa4a-b39e-4d0d-aa24-3b15d6197f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701787518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1701787518
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1266010923
Short name T904
Test name
Test status
Simulation time 8643607779 ps
CPU time 16.68 seconds
Started Dec 24 01:55:32 PM PST 23
Finished Dec 24 01:55:49 PM PST 23
Peak memory 235708 kb
Host smart-3b7e2a99-3564-4f2d-88c4-b45ae541953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266010923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1266010923
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_perf.2477761839
Short name T540
Test name
Test status
Simulation time 53319708955 ps
CPU time 546.3 seconds
Started Dec 24 01:54:55 PM PST 23
Finished Dec 24 02:04:04 PM PST 23
Peak memory 282028 kb
Host smart-872e1ada-6798-496c-b08c-5a26ba27df58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477761839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_perf.2477761839
Directory /workspace/12.spi_device_perf/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3730999383
Short name T1629
Test name
Test status
Simulation time 120357262 ps
CPU time 0.72 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:18 PM PST 23
Peak memory 216816 kb
Host smart-f27967d9-5e8e-49b5-8d9b-68aa3d3a30a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730999383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3730999383
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3007110401
Short name T1017
Test name
Test status
Simulation time 1448506026 ps
CPU time 4.46 seconds
Started Dec 24 01:56:00 PM PST 23
Finished Dec 24 01:56:06 PM PST 23
Peak memory 220156 kb
Host smart-21931b3f-3d8e-49f1-a0ca-553bed42aabc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3007110401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3007110401
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_rx_async_fifo_reset.200723891
Short name T1362
Test name
Test status
Simulation time 19523996 ps
CPU time 0.88 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:18 PM PST 23
Peak memory 208452 kb
Host smart-94c71eaa-d8f2-4918-b879-5ef84fd74139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200723891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_async_fifo_reset.200723891
Directory /workspace/12.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_rx_timeout.2871275184
Short name T1356
Test name
Test status
Simulation time 788689043 ps
CPU time 6.08 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 216884 kb
Host smart-565db83a-6d98-409c-86c0-f87e05e165ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871275184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_timeout.2871275184
Directory /workspace/12.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/12.spi_device_smoke.3815184174
Short name T1587
Test name
Test status
Simulation time 33855451 ps
CPU time 1.14 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:02 PM PST 23
Peak memory 208296 kb
Host smart-507755ca-354b-4ef4-b78c-99430f68fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815184174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_smoke.3815184174
Directory /workspace/12.spi_device_smoke/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2717803269
Short name T1230
Test name
Test status
Simulation time 374281988766 ps
CPU time 1463.8 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 02:20:27 PM PST 23
Peak memory 409084 kb
Host smart-4bb7f215-366c-4361-beae-16fa5940e67d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717803269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2717803269
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2078302870
Short name T1395
Test name
Test status
Simulation time 27204686305 ps
CPU time 54.08 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:56:10 PM PST 23
Peak memory 217020 kb
Host smart-b715425e-80f0-436e-81a0-e7c87e345126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078302870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2078302870
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3847542035
Short name T955
Test name
Test status
Simulation time 3473091492 ps
CPU time 16.8 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:56 PM PST 23
Peak memory 216940 kb
Host smart-5ac461f8-74ba-4975-8a4f-7e24f0daa16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847542035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3847542035
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3077835261
Short name T1685
Test name
Test status
Simulation time 168639387 ps
CPU time 4.59 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 217044 kb
Host smart-47056e3b-0eb4-46e5-a17d-0bceacea1488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077835261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3077835261
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3242876405
Short name T1074
Test name
Test status
Simulation time 52779373 ps
CPU time 0.71 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:20 PM PST 23
Peak memory 207032 kb
Host smart-2dd19b82-226b-47a6-beec-c7ec04a37ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242876405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3242876405
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tx_async_fifo_reset.4239777581
Short name T740
Test name
Test status
Simulation time 17247631 ps
CPU time 0.79 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:55:15 PM PST 23
Peak memory 208460 kb
Host smart-02a7b928-bf96-470f-873c-f637772b0fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239777581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tx_async_fifo_reset.4239777581
Directory /workspace/12.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/12.spi_device_txrx.18700784
Short name T1135
Test name
Test status
Simulation time 218686407575 ps
CPU time 410.95 seconds
Started Dec 24 01:54:53 PM PST 23
Finished Dec 24 02:01:45 PM PST 23
Peak memory 286140 kb
Host smart-09be8766-9fea-4380-acf0-8ec7bc8ecd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18700784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_txrx.18700784
Directory /workspace/12.spi_device_txrx/latest

Test location /workspace/coverage/default/12.spi_device_upload.1960554825
Short name T1458
Test name
Test status
Simulation time 691610984 ps
CPU time 10.85 seconds
Started Dec 24 01:55:34 PM PST 23
Finished Dec 24 01:55:46 PM PST 23
Peak memory 228572 kb
Host smart-e3769619-3732-4db2-aba2-f82471ba5116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960554825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1960554825
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_abort.1828242956
Short name T1457
Test name
Test status
Simulation time 121889407 ps
CPU time 0.76 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:54:59 PM PST 23
Peak memory 206632 kb
Host smart-8dfe29c5-600b-4ec7-9628-21233a85f84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828242956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_abort.1828242956
Directory /workspace/13.spi_device_abort/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4266859997
Short name T1320
Test name
Test status
Simulation time 39534906 ps
CPU time 0.72 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:55:00 PM PST 23
Peak memory 206516 kb
Host smart-6761e6a2-ef1e-41c7-b820-739a05c2ca3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266859997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4266859997
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_bit_transfer.3307486224
Short name T628
Test name
Test status
Simulation time 278366407 ps
CPU time 2.53 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:55:01 PM PST 23
Peak memory 216952 kb
Host smart-252d5756-04cf-4dc3-ada7-5238a8852f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307486224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_bit_transfer.3307486224
Directory /workspace/13.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/13.spi_device_byte_transfer.430796405
Short name T1118
Test name
Test status
Simulation time 62552405 ps
CPU time 2.47 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:16 PM PST 23
Peak memory 216816 kb
Host smart-98264b7a-b7eb-4f73-b140-f3b1363c8485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430796405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_byte_transfer.430796405
Directory /workspace/13.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2009336007
Short name T18
Test name
Test status
Simulation time 622185511 ps
CPU time 3.06 seconds
Started Dec 24 01:55:11 PM PST 23
Finished Dec 24 01:55:15 PM PST 23
Peak memory 218176 kb
Host smart-6c8939b2-e9a4-497b-95b9-c4f70f2dbc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009336007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2009336007
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1793628612
Short name T777
Test name
Test status
Simulation time 19197018 ps
CPU time 0.8 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:24 PM PST 23
Peak memory 206112 kb
Host smart-390fe834-ca73-4990-8662-8c5411d8d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793628612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1793628612
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_dummy_item_extra_dly.664657259
Short name T655
Test name
Test status
Simulation time 111477337680 ps
CPU time 385.61 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 02:02:40 PM PST 23
Peak memory 271672 kb
Host smart-9b9a9bdf-6a98-480e-b7db-4d239e00b413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664657259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_dummy_item_extra_dly.664657259
Directory /workspace/13.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/13.spi_device_extreme_fifo_size.3681277902
Short name T982
Test name
Test status
Simulation time 59553831558 ps
CPU time 863.16 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 02:10:44 PM PST 23
Peak memory 218236 kb
Host smart-e55d80b2-926b-4286-b1d2-ee2192ad4e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681277902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_extreme_fifo_size.3681277902
Directory /workspace/13.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/13.spi_device_fifo_full.3579860524
Short name T1163
Test name
Test status
Simulation time 35137919146 ps
CPU time 978.13 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 02:12:28 PM PST 23
Peak memory 302248 kb
Host smart-f946511e-59a1-4577-b49d-b4f1741ca2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579860524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_full.3579860524
Directory /workspace/13.spi_device_fifo_full/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2974346885
Short name T1542
Test name
Test status
Simulation time 599300504997 ps
CPU time 231.33 seconds
Started Dec 24 01:54:55 PM PST 23
Finished Dec 24 01:58:48 PM PST 23
Peak memory 264184 kb
Host smart-c5d16d8b-285b-4db3-b58c-86a7c39e708a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974346885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2974346885
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.988924878
Short name T1581
Test name
Test status
Simulation time 49929690000 ps
CPU time 346.71 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 02:01:06 PM PST 23
Peak memory 258032 kb
Host smart-f9573ea5-23ab-4984-abcb-accb81bca1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988924878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.988924878
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1418771850
Short name T949
Test name
Test status
Simulation time 4390190217 ps
CPU time 23.44 seconds
Started Dec 24 01:54:58 PM PST 23
Finished Dec 24 01:55:24 PM PST 23
Peak memory 248064 kb
Host smart-d571ec9f-f6e7-42b5-af95-076e65e41f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418771850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1418771850
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2166615995
Short name T1196
Test name
Test status
Simulation time 1220849878 ps
CPU time 4.21 seconds
Started Dec 24 01:54:59 PM PST 23
Finished Dec 24 01:55:06 PM PST 23
Peak memory 234288 kb
Host smart-de33a653-a360-4caa-abf4-d98861df6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166615995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2166615995
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intr.2305042208
Short name T824
Test name
Test status
Simulation time 5889612745 ps
CPU time 17.37 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:56:39 PM PST 23
Peak memory 225068 kb
Host smart-4474aba5-a035-44c5-bb14-eb5d86741f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305042208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intr.2305042208
Directory /workspace/13.spi_device_intr/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2735933746
Short name T1090
Test name
Test status
Simulation time 2340763772 ps
CPU time 17.3 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:55:16 PM PST 23
Peak memory 237468 kb
Host smart-87ee9719-ce8f-4de3-9d61-af146526eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735933746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2735933746
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.336525439
Short name T1607
Test name
Test status
Simulation time 14667685 ps
CPU time 1.04 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 218920 kb
Host smart-921afa15-fcfc-44d6-8c76-b0e35e113e5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336525439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.336525439
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1471318937
Short name T1696
Test name
Test status
Simulation time 2125128286 ps
CPU time 11.16 seconds
Started Dec 24 01:55:01 PM PST 23
Finished Dec 24 01:55:14 PM PST 23
Peak memory 233332 kb
Host smart-78461da9-ea67-4829-bcea-1f3bd4fcb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471318937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1471318937
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2498192385
Short name T1183
Test name
Test status
Simulation time 1373931109 ps
CPU time 11.03 seconds
Started Dec 24 01:54:55 PM PST 23
Finished Dec 24 01:55:08 PM PST 23
Peak memory 257124 kb
Host smart-5b21aba9-5c0f-45e0-a7b3-223a1e630346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498192385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2498192385
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_perf.2323780485
Short name T1442
Test name
Test status
Simulation time 36960197094 ps
CPU time 2193.62 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 02:32:48 PM PST 23
Peak memory 233316 kb
Host smart-7ce93a0d-9ace-433a-a06e-6080f9bd9e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323780485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_perf.2323780485
Directory /workspace/13.spi_device_perf/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2287178201
Short name T1552
Test name
Test status
Simulation time 16402182 ps
CPU time 0.71 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:56:23 PM PST 23
Peak memory 216584 kb
Host smart-7e2b290b-f838-4c39-9fc8-b6b88c09cb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287178201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2287178201
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3050530779
Short name T1513
Test name
Test status
Simulation time 2651244877 ps
CPU time 5.04 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 234396 kb
Host smart-9226a038-c549-4ea5-a5c0-f0ed4895d9fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050530779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3050530779
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_rx_async_fifo_reset.205485969
Short name T872
Test name
Test status
Simulation time 188871044 ps
CPU time 0.87 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:01 PM PST 23
Peak memory 208492 kb
Host smart-6dae5ddb-d203-4592-9a97-9a1bbdda2572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205485969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_async_fifo_reset.205485969
Directory /workspace/13.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/13.spi_device_rx_timeout.128976378
Short name T1518
Test name
Test status
Simulation time 9074496881 ps
CPU time 6.91 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:56:09 PM PST 23
Peak memory 216860 kb
Host smart-809db467-a49e-40b0-baaa-8e6a8150ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128976378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_timeout.128976378
Directory /workspace/13.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/13.spi_device_smoke.1945230968
Short name T1285
Test name
Test status
Simulation time 26546888 ps
CPU time 1.01 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 01:56:00 PM PST 23
Peak memory 208312 kb
Host smart-510558f8-de21-441d-9a26-ffdf2ae3205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945230968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_smoke.1945230968
Directory /workspace/13.spi_device_smoke/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.252320626
Short name T663
Test name
Test status
Simulation time 208759702356 ps
CPU time 1502.26 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 02:20:01 PM PST 23
Peak memory 446736 kb
Host smart-88818648-097a-4507-8015-e16ab256eb52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252320626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.252320626
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.51124515
Short name T757
Test name
Test status
Simulation time 7576974363 ps
CPU time 41.8 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:57:06 PM PST 23
Peak memory 216952 kb
Host smart-e2f422f5-1280-4c48-b1fd-705cf2ccfab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51124515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.51124515
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2646860143
Short name T1668
Test name
Test status
Simulation time 38608077446 ps
CPU time 27.06 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:50 PM PST 23
Peak memory 216924 kb
Host smart-5f4f2cb3-19c6-45a6-b399-3c26d1ca7dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646860143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2646860143
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2711033925
Short name T585
Test name
Test status
Simulation time 118165114 ps
CPU time 3.74 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:03 PM PST 23
Peak memory 216792 kb
Host smart-bb5e0d8a-769c-46bd-b919-0415a511b45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711033925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2711033925
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3931477636
Short name T873
Test name
Test status
Simulation time 210535586 ps
CPU time 0.75 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:16 PM PST 23
Peak memory 206888 kb
Host smart-8fda451c-56ae-4580-993a-1c38bd242d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931477636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3931477636
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_txrx.3146955407
Short name T484
Test name
Test status
Simulation time 57528540119 ps
CPU time 134.46 seconds
Started Dec 24 01:56:00 PM PST 23
Finished Dec 24 01:58:16 PM PST 23
Peak memory 250856 kb
Host smart-02b12db3-ce78-4c7b-980c-44edb5d272a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146955407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_txrx.3146955407
Directory /workspace/13.spi_device_txrx/latest

Test location /workspace/coverage/default/13.spi_device_upload.1426129937
Short name T706
Test name
Test status
Simulation time 34290536560 ps
CPU time 30.73 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:55:30 PM PST 23
Peak memory 249692 kb
Host smart-548ee11f-549f-492c-8fc6-74d0f66a082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426129937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1426129937
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_abort.2694841838
Short name T766
Test name
Test status
Simulation time 16174444 ps
CPU time 0.75 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:55:00 PM PST 23
Peak memory 206552 kb
Host smart-e0944b15-7ea7-40ce-8a84-d42622b2bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694841838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_abort.2694841838
Directory /workspace/14.spi_device_abort/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3173513147
Short name T857
Test name
Test status
Simulation time 15231574 ps
CPU time 0.72 seconds
Started Dec 24 01:55:19 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 206444 kb
Host smart-5a5251b8-e442-4234-a053-f037128cf20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173513147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3173513147
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_bit_transfer.1544850791
Short name T832
Test name
Test status
Simulation time 149766685 ps
CPU time 2.26 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:02 PM PST 23
Peak memory 216844 kb
Host smart-25602eef-67e5-40be-bc8b-c4371b341ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544850791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_bit_transfer.1544850791
Directory /workspace/14.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/14.spi_device_byte_transfer.844950840
Short name T893
Test name
Test status
Simulation time 279866128 ps
CPU time 2.79 seconds
Started Dec 24 01:54:55 PM PST 23
Finished Dec 24 01:55:00 PM PST 23
Peak memory 216832 kb
Host smart-2ae6dcf4-ff14-474b-916d-29c315344e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844950840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_byte_transfer.844950840
Directory /workspace/14.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.661812346
Short name T97
Test name
Test status
Simulation time 6068271636 ps
CPU time 3.64 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:55:17 PM PST 23
Peak memory 218228 kb
Host smart-a4c0e679-b9e8-4d8a-80ed-f7bbfd463e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661812346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.661812346
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.754775053
Short name T724
Test name
Test status
Simulation time 42999573 ps
CPU time 0.75 seconds
Started Dec 24 01:54:53 PM PST 23
Finished Dec 24 01:54:55 PM PST 23
Peak memory 206544 kb
Host smart-a23ead8a-97a9-4731-a617-a0325c7c5c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754775053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.754775053
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_dummy_item_extra_dly.1110981113
Short name T1475
Test name
Test status
Simulation time 100404842007 ps
CPU time 315.47 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 02:00:14 PM PST 23
Peak memory 269960 kb
Host smart-6853d704-26c6-4691-8a25-90af25e358df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110981113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_dummy_item_extra_dly.1110981113
Directory /workspace/14.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/14.spi_device_extreme_fifo_size.3158383460
Short name T719
Test name
Test status
Simulation time 25872855311 ps
CPU time 48.25 seconds
Started Dec 24 01:54:58 PM PST 23
Finished Dec 24 01:55:50 PM PST 23
Peak memory 233148 kb
Host smart-25edda51-4882-4f27-8000-309cb103f413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158383460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_extreme_fifo_size.3158383460
Directory /workspace/14.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/14.spi_device_fifo_full.3729308577
Short name T1787
Test name
Test status
Simulation time 85923313945 ps
CPU time 1780.77 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 02:24:39 PM PST 23
Peak memory 266088 kb
Host smart-53ee6d5e-c0a7-4090-b51c-feea2cdfe4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729308577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_full.3729308577
Directory /workspace/14.spi_device_fifo_full/latest

Test location /workspace/coverage/default/14.spi_device_fifo_underflow_overflow.479369650
Short name T627
Test name
Test status
Simulation time 62448052932 ps
CPU time 409.33 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 02:01:47 PM PST 23
Peak memory 325080 kb
Host smart-54bb380e-2055-4300-88f6-9243de5da329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479369650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_underflow_overfl
ow.479369650
Directory /workspace/14.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1828600206
Short name T338
Test name
Test status
Simulation time 69014476912 ps
CPU time 340.61 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 02:00:59 PM PST 23
Peak memory 265880 kb
Host smart-9162c3fa-e08d-4b58-9a16-60038578dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828600206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1828600206
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2130713801
Short name T221
Test name
Test status
Simulation time 50617205849 ps
CPU time 74.92 seconds
Started Dec 24 01:54:58 PM PST 23
Finished Dec 24 01:56:16 PM PST 23
Peak memory 265860 kb
Host smart-bd21dac6-b7f3-4492-8379-21f9b3f8888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130713801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2130713801
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3154830388
Short name T349
Test name
Test status
Simulation time 6601423663 ps
CPU time 32.12 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:55:30 PM PST 23
Peak memory 249012 kb
Host smart-0bece5f1-ed8a-4cd1-943c-bb9ce3941678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154830388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3154830388
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2921885915
Short name T1540
Test name
Test status
Simulation time 9740302189 ps
CPU time 10.08 seconds
Started Dec 24 01:54:55 PM PST 23
Finished Dec 24 01:55:07 PM PST 23
Peak memory 240140 kb
Host smart-b2df481e-fbc6-49a6-afc4-6bd84d16263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921885915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2921885915
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intr.1350798617
Short name T944
Test name
Test status
Simulation time 33749633742 ps
CPU time 59.33 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:56:19 PM PST 23
Peak memory 241588 kb
Host smart-c7c04ee5-6655-4cad-9501-a553bfeac764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350798617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intr.1350798617
Directory /workspace/14.spi_device_intr/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.91868841
Short name T1300
Test name
Test status
Simulation time 581980296 ps
CPU time 5.19 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:04 PM PST 23
Peak memory 233208 kb
Host smart-2b532f83-e95b-4970-8c42-21a90a43e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91868841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.91868841
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2807605655
Short name T1548
Test name
Test status
Simulation time 92182556 ps
CPU time 1.09 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:17 PM PST 23
Peak memory 218880 kb
Host smart-15f26cf3-d554-4c71-8702-5ea06b3aa0a8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807605655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2807605655
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3775602689
Short name T1608
Test name
Test status
Simulation time 3637443398 ps
CPU time 9.61 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:55:24 PM PST 23
Peak memory 249688 kb
Host smart-141cab41-de9f-452e-8abd-b75d70b78560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775602689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3775602689
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.626769140
Short name T1179
Test name
Test status
Simulation time 5264173791 ps
CPU time 17.23 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:55:16 PM PST 23
Peak memory 232368 kb
Host smart-0faee20f-4a81-4489-b585-85759af8420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626769140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.626769140
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_perf.2769249647
Short name T618
Test name
Test status
Simulation time 68569234811 ps
CPU time 1096.07 seconds
Started Dec 24 01:54:54 PM PST 23
Finished Dec 24 02:13:11 PM PST 23
Peak memory 265876 kb
Host smart-39d0e6a9-8e7d-4ec1-b8a1-ef924bab0374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769249647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_perf.2769249647
Directory /workspace/14.spi_device_perf/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2504307180
Short name T39
Test name
Test status
Simulation time 16233589 ps
CPU time 0.73 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:16 PM PST 23
Peak memory 216752 kb
Host smart-89059723-e8a9-4b19-b705-8f8e091eaf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504307180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2504307180
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3409614121
Short name T1727
Test name
Test status
Simulation time 1448936913 ps
CPU time 6.38 seconds
Started Dec 24 01:55:06 PM PST 23
Finished Dec 24 01:55:13 PM PST 23
Peak memory 220728 kb
Host smart-03cfedae-925a-4865-bef4-9eda8fc512c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3409614121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3409614121
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_rx_async_fifo_reset.2214834906
Short name T726
Test name
Test status
Simulation time 21208739 ps
CPU time 0.89 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:54:59 PM PST 23
Peak memory 208492 kb
Host smart-405d3a76-494f-4fc2-b102-646f50ea938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214834906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_async_fifo_reset.2214834906
Directory /workspace/14.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_rx_timeout.1992482153
Short name T1256
Test name
Test status
Simulation time 2284007027 ps
CPU time 4.6 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:05 PM PST 23
Peak memory 216896 kb
Host smart-e330c334-d33c-479c-adb1-c1e430317578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992482153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_timeout.1992482153
Directory /workspace/14.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/14.spi_device_smoke.1193021683
Short name T1332
Test name
Test status
Simulation time 20888873 ps
CPU time 1.08 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:19 PM PST 23
Peak memory 216532 kb
Host smart-e738f068-93c8-45ef-b91c-c8aea1d3b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193021683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_smoke.1193021683
Directory /workspace/14.spi_device_smoke/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2107162779
Short name T1708
Test name
Test status
Simulation time 114372083510 ps
CPU time 1688.71 seconds
Started Dec 24 01:54:58 PM PST 23
Finished Dec 24 02:23:10 PM PST 23
Peak memory 348836 kb
Host smart-77bc192e-7901-42fb-ab5d-82213b842525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107162779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2107162779
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3209639125
Short name T4
Test name
Test status
Simulation time 7041056597 ps
CPU time 30.46 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:55:46 PM PST 23
Peak memory 220736 kb
Host smart-679b9df1-ef94-43b1-a30c-a9dd1a6221c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209639125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3209639125
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1560958334
Short name T1419
Test name
Test status
Simulation time 16433669240 ps
CPU time 17.88 seconds
Started Dec 24 01:54:58 PM PST 23
Finished Dec 24 01:55:19 PM PST 23
Peak memory 216876 kb
Host smart-41301608-5b3f-4bb4-806b-4b25fb18fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560958334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1560958334
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.577351044
Short name T764
Test name
Test status
Simulation time 219717562 ps
CPU time 1.44 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:02 PM PST 23
Peak memory 216840 kb
Host smart-743f62ab-9cb3-4d3b-92ab-16a9efbc0a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577351044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.577351044
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.133982338
Short name T684
Test name
Test status
Simulation time 58658882 ps
CPU time 0.91 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:55:15 PM PST 23
Peak memory 206948 kb
Host smart-3bc83c54-4de1-42e9-98fa-13cf2ed29258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133982338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.133982338
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tx_async_fifo_reset.1522303537
Short name T1310
Test name
Test status
Simulation time 202664913 ps
CPU time 0.75 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:00 PM PST 23
Peak memory 208488 kb
Host smart-c58b91c6-28e5-43a6-83da-5fb8aaa018e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522303537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tx_async_fifo_reset.1522303537
Directory /workspace/14.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/14.spi_device_txrx.3246773939
Short name T640
Test name
Test status
Simulation time 13643022674 ps
CPU time 159.03 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:57:56 PM PST 23
Peak memory 282228 kb
Host smart-4cf0e21f-142d-4c61-af69-53c7473f7eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246773939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_txrx.3246773939
Directory /workspace/14.spi_device_txrx/latest

Test location /workspace/coverage/default/14.spi_device_upload.2481690531
Short name T951
Test name
Test status
Simulation time 2496020017 ps
CPU time 6.01 seconds
Started Dec 24 01:54:57 PM PST 23
Finished Dec 24 01:55:06 PM PST 23
Peak memory 231072 kb
Host smart-93df388e-c8c8-48f8-9dde-52d27ebefa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481690531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2481690531
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_abort.165698652
Short name T1453
Test name
Test status
Simulation time 15107802 ps
CPU time 0.76 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:16 PM PST 23
Peak memory 206596 kb
Host smart-b5be5eb3-9b1d-4a84-862d-c4cc399d4898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165698652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_abort.165698652
Directory /workspace/15.spi_device_abort/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1829592679
Short name T1664
Test name
Test status
Simulation time 53474514 ps
CPU time 0.76 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:55:15 PM PST 23
Peak memory 206468 kb
Host smart-b3d3ffcf-1271-4a2c-81b3-07a29d48514b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829592679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1829592679
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_bit_transfer.4280344068
Short name T1526
Test name
Test status
Simulation time 296448130 ps
CPU time 2.27 seconds
Started Dec 24 01:55:10 PM PST 23
Finished Dec 24 01:55:14 PM PST 23
Peak memory 216776 kb
Host smart-a3d19e9d-08af-4aa3-b3f9-f3ffa23eddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280344068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_bit_transfer.4280344068
Directory /workspace/15.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/15.spi_device_byte_transfer.858237351
Short name T1568
Test name
Test status
Simulation time 734676013 ps
CPU time 3.13 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 216748 kb
Host smart-48489f1a-200c-4057-b90f-8c1086e6c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858237351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_byte_transfer.858237351
Directory /workspace/15.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3693897686
Short name T863
Test name
Test status
Simulation time 1376548341 ps
CPU time 3.66 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 224968 kb
Host smart-8f4a3b08-26db-40f1-9ce8-ac883eb3865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693897686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3693897686
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.452164244
Short name T480
Test name
Test status
Simulation time 14638967 ps
CPU time 0.79 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:55:15 PM PST 23
Peak memory 207600 kb
Host smart-513cfdd6-832f-42eb-8ea9-f0d15feea339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452164244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.452164244
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_dummy_item_extra_dly.1440429023
Short name T1751
Test name
Test status
Simulation time 44692774358 ps
CPU time 445.06 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 02:03:03 PM PST 23
Peak memory 282652 kb
Host smart-490bf3ca-3fa8-4317-b416-0fd89781f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440429023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_dummy_item_extra_dly.1440429023
Directory /workspace/15.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/15.spi_device_extreme_fifo_size.1232670514
Short name T1159
Test name
Test status
Simulation time 5497772385 ps
CPU time 26.54 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 230696 kb
Host smart-61def783-4466-4b61-b0a6-3a27f1be1614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232670514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_extreme_fifo_size.1232670514
Directory /workspace/15.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/15.spi_device_fifo_full.702335191
Short name T690
Test name
Test status
Simulation time 24572331704 ps
CPU time 399.26 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 02:01:56 PM PST 23
Peak memory 282484 kb
Host smart-ddf680a7-188f-41a7-8a0f-2618166837ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702335191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_full.702335191
Directory /workspace/15.spi_device_fifo_full/latest

Test location /workspace/coverage/default/15.spi_device_fifo_underflow_overflow.1499919017
Short name T1650
Test name
Test status
Simulation time 50064961540 ps
CPU time 203.85 seconds
Started Dec 24 01:55:19 PM PST 23
Finished Dec 24 01:58:44 PM PST 23
Peak memory 389776 kb
Host smart-42d1ee99-2714-4826-8142-edaff4012da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499919017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_underflow_overf
low.1499919017
Directory /workspace/15.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2997874587
Short name T29
Test name
Test status
Simulation time 6437670366 ps
CPU time 71.58 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:56:29 PM PST 23
Peak memory 263452 kb
Host smart-51be130e-c0f1-4dc1-a443-2d6c32567009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997874587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2997874587
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.704628232
Short name T1522
Test name
Test status
Simulation time 8173187168 ps
CPU time 73.85 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:56:32 PM PST 23
Peak memory 269624 kb
Host smart-cb738b08-18e5-4aa7-bd74-d88a3ca006d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704628232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.704628232
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2182459515
Short name T1170
Test name
Test status
Simulation time 246823579630 ps
CPU time 254.84 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:59:27 PM PST 23
Peak memory 266332 kb
Host smart-782291ef-dade-4f45-bdc6-ae1ddd18d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182459515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2182459515
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2039022380
Short name T1461
Test name
Test status
Simulation time 257669200 ps
CPU time 9.45 seconds
Started Dec 24 01:55:54 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 241516 kb
Host smart-07fd2716-5fba-47b9-a092-9e522ec4636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039022380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2039022380
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4064396745
Short name T24
Test name
Test status
Simulation time 8351960546 ps
CPU time 13.28 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:29 PM PST 23
Peak memory 220024 kb
Host smart-31dc96ac-e6a7-4abd-ae1b-d4f161ac4c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064396745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4064396745
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intr.3659116775
Short name T1025
Test name
Test status
Simulation time 15988837627 ps
CPU time 19.3 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:38 PM PST 23
Peak memory 217484 kb
Host smart-bbf76498-b8ab-458b-a219-78eeeed12a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659116775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intr.3659116775
Directory /workspace/15.spi_device_intr/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1466221231
Short name T1377
Test name
Test status
Simulation time 8506429515 ps
CPU time 17.2 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:32 PM PST 23
Peak memory 228344 kb
Host smart-eae03650-26d5-435c-a441-136fdb953bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466221231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1466221231
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1623879377
Short name T1314
Test name
Test status
Simulation time 16173420 ps
CPU time 1.08 seconds
Started Dec 24 01:55:19 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 218940 kb
Host smart-36915b21-1ce1-4207-bcce-78830d311997
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623879377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1623879377
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3969494969
Short name T1735
Test name
Test status
Simulation time 5387058658 ps
CPU time 10.23 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:55:26 PM PST 23
Peak memory 241204 kb
Host smart-26d9e046-164a-4278-b6a4-201c3fb56844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969494969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3969494969
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1665341585
Short name T1272
Test name
Test status
Simulation time 10679572007 ps
CPU time 19.01 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:34 PM PST 23
Peak memory 222668 kb
Host smart-28bba896-d730-41aa-bf3f-b1fa8e27a095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665341585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1665341585
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_perf.3762622497
Short name T1228
Test name
Test status
Simulation time 55332160777 ps
CPU time 3385.89 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 02:51:45 PM PST 23
Peak memory 257988 kb
Host smart-a3daa15d-8c91-4453-9f06-ebfe5de9c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762622497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_perf.3762622497
Directory /workspace/15.spi_device_perf/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.775487259
Short name T89
Test name
Test status
Simulation time 123164125 ps
CPU time 0.78 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:55:15 PM PST 23
Peak memory 216736 kb
Host smart-45f21147-39a2-4949-af7d-cfc8d2950c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775487259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.775487259
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4176687321
Short name T171
Test name
Test status
Simulation time 377698242 ps
CPU time 3.74 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 235392 kb
Host smart-704465d9-9878-4195-81a0-1c714df671f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176687321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4176687321
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_rx_async_fifo_reset.3806931545
Short name T1226
Test name
Test status
Simulation time 16311630 ps
CPU time 0.86 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 208572 kb
Host smart-1824802a-cda5-490b-b440-93edcd9cbcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806931545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_async_fifo_reset.3806931545
Directory /workspace/15.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_rx_timeout.1138820980
Short name T747
Test name
Test status
Simulation time 2166326034 ps
CPU time 5.19 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:20 PM PST 23
Peak memory 216840 kb
Host smart-0f63856c-8537-4dea-8a3a-07848f3c856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138820980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_timeout.1138820980
Directory /workspace/15.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/15.spi_device_smoke.407673017
Short name T739
Test name
Test status
Simulation time 34900604 ps
CPU time 0.99 seconds
Started Dec 24 01:54:56 PM PST 23
Finished Dec 24 01:54:59 PM PST 23
Peak memory 207892 kb
Host smart-01d46724-e453-43bc-94cf-8207b81519a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407673017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_smoke.407673017
Directory /workspace/15.spi_device_smoke/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.985887134
Short name T1656
Test name
Test status
Simulation time 31878180752 ps
CPU time 467.34 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 02:03:03 PM PST 23
Peak memory 328364 kb
Host smart-3f5ee797-565d-4fe7-9a61-a77940e0c62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985887134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.985887134
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.392153127
Short name T140
Test name
Test status
Simulation time 18313336552 ps
CPU time 49.83 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 216816 kb
Host smart-99a4e01c-5acf-44c5-a63c-56e0d3d72fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392153127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.392153127
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3342501102
Short name T1220
Test name
Test status
Simulation time 442883026 ps
CPU time 3.59 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:55:17 PM PST 23
Peak memory 216716 kb
Host smart-0442576b-082a-44cb-a74e-fe54e1a9afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342501102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3342501102
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1235742013
Short name T616
Test name
Test status
Simulation time 397198225 ps
CPU time 10.86 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:55:24 PM PST 23
Peak memory 216788 kb
Host smart-a643da58-378b-4e36-8be6-f5987378c332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235742013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1235742013
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1447356375
Short name T776
Test name
Test status
Simulation time 52887390 ps
CPU time 0.93 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:55:16 PM PST 23
Peak memory 207920 kb
Host smart-f8ffe3a4-916b-40b2-bfc5-5d0217ef5541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447356375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1447356375
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tx_async_fifo_reset.2588926146
Short name T806
Test name
Test status
Simulation time 56255215 ps
CPU time 0.78 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:19 PM PST 23
Peak memory 208476 kb
Host smart-3c3b3fbe-a59b-4436-9cbb-f4fcf9541cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588926146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tx_async_fifo_reset.2588926146
Directory /workspace/15.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/15.spi_device_txrx.447774380
Short name T629
Test name
Test status
Simulation time 17534239557 ps
CPU time 51.56 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:56:05 PM PST 23
Peak memory 241572 kb
Host smart-bceb227d-0fe3-45b3-8619-0858b966db9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447774380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_txrx.447774380
Directory /workspace/15.spi_device_txrx/latest

Test location /workspace/coverage/default/15.spi_device_upload.1106573862
Short name T1027
Test name
Test status
Simulation time 7954049501 ps
CPU time 24.65 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:42 PM PST 23
Peak memory 246476 kb
Host smart-6a589259-cd33-48f1-b6c8-7083a6dd0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106573862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1106573862
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_abort.1224393255
Short name T840
Test name
Test status
Simulation time 16320911 ps
CPU time 0.75 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:20 PM PST 23
Peak memory 206640 kb
Host smart-f50f1bc9-626c-417c-b887-dba856d273e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224393255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_abort.1224393255
Directory /workspace/16.spi_device_abort/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1600598572
Short name T1254
Test name
Test status
Simulation time 43330108 ps
CPU time 0.74 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:18 PM PST 23
Peak memory 206356 kb
Host smart-8a2d8d88-bd8d-4ce4-87c0-26d34ff46b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600598572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1600598572
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_bit_transfer.805598545
Short name T1367
Test name
Test status
Simulation time 862705422 ps
CPU time 2.31 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 01:55:41 PM PST 23
Peak memory 216804 kb
Host smart-4dd1cc9d-3395-4c13-8298-0f266672ac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805598545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_bit_transfer.805598545
Directory /workspace/16.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/16.spi_device_byte_transfer.4180552854
Short name T784
Test name
Test status
Simulation time 208202266 ps
CPU time 3.04 seconds
Started Dec 24 01:55:10 PM PST 23
Finished Dec 24 01:55:14 PM PST 23
Peak memory 216824 kb
Host smart-25dbd8da-3ad5-4954-8823-03071c4954c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180552854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_byte_transfer.4180552854
Directory /workspace/16.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2648256148
Short name T841
Test name
Test status
Simulation time 5854501707 ps
CPU time 6.31 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 221756 kb
Host smart-90f38dc5-ddba-492a-8384-2106f8383762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648256148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2648256148
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1381967065
Short name T487
Test name
Test status
Simulation time 42741147 ps
CPU time 0.76 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:55:14 PM PST 23
Peak memory 206584 kb
Host smart-8e6fe89b-8eec-4f40-96dc-b70cf20074e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381967065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1381967065
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_dummy_item_extra_dly.802862141
Short name T542
Test name
Test status
Simulation time 139490442435 ps
CPU time 236.62 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:59:11 PM PST 23
Peak memory 282560 kb
Host smart-b7111ec6-2a55-41c2-8707-95d6375a8345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802862141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_dummy_item_extra_dly.802862141
Directory /workspace/16.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/16.spi_device_extreme_fifo_size.1168167833
Short name T1631
Test name
Test status
Simulation time 183578203142 ps
CPU time 1623.63 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 02:22:22 PM PST 23
Peak memory 225132 kb
Host smart-430b123d-e83f-44f3-8787-c5acc62f3b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168167833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_extreme_fifo_size.1168167833
Directory /workspace/16.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/16.spi_device_fifo_full.1239947709
Short name T677
Test name
Test status
Simulation time 10023085770 ps
CPU time 552.35 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 02:04:26 PM PST 23
Peak memory 273748 kb
Host smart-616b1565-4800-4eec-918c-4a3cbe2eb49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239947709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_full.1239947709
Directory /workspace/16.spi_device_fifo_full/latest

Test location /workspace/coverage/default/16.spi_device_fifo_underflow_overflow.1322123695
Short name T1531
Test name
Test status
Simulation time 346116325151 ps
CPU time 389.19 seconds
Started Dec 24 01:55:32 PM PST 23
Finished Dec 24 02:02:02 PM PST 23
Peak memory 327248 kb
Host smart-57726107-da2a-40c9-bd66-42c63e04485f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322123695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_underflow_overf
low.1322123695
Directory /workspace/16.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2316711445
Short name T242
Test name
Test status
Simulation time 17730251520 ps
CPU time 141.4 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 01:58:21 PM PST 23
Peak memory 267624 kb
Host smart-56a44a10-555b-4461-9d2c-69e950d4abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316711445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2316711445
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2363091885
Short name T347
Test name
Test status
Simulation time 194152669795 ps
CPU time 353.69 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 02:01:55 PM PST 23
Peak memory 255216 kb
Host smart-ae96cc00-6a6f-4970-82ac-6241c4ccac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363091885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2363091885
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3433595209
Short name T352
Test name
Test status
Simulation time 13416633583 ps
CPU time 12.14 seconds
Started Dec 24 01:55:42 PM PST 23
Finished Dec 24 01:55:55 PM PST 23
Peak memory 254584 kb
Host smart-cd13fbe5-91e3-4f8e-9f5a-010a5ea40be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433595209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3433595209
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3993616820
Short name T1770
Test name
Test status
Simulation time 603745226 ps
CPU time 5.78 seconds
Started Dec 24 01:55:41 PM PST 23
Finished Dec 24 01:55:48 PM PST 23
Peak memory 219612 kb
Host smart-223944ff-f940-4ca6-a500-7f60a5deb348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993616820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3993616820
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intr.81237835
Short name T957
Test name
Test status
Simulation time 28954169730 ps
CPU time 18.06 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:35 PM PST 23
Peak memory 218368 kb
Host smart-243d2039-4893-49c5-ad42-cb985024821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81237835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intr.81237835
Directory /workspace/16.spi_device_intr/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.371274147
Short name T1357
Test name
Test status
Simulation time 129831244 ps
CPU time 3.81 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:55:53 PM PST 23
Peak memory 234696 kb
Host smart-1fe12cbd-04b1-4d01-a601-2517c678dd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371274147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.371274147
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1480900397
Short name T770
Test name
Test status
Simulation time 144928032 ps
CPU time 1.09 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:18 PM PST 23
Peak memory 218896 kb
Host smart-a7d59346-cfbc-4e60-afd9-bdfd4d27b5a5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480900397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1480900397
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3168155928
Short name T1072
Test name
Test status
Simulation time 16748729542 ps
CPU time 16.42 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:56:06 PM PST 23
Peak memory 244756 kb
Host smart-7654ed57-26fc-405b-b9b7-6e80863c6645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168155928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3168155928
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.920237996
Short name T276
Test name
Test status
Simulation time 4723317742 ps
CPU time 19.39 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:57 PM PST 23
Peak memory 239240 kb
Host smart-235f8600-64f3-465b-952b-effedb31202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920237996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.920237996
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_perf.1770805630
Short name T866
Test name
Test status
Simulation time 27505740647 ps
CPU time 176.18 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:58:11 PM PST 23
Peak memory 286180 kb
Host smart-df797efe-f41c-4510-8ae3-c24bf0bfc515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770805630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_perf.1770805630
Directory /workspace/16.spi_device_perf/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2814777673
Short name T817
Test name
Test status
Simulation time 34976130 ps
CPU time 0.75 seconds
Started Dec 24 01:55:35 PM PST 23
Finished Dec 24 01:55:37 PM PST 23
Peak memory 216704 kb
Host smart-47aeb3d5-21a0-426d-99e2-f705e657796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814777673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2814777673
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3149475231
Short name T1056
Test name
Test status
Simulation time 5989331864 ps
CPU time 4.82 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:56:13 PM PST 23
Peak memory 220324 kb
Host smart-57a7ae1a-1617-4d2c-88c0-fafdbd1789f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3149475231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3149475231
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_rx_async_fifo_reset.2027000347
Short name T76
Test name
Test status
Simulation time 175388823 ps
CPU time 0.83 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:37 PM PST 23
Peak memory 208496 kb
Host smart-028b7cbb-2000-4d00-9c2c-6c2445361b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027000347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_async_fifo_reset.2027000347
Directory /workspace/16.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_rx_timeout.699738207
Short name T1496
Test name
Test status
Simulation time 2911267805 ps
CPU time 5.45 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:24 PM PST 23
Peak memory 216812 kb
Host smart-ad53a2da-c85e-4c5f-99e8-cf1a14e08dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699738207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_timeout.699738207
Directory /workspace/16.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/16.spi_device_smoke.4173658495
Short name T797
Test name
Test status
Simulation time 234242202 ps
CPU time 1.29 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:38 PM PST 23
Peak memory 216820 kb
Host smart-817512ad-1f92-4110-9c86-35b15b074776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173658495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_smoke.4173658495
Directory /workspace/16.spi_device_smoke/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2868463826
Short name T970
Test name
Test status
Simulation time 960180760 ps
CPU time 15.18 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:31 PM PST 23
Peak memory 220272 kb
Host smart-55bc648b-c8fe-422b-b69d-56a8be079e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868463826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2868463826
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2825198065
Short name T1534
Test name
Test status
Simulation time 5460307379 ps
CPU time 5 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:42 PM PST 23
Peak memory 217764 kb
Host smart-692147cb-2df0-4268-b0cc-dba9a67f4d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825198065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2825198065
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.773388699
Short name T920
Test name
Test status
Simulation time 105334807 ps
CPU time 2.86 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:23 PM PST 23
Peak memory 216776 kb
Host smart-c5593f51-5ec3-4c8d-9656-99f037675084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773388699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.773388699
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3819102613
Short name T1144
Test name
Test status
Simulation time 14957854 ps
CPU time 0.75 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:19 PM PST 23
Peak memory 206904 kb
Host smart-b26d4f68-1ac8-464e-ae83-85bb84c29cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819102613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3819102613
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tx_async_fifo_reset.1641759549
Short name T733
Test name
Test status
Simulation time 155194877 ps
CPU time 0.77 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:20 PM PST 23
Peak memory 208460 kb
Host smart-3926595f-ee9d-42e6-8c20-96d5b779831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641759549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tx_async_fifo_reset.1641759549
Directory /workspace/16.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/16.spi_device_txrx.65761086
Short name T693
Test name
Test status
Simulation time 26576497911 ps
CPU time 170.59 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:58:10 PM PST 23
Peak memory 257252 kb
Host smart-56bf6827-d3fb-42cb-aa22-4a80abd4cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65761086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_txrx.65761086
Directory /workspace/16.spi_device_txrx/latest

Test location /workspace/coverage/default/16.spi_device_upload.2239843953
Short name T1275
Test name
Test status
Simulation time 1900606864 ps
CPU time 7.6 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:23 PM PST 23
Peak memory 235668 kb
Host smart-ad3ed370-02ff-44a1-be33-21dadf5f7073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239843953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2239843953
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_abort.258267936
Short name T1042
Test name
Test status
Simulation time 43459611 ps
CPU time 0.74 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:19 PM PST 23
Peak memory 206672 kb
Host smart-4a482bc4-91c2-45aa-9157-879a373b6acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258267936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_abort.258267936
Directory /workspace/17.spi_device_abort/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4019100589
Short name T79
Test name
Test status
Simulation time 29212036 ps
CPU time 0.69 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 206464 kb
Host smart-59f60d37-29e9-488f-a823-52a2628d5dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019100589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4019100589
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_bit_transfer.3599804525
Short name T1160
Test name
Test status
Simulation time 145532825 ps
CPU time 1.98 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 216904 kb
Host smart-7f7f4341-bfb8-4667-b978-17497d3a7a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599804525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_bit_transfer.3599804525
Directory /workspace/17.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/17.spi_device_byte_transfer.1322233948
Short name T36
Test name
Test status
Simulation time 302820199 ps
CPU time 3.28 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 216860 kb
Host smart-c40df452-fc50-4f43-98b5-5b99b80dd17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322233948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_byte_transfer.1322233948
Directory /workspace/17.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3275879060
Short name T1721
Test name
Test status
Simulation time 77873020 ps
CPU time 2.76 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:10 PM PST 23
Peak memory 218828 kb
Host smart-392403b7-4370-4e88-9aa4-5904cbbb6ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275879060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3275879060
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3288424022
Short name T1459
Test name
Test status
Simulation time 19659193 ps
CPU time 0.78 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 01:55:15 PM PST 23
Peak memory 207440 kb
Host smart-69509e53-b6f7-4201-b5a0-30f695729b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288424022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3288424022
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_dummy_item_extra_dly.2576863403
Short name T207
Test name
Test status
Simulation time 871282227697 ps
CPU time 834.66 seconds
Started Dec 24 01:55:34 PM PST 23
Finished Dec 24 02:09:30 PM PST 23
Peak memory 257660 kb
Host smart-0bb6b98b-371e-4535-92d4-5661c45a26a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576863403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_dummy_item_extra_dly.2576863403
Directory /workspace/17.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/17.spi_device_extreme_fifo_size.3417873065
Short name T912
Test name
Test status
Simulation time 153020009966 ps
CPU time 75.66 seconds
Started Dec 24 01:55:12 PM PST 23
Finished Dec 24 01:56:29 PM PST 23
Peak memory 231304 kb
Host smart-0af62b37-4e29-4f26-ba0d-642df9073394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417873065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_extreme_fifo_size.3417873065
Directory /workspace/17.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/17.spi_device_fifo_full.3909241009
Short name T1051
Test name
Test status
Simulation time 157099072946 ps
CPU time 873.47 seconds
Started Dec 24 01:55:13 PM PST 23
Finished Dec 24 02:09:48 PM PST 23
Peak memory 262712 kb
Host smart-c75da2fa-0788-4386-905b-1e506ee7ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909241009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_full.3909241009
Directory /workspace/17.spi_device_fifo_full/latest

Test location /workspace/coverage/default/17.spi_device_fifo_underflow_overflow.2778509880
Short name T1050
Test name
Test status
Simulation time 18126821052 ps
CPU time 162.25 seconds
Started Dec 24 01:55:11 PM PST 23
Finished Dec 24 01:57:54 PM PST 23
Peak memory 319404 kb
Host smart-4fb52911-019a-4003-8339-34c3dcbf7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778509880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_underflow_overf
low.2778509880
Directory /workspace/17.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2746354065
Short name T328
Test name
Test status
Simulation time 262668114637 ps
CPU time 305.77 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 02:01:04 PM PST 23
Peak memory 256672 kb
Host smart-0d58e9b4-e539-4005-b1ba-d1ae1523e28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746354065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2746354065
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1804654030
Short name T1530
Test name
Test status
Simulation time 19954417898 ps
CPU time 31.07 seconds
Started Dec 24 01:55:53 PM PST 23
Finished Dec 24 01:56:25 PM PST 23
Peak memory 234660 kb
Host smart-7422fa4e-b108-43aa-a31f-8220d6e3c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804654030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1804654030
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2925757045
Short name T104
Test name
Test status
Simulation time 247600366917 ps
CPU time 393.83 seconds
Started Dec 24 01:56:00 PM PST 23
Finished Dec 24 02:02:35 PM PST 23
Peak memory 257384 kb
Host smart-888dba6c-05e8-42d5-8104-20e3a8077a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925757045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2925757045
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.220124580
Short name T229
Test name
Test status
Simulation time 481941151 ps
CPU time 5.93 seconds
Started Dec 24 01:55:50 PM PST 23
Finished Dec 24 01:55:57 PM PST 23
Peak memory 239344 kb
Host smart-c7125d7a-f9e2-4d68-ad84-cbf05c5d269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220124580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.220124580
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intr.1119759341
Short name T132
Test name
Test status
Simulation time 22802512996 ps
CPU time 23.11 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 218384 kb
Host smart-8d9bcf16-d574-4bb8-9843-d40aa06d2fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119759341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intr.1119759341
Directory /workspace/17.spi_device_intr/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1963447340
Short name T227
Test name
Test status
Simulation time 8588971701 ps
CPU time 15.2 seconds
Started Dec 24 01:55:19 PM PST 23
Finished Dec 24 01:55:36 PM PST 23
Peak memory 252016 kb
Host smart-7aa8d7d3-94c2-4c1c-8fc3-5d496065aa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963447340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1963447340
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4285188164
Short name T1079
Test name
Test status
Simulation time 24705870 ps
CPU time 1.09 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:19 PM PST 23
Peak memory 218688 kb
Host smart-1d757432-d185-4e52-97e3-d3b8e0d54d03
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285188164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4285188164
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3695043655
Short name T1529
Test name
Test status
Simulation time 651377986 ps
CPU time 8.1 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 01:55:47 PM PST 23
Peak memory 241368 kb
Host smart-17dda44d-c935-4fe3-8c6b-8348f24a936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695043655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3695043655
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1261483112
Short name T875
Test name
Test status
Simulation time 478141177 ps
CPU time 3.73 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 01:56:03 PM PST 23
Peak memory 238376 kb
Host smart-52492f4a-c06c-4feb-afc5-0e76e817efca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261483112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1261483112
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_perf.1278032867
Short name T579
Test name
Test status
Simulation time 35264800214 ps
CPU time 704.29 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 304416 kb
Host smart-72e7aac8-9dc4-4e09-8f60-a9a8a17425ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278032867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_perf.1278032867
Directory /workspace/17.spi_device_perf/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3900050010
Short name T1745
Test name
Test status
Simulation time 42380134 ps
CPU time 0.74 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 216688 kb
Host smart-13c098fd-58b2-41fa-a7b1-262be4f78b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900050010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3900050010
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2474340560
Short name T44
Test name
Test status
Simulation time 1165433423 ps
CPU time 4.31 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:56:02 PM PST 23
Peak memory 218768 kb
Host smart-59b9049b-da0c-4937-97a6-a0e5c58755bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2474340560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2474340560
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_rx_async_fifo_reset.1365903177
Short name T737
Test name
Test status
Simulation time 21207659 ps
CPU time 0.87 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 208488 kb
Host smart-6b97d755-d1bb-4996-8786-8247b4121bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365903177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_async_fifo_reset.1365903177
Directory /workspace/17.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_rx_timeout.3515031336
Short name T1093
Test name
Test status
Simulation time 724860268 ps
CPU time 5.52 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 216524 kb
Host smart-957be246-4d60-4c7a-b087-71fdeb01b9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515031336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_timeout.3515031336
Directory /workspace/17.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/17.spi_device_smoke.1417461053
Short name T868
Test name
Test status
Simulation time 86378468 ps
CPU time 1.05 seconds
Started Dec 24 01:55:19 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 208064 kb
Host smart-da948fce-f013-4d3e-bfb9-4957f84d08c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417461053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_smoke.1417461053
Directory /workspace/17.spi_device_smoke/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1251943550
Short name T130
Test name
Test status
Simulation time 116399150131 ps
CPU time 254.53 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 02:00:28 PM PST 23
Peak memory 307128 kb
Host smart-c11ac365-f625-4ebe-9407-0b5af110f609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251943550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1251943550
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1985274057
Short name T741
Test name
Test status
Simulation time 25955884712 ps
CPU time 94.72 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:56:50 PM PST 23
Peak memory 216864 kb
Host smart-e7343a39-1c9a-4e14-afe1-9760c29e3e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985274057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1985274057
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1323255096
Short name T758
Test name
Test status
Simulation time 18906677106 ps
CPU time 13 seconds
Started Dec 24 01:55:40 PM PST 23
Finished Dec 24 01:55:55 PM PST 23
Peak memory 216916 kb
Host smart-1de0157a-0627-43f6-af99-ddeb627e8f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323255096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1323255096
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.755803385
Short name T1109
Test name
Test status
Simulation time 766814350 ps
CPU time 2.56 seconds
Started Dec 24 01:56:00 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 216864 kb
Host smart-579ade14-2427-4a78-9e66-0057b3443e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755803385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.755803385
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3642059568
Short name T1578
Test name
Test status
Simulation time 168867908 ps
CPU time 1.17 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:38 PM PST 23
Peak memory 207964 kb
Host smart-24c825b8-e5ed-498d-aaf2-7aa87ce8a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642059568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3642059568
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tx_async_fifo_reset.3288599108
Short name T1492
Test name
Test status
Simulation time 77543480 ps
CPU time 0.76 seconds
Started Dec 24 01:55:35 PM PST 23
Finished Dec 24 01:55:37 PM PST 23
Peak memory 208448 kb
Host smart-6f40db2c-2e09-416a-8ebf-5f0619eab151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288599108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tx_async_fifo_reset.3288599108
Directory /workspace/17.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/17.spi_device_txrx.3137066213
Short name T1152
Test name
Test status
Simulation time 119736645142 ps
CPU time 313.59 seconds
Started Dec 24 01:55:39 PM PST 23
Finished Dec 24 02:00:55 PM PST 23
Peak memory 281344 kb
Host smart-9678c09e-d832-4be8-be7c-3a76ec5f40e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137066213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_txrx.3137066213
Directory /workspace/17.spi_device_txrx/latest

Test location /workspace/coverage/default/17.spi_device_upload.3388667777
Short name T736
Test name
Test status
Simulation time 8379208748 ps
CPU time 29.25 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:56:37 PM PST 23
Peak memory 249688 kb
Host smart-867f2ef6-d3ba-4dbe-9b43-4f90fd0770e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388667777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3388667777
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_abort.309091395
Short name T808
Test name
Test status
Simulation time 41099503 ps
CPU time 0.74 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 206740 kb
Host smart-18eea6c8-b470-4582-adf8-52381248a171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309091395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_abort.309091395
Directory /workspace/18.spi_device_abort/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2614861405
Short name T1039
Test name
Test status
Simulation time 39372816 ps
CPU time 0.8 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:37 PM PST 23
Peak memory 206392 kb
Host smart-eeddb376-9c8a-4ccf-8e6b-32dd6b79c07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614861405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2614861405
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_bit_transfer.1917954023
Short name T539
Test name
Test status
Simulation time 1394945437 ps
CPU time 2.42 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:56:32 PM PST 23
Peak memory 216788 kb
Host smart-943c864a-2f4e-40c7-8034-1cdb66443a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917954023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_bit_transfer.1917954023
Directory /workspace/18.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/18.spi_device_byte_transfer.2970463111
Short name T1319
Test name
Test status
Simulation time 178601811 ps
CPU time 3.24 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:56:25 PM PST 23
Peak memory 216868 kb
Host smart-481e833b-51d1-4c51-99b2-df99730f4f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970463111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_byte_transfer.2970463111
Directory /workspace/18.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.819362159
Short name T913
Test name
Test status
Simulation time 476077041 ps
CPU time 3.73 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 238292 kb
Host smart-601c69d2-c190-4495-b580-a74b7520ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819362159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.819362159
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1466961065
Short name T701
Test name
Test status
Simulation time 49001286 ps
CPU time 0.8 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:25 PM PST 23
Peak memory 207516 kb
Host smart-e41cf674-d7a0-469f-bd26-ed7671d34df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466961065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1466961065
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_dummy_item_extra_dly.1610758576
Short name T1748
Test name
Test status
Simulation time 53282617560 ps
CPU time 107.03 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:58:01 PM PST 23
Peak memory 241312 kb
Host smart-159ce1f7-5cdc-452e-a004-d7b65b298369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610758576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_dummy_item_extra_dly.1610758576
Directory /workspace/18.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/18.spi_device_extreme_fifo_size.1725736886
Short name T1363
Test name
Test status
Simulation time 60108795853 ps
CPU time 1039.36 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 02:13:42 PM PST 23
Peak memory 220084 kb
Host smart-a3ea6dcd-75d7-44d5-9802-51c529af557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725736886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_extreme_fifo_size.1725736886
Directory /workspace/18.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/18.spi_device_fifo_full.3529591882
Short name T1715
Test name
Test status
Simulation time 93293211800 ps
CPU time 2512.44 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:38:04 PM PST 23
Peak memory 249552 kb
Host smart-529788a3-bc09-42b0-bef0-7a1a7a0c7041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529591882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_full.3529591882
Directory /workspace/18.spi_device_fifo_full/latest

Test location /workspace/coverage/default/18.spi_device_fifo_underflow_overflow.2563197942
Short name T1508
Test name
Test status
Simulation time 55060248575 ps
CPU time 301.96 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 02:01:02 PM PST 23
Peak memory 419992 kb
Host smart-04c92ef4-7c8e-44e7-acb4-a82aaee22f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563197942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_underflow_overf
low.2563197942
Directory /workspace/18.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2487393899
Short name T1034
Test name
Test status
Simulation time 168057254798 ps
CPU time 222.72 seconds
Started Dec 24 01:55:19 PM PST 23
Finished Dec 24 01:59:03 PM PST 23
Peak memory 257836 kb
Host smart-f09e533e-4937-41e5-8196-e44293e425c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487393899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2487393899
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3297613745
Short name T994
Test name
Test status
Simulation time 53300957198 ps
CPU time 214.73 seconds
Started Dec 24 01:55:16 PM PST 23
Finished Dec 24 01:58:53 PM PST 23
Peak memory 249784 kb
Host smart-27d5dd84-8839-43cd-8ef4-17820ddbefa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297613745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3297613745
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4238339472
Short name T818
Test name
Test status
Simulation time 14303475625 ps
CPU time 112.98 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:57:33 PM PST 23
Peak memory 238772 kb
Host smart-01cf9e0e-bc28-4695-9f2e-65c214cb2c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238339472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4238339472
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.517349323
Short name T952
Test name
Test status
Simulation time 3794051963 ps
CPU time 19.88 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 231816 kb
Host smart-9c9f0961-3887-4bc4-a5d6-a0db951639ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517349323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.517349323
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2326992246
Short name T1789
Test name
Test status
Simulation time 2649326215 ps
CPU time 6.32 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:55:23 PM PST 23
Peak memory 219004 kb
Host smart-84966f51-d490-4e08-b8e4-556e19166751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326992246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2326992246
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intr.2402221206
Short name T937
Test name
Test status
Simulation time 9909039469 ps
CPU time 29.09 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:41 PM PST 23
Peak memory 224784 kb
Host smart-87350dfe-4345-44b4-996a-4f4710a72e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402221206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intr.2402221206
Directory /workspace/18.spi_device_intr/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.155288662
Short name T1158
Test name
Test status
Simulation time 7308259677 ps
CPU time 10.68 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:30 PM PST 23
Peak memory 219756 kb
Host smart-ad925df1-876d-45c8-b4e5-91f5d4fe0a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155288662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.155288662
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1332464263
Short name T46
Test name
Test status
Simulation time 16048665 ps
CPU time 1.01 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:08 PM PST 23
Peak memory 218864 kb
Host smart-08818adb-e14e-49b2-86b7-51077466d951
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332464263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1332464263
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2266169311
Short name T22
Test name
Test status
Simulation time 8183393486 ps
CPU time 21.33 seconds
Started Dec 24 01:55:32 PM PST 23
Finished Dec 24 01:55:54 PM PST 23
Peak memory 225168 kb
Host smart-90cc1d65-7a79-4128-85bb-b6d8bdffc8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266169311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2266169311
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3008067165
Short name T1476
Test name
Test status
Simulation time 12584908164 ps
CPU time 33.02 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:57 PM PST 23
Peak memory 233372 kb
Host smart-9cb63e10-e526-419f-bf41-0d202c6aa24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008067165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3008067165
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_perf.606366147
Short name T1366
Test name
Test status
Simulation time 7628181218 ps
CPU time 513.99 seconds
Started Dec 24 01:56:11 PM PST 23
Finished Dec 24 02:04:51 PM PST 23
Peak memory 257388 kb
Host smart-059b9480-5a18-41a9-bc5c-90c19097595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606366147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_perf.606366147
Directory /workspace/18.spi_device_perf/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.766333151
Short name T90
Test name
Test status
Simulation time 15263172 ps
CPU time 0.74 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:08 PM PST 23
Peak memory 216656 kb
Host smart-2e2c031b-2321-4ebd-a883-22f45789e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766333151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.766333151
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2649195189
Short name T1379
Test name
Test status
Simulation time 1156744259 ps
CPU time 7.04 seconds
Started Dec 24 01:55:35 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 234096 kb
Host smart-5ee22992-69a8-4d38-959c-57d139bc0126
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2649195189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2649195189
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_rx_async_fifo_reset.2545271
Short name T1503
Test name
Test status
Simulation time 37688160 ps
CPU time 0.92 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 208464 kb
Host smart-09be68af-032f-4cdf-8c4d-055f84de2154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_async_fifo_reset.2545271
Directory /workspace/18.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_rx_timeout.2117767788
Short name T113
Test name
Test status
Simulation time 2394779293 ps
CPU time 5.46 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:16 PM PST 23
Peak memory 216824 kb
Host smart-decbe8bf-7439-41b8-b095-c3d2c1726c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117767788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_timeout.2117767788
Directory /workspace/18.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/18.spi_device_smoke.1861563087
Short name T1208
Test name
Test status
Simulation time 63249821 ps
CPU time 1.11 seconds
Started Dec 24 01:56:02 PM PST 23
Finished Dec 24 01:56:06 PM PST 23
Peak memory 207964 kb
Host smart-5b16d9ce-1f1a-4b5b-befc-a90d43bdee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861563087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_smoke.1861563087
Directory /workspace/18.spi_device_smoke/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3190559159
Short name T131
Test name
Test status
Simulation time 180028774307 ps
CPU time 907.8 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 02:10:46 PM PST 23
Peak memory 341968 kb
Host smart-eeb08867-5a4c-4e3f-b5c5-80ac19cd3cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190559159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3190559159
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1004707610
Short name T515
Test name
Test status
Simulation time 2867333519 ps
CPU time 8.99 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:17 PM PST 23
Peak memory 216944 kb
Host smart-96529a45-d8f0-4dc2-a393-9ab004c9c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004707610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1004707610
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.579989171
Short name T956
Test name
Test status
Simulation time 309496756 ps
CPU time 2.24 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 216820 kb
Host smart-235c3d49-3b7d-428d-a1b3-540fc1b384c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579989171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.579989171
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.442025765
Short name T759
Test name
Test status
Simulation time 131567576 ps
CPU time 1.61 seconds
Started Dec 24 01:56:11 PM PST 23
Finished Dec 24 01:56:18 PM PST 23
Peak memory 216896 kb
Host smart-0d5c45b7-1ac9-40fb-a696-d86cd22f6a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442025765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.442025765
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3454611463
Short name T1471
Test name
Test status
Simulation time 683602509 ps
CPU time 0.99 seconds
Started Dec 24 01:56:11 PM PST 23
Finished Dec 24 01:56:18 PM PST 23
Peak memory 206964 kb
Host smart-a391cece-d684-4851-aeaa-0ab12a79b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454611463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3454611463
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tx_async_fifo_reset.1013593951
Short name T1315
Test name
Test status
Simulation time 62629123 ps
CPU time 0.81 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 208424 kb
Host smart-0cf44e91-d75d-4166-8020-731836d6085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013593951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tx_async_fifo_reset.1013593951
Directory /workspace/18.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/18.spi_device_txrx.2199140934
Short name T688
Test name
Test status
Simulation time 441365066392 ps
CPU time 431.15 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 02:03:21 PM PST 23
Peak memory 277416 kb
Host smart-30919457-f882-49ed-8f42-5aa22ac095f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199140934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_txrx.2199140934
Directory /workspace/18.spi_device_txrx/latest

Test location /workspace/coverage/default/18.spi_device_upload.1571497071
Short name T1077
Test name
Test status
Simulation time 14984223895 ps
CPU time 27.35 seconds
Started Dec 24 01:55:14 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 250720 kb
Host smart-bcdb4612-ea1c-4f06-b1e4-29a2d25a7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571497071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1571497071
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_abort.1182430350
Short name T680
Test name
Test status
Simulation time 15136875 ps
CPU time 0.73 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 01:55:39 PM PST 23
Peak memory 206648 kb
Host smart-c73edf3b-bf6d-4266-8669-a44454d99414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182430350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_abort.1182430350
Directory /workspace/19.spi_device_abort/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3880967712
Short name T600
Test name
Test status
Simulation time 22695216 ps
CPU time 0.74 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 206496 kb
Host smart-fa497d7e-3260-4caa-aaf0-bb8b89ef02b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880967712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3880967712
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_bit_transfer.2172713335
Short name T502
Test name
Test status
Simulation time 266056699 ps
CPU time 2.52 seconds
Started Dec 24 01:55:42 PM PST 23
Finished Dec 24 01:55:45 PM PST 23
Peak memory 216804 kb
Host smart-7f6cd380-b4e7-4158-be8d-4dd1c503cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172713335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_bit_transfer.2172713335
Directory /workspace/19.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/19.spi_device_byte_transfer.949904414
Short name T1648
Test name
Test status
Simulation time 469090505 ps
CPU time 2.99 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:55:53 PM PST 23
Peak memory 216776 kb
Host smart-f4ebd3ce-ba9c-4ec1-a0e5-61c3549522ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949904414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_byte_transfer.949904414
Directory /workspace/19.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3539168962
Short name T1591
Test name
Test status
Simulation time 271658059 ps
CPU time 3.36 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 241104 kb
Host smart-834ee0ae-0c81-4e64-afbd-30836e0d8ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539168962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3539168962
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2037411975
Short name T1387
Test name
Test status
Simulation time 43791965 ps
CPU time 0.74 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:08 PM PST 23
Peak memory 206540 kb
Host smart-d1a3852e-1497-4dcc-8368-6766334b4fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037411975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2037411975
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_dummy_item_extra_dly.1174901247
Short name T1129
Test name
Test status
Simulation time 389234268794 ps
CPU time 301.65 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 02:01:08 PM PST 23
Peak memory 282660 kb
Host smart-b269166a-330b-4e61-a262-d67bc88504a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174901247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_dummy_item_extra_dly.1174901247
Directory /workspace/19.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/19.spi_device_extreme_fifo_size.1332082967
Short name T1710
Test name
Test status
Simulation time 153519418958 ps
CPU time 1018.12 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 02:12:57 PM PST 23
Peak memory 225116 kb
Host smart-5185216a-2d9e-4ed6-80be-f63fd6eb50c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332082967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_extreme_fifo_size.1332082967
Directory /workspace/19.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/19.spi_device_fifo_full.730801831
Short name T858
Test name
Test status
Simulation time 72530495641 ps
CPU time 733.99 seconds
Started Dec 24 01:55:35 PM PST 23
Finished Dec 24 02:07:49 PM PST 23
Peak memory 249816 kb
Host smart-ae35ed94-7086-4260-95b0-ffd277ede9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730801831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_full.730801831
Directory /workspace/19.spi_device_fifo_full/latest

Test location /workspace/coverage/default/19.spi_device_fifo_underflow_overflow.1698872927
Short name T551
Test name
Test status
Simulation time 46208298347 ps
CPU time 201.85 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 01:59:00 PM PST 23
Peak memory 328296 kb
Host smart-beb82c87-ddf7-4b56-96f4-19b7390ccc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698872927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_underflow_overf
low.1698872927
Directory /workspace/19.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.376295363
Short name T295
Test name
Test status
Simulation time 55379094043 ps
CPU time 153.54 seconds
Started Dec 24 01:55:48 PM PST 23
Finished Dec 24 01:58:22 PM PST 23
Peak memory 249772 kb
Host smart-1bb1b979-9077-4339-a550-84c19fe96c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376295363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.376295363
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.781078377
Short name T1674
Test name
Test status
Simulation time 9110618388 ps
CPU time 88.3 seconds
Started Dec 24 01:55:40 PM PST 23
Finished Dec 24 01:57:10 PM PST 23
Peak memory 225236 kb
Host smart-4db0eddc-d06e-40f2-80ba-f702020ef540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781078377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.781078377
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3192747848
Short name T43
Test name
Test status
Simulation time 42136392072 ps
CPU time 85.37 seconds
Started Dec 24 01:55:55 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 252960 kb
Host smart-83635b84-867e-4ea8-8b9d-64165f2a8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192747848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3192747848
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4193544142
Short name T1511
Test name
Test status
Simulation time 8039898615 ps
CPU time 14.15 seconds
Started Dec 24 01:55:48 PM PST 23
Finished Dec 24 01:56:02 PM PST 23
Peak memory 223144 kb
Host smart-8268e755-2207-4faa-a407-6791a902d0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193544142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4193544142
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3664751693
Short name T1211
Test name
Test status
Simulation time 24806958913 ps
CPU time 13.08 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:51 PM PST 23
Peak memory 220428 kb
Host smart-4c278a59-bb74-4467-9bf7-9b15b9d80132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664751693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3664751693
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intr.3875207239
Short name T1236
Test name
Test status
Simulation time 46547619231 ps
CPU time 62.03 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:57:23 PM PST 23
Peak memory 236360 kb
Host smart-3ffe1058-9755-470b-beb6-e37217b300a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875207239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intr.3875207239
Directory /workspace/19.spi_device_intr/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3405743783
Short name T19
Test name
Test status
Simulation time 9140016351 ps
CPU time 33.72 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 238052 kb
Host smart-5701a5aa-d111-4557-bd23-e59e26d7104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405743783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3405743783
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3277506410
Short name T605
Test name
Test status
Simulation time 14362904 ps
CPU time 1 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:38 PM PST 23
Peak memory 218956 kb
Host smart-4ea5812e-43f4-42c2-8d8f-264a9b6a22e2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277506410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3277506410
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1920229391
Short name T1286
Test name
Test status
Simulation time 930039156 ps
CPU time 6.27 seconds
Started Dec 24 01:55:17 PM PST 23
Finished Dec 24 01:55:24 PM PST 23
Peak memory 229148 kb
Host smart-8a3e550d-1f2d-44cd-a0e5-89528a933a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920229391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1920229391
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2199522063
Short name T1279
Test name
Test status
Simulation time 1084407862 ps
CPU time 7.21 seconds
Started Dec 24 01:55:42 PM PST 23
Finished Dec 24 01:55:50 PM PST 23
Peak memory 231252 kb
Host smart-4e1ecdf2-1fda-451c-8e44-fd754c40912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199522063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2199522063
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_perf.2369681515
Short name T1022
Test name
Test status
Simulation time 148774632887 ps
CPU time 814.08 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 02:09:33 PM PST 23
Peak memory 260740 kb
Host smart-772813ed-5417-4412-85de-708e3b075834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369681515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_perf.2369681515
Directory /workspace/19.spi_device_perf/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3213782957
Short name T1576
Test name
Test status
Simulation time 25747237 ps
CPU time 0.76 seconds
Started Dec 24 01:55:50 PM PST 23
Finished Dec 24 01:55:52 PM PST 23
Peak memory 216624 kb
Host smart-00f32eb2-9e70-47b9-a217-1b71770cae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213782957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3213782957
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.567192562
Short name T35
Test name
Test status
Simulation time 1079028843 ps
CPU time 4.14 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:55:54 PM PST 23
Peak memory 221244 kb
Host smart-59a428a8-e23c-44c2-b400-72352a704474
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=567192562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.567192562
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_rx_async_fifo_reset.474160271
Short name T769
Test name
Test status
Simulation time 27031774 ps
CPU time 0.84 seconds
Started Dec 24 01:55:18 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 208436 kb
Host smart-e0a3d094-03f1-4f0c-a798-c2ac0c3a05b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474160271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_async_fifo_reset.474160271
Directory /workspace/19.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_rx_timeout.4082486499
Short name T513
Test name
Test status
Simulation time 820729666 ps
CPU time 6.88 seconds
Started Dec 24 01:55:52 PM PST 23
Finished Dec 24 01:56:00 PM PST 23
Peak memory 216932 kb
Host smart-177bf80a-852f-43d5-bd22-596bd2733f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082486499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_timeout.4082486499
Directory /workspace/19.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/19.spi_device_smoke.4046436691
Short name T1677
Test name
Test status
Simulation time 99742272 ps
CPU time 0.94 seconds
Started Dec 24 01:55:52 PM PST 23
Finished Dec 24 01:55:53 PM PST 23
Peak memory 207960 kb
Host smart-206158d9-4dfb-4f4f-95ba-b3e4708c5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046436691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_smoke.4046436691
Directory /workspace/19.spi_device_smoke/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1429362616
Short name T1433
Test name
Test status
Simulation time 96392144061 ps
CPU time 765.7 seconds
Started Dec 24 01:55:21 PM PST 23
Finished Dec 24 02:08:08 PM PST 23
Peak memory 330680 kb
Host smart-3fe465c7-3df5-482f-b05a-3f864a8d85c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429362616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1429362616
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2866711055
Short name T357
Test name
Test status
Simulation time 34812514918 ps
CPU time 142.91 seconds
Started Dec 24 01:55:20 PM PST 23
Finished Dec 24 01:57:45 PM PST 23
Peak memory 216968 kb
Host smart-23ca5c91-7b6c-4839-85be-f46a990b2387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866711055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2866711055
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1104365606
Short name T914
Test name
Test status
Simulation time 8508033974 ps
CPU time 23.49 seconds
Started Dec 24 01:55:52 PM PST 23
Finished Dec 24 01:56:16 PM PST 23
Peak memory 216876 kb
Host smart-9b56e78c-6e93-42f4-a60b-fcc3b6c13802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104365606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1104365606
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.247114844
Short name T1345
Test name
Test status
Simulation time 27412349 ps
CPU time 1.19 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 208128 kb
Host smart-9e80890d-fc3e-4986-8b7e-689f550db6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247114844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.247114844
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2768946567
Short name T1716
Test name
Test status
Simulation time 142006083 ps
CPU time 1.13 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:41 PM PST 23
Peak memory 207984 kb
Host smart-9cafe0e6-dd8a-4187-b1ee-4c83be2697b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768946567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2768946567
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tx_async_fifo_reset.754407408
Short name T1342
Test name
Test status
Simulation time 20144516 ps
CPU time 0.76 seconds
Started Dec 24 01:55:51 PM PST 23
Finished Dec 24 01:55:53 PM PST 23
Peak memory 208456 kb
Host smart-c6343149-cbcb-4918-a6e1-aabbff0d1272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754407408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tx_async_fifo_reset.754407408
Directory /workspace/19.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/19.spi_device_txrx.2645132824
Short name T1305
Test name
Test status
Simulation time 17305738759 ps
CPU time 187.92 seconds
Started Dec 24 01:55:15 PM PST 23
Finished Dec 24 01:58:24 PM PST 23
Peak memory 266164 kb
Host smart-3acbbba4-70cb-45ab-892a-14e7d8d478f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645132824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_txrx.2645132824
Directory /workspace/19.spi_device_txrx/latest

Test location /workspace/coverage/default/19.spi_device_upload.930514205
Short name T1549
Test name
Test status
Simulation time 405227696 ps
CPU time 3.78 seconds
Started Dec 24 01:55:39 PM PST 23
Finished Dec 24 01:55:44 PM PST 23
Peak memory 225196 kb
Host smart-87fef647-37a4-4367-8115-c93d3e3f41ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930514205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.930514205
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_abort.3869622702
Short name T1193
Test name
Test status
Simulation time 22331864 ps
CPU time 0.75 seconds
Started Dec 24 01:54:03 PM PST 23
Finished Dec 24 01:54:05 PM PST 23
Peak memory 206652 kb
Host smart-db4d00e8-cf3c-4cdb-bfa3-5c3b02972381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869622702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_abort.3869622702
Directory /workspace/2.spi_device_abort/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.107158300
Short name T1358
Test name
Test status
Simulation time 54176442 ps
CPU time 0.71 seconds
Started Dec 24 01:54:05 PM PST 23
Finished Dec 24 01:54:07 PM PST 23
Peak memory 206444 kb
Host smart-86e52623-ff2a-4ecb-aed1-ac02df7d27f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107158300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.107158300
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_bit_transfer.3182807234
Short name T1280
Test name
Test status
Simulation time 137780632 ps
CPU time 2.43 seconds
Started Dec 24 01:54:03 PM PST 23
Finished Dec 24 01:54:07 PM PST 23
Peak memory 216800 kb
Host smart-f628b969-74fc-4b24-8d3a-cb7db3913cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182807234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_bit_transfer.3182807234
Directory /workspace/2.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/2.spi_device_byte_transfer.825916410
Short name T735
Test name
Test status
Simulation time 1312025647 ps
CPU time 3.59 seconds
Started Dec 24 01:54:05 PM PST 23
Finished Dec 24 01:54:10 PM PST 23
Peak memory 216808 kb
Host smart-3f28cebb-dd2d-42ed-8966-a77f1dc1faf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825916410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_byte_transfer.825916410
Directory /workspace/2.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1090719627
Short name T1704
Test name
Test status
Simulation time 1542593206 ps
CPU time 4.79 seconds
Started Dec 24 01:54:03 PM PST 23
Finished Dec 24 01:54:09 PM PST 23
Peak memory 219592 kb
Host smart-a6139ede-b2ed-41c0-a94f-501877cd2692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090719627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1090719627
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1034936992
Short name T1700
Test name
Test status
Simulation time 16956483 ps
CPU time 0.79 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:07 PM PST 23
Peak memory 206588 kb
Host smart-0d208db8-d792-402e-86af-d063d20b1a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034936992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1034936992
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_dummy_item_extra_dly.1359407189
Short name T501
Test name
Test status
Simulation time 456221397314 ps
CPU time 2904.11 seconds
Started Dec 24 01:53:55 PM PST 23
Finished Dec 24 02:42:23 PM PST 23
Peak memory 270452 kb
Host smart-5e668be1-7705-4cc8-9af8-99c3808d036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359407189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_dummy_item_extra_dly.1359407189
Directory /workspace/2.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/2.spi_device_extreme_fifo_size.765193875
Short name T1023
Test name
Test status
Simulation time 69263842451 ps
CPU time 559.3 seconds
Started Dec 24 01:53:52 PM PST 23
Finished Dec 24 02:03:12 PM PST 23
Peak memory 217824 kb
Host smart-b0412c9c-eec8-4af9-825a-8bbac1388dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765193875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_extreme_fifo_size.765193875
Directory /workspace/2.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/2.spi_device_fifo_full.1137235628
Short name T1416
Test name
Test status
Simulation time 86402344354 ps
CPU time 1189.25 seconds
Started Dec 24 01:53:55 PM PST 23
Finished Dec 24 02:13:47 PM PST 23
Peak memory 265944 kb
Host smart-805e7105-0bc0-4d52-bb0e-2ef911b602ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137235628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_full.1137235628
Directory /workspace/2.spi_device_fifo_full/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.4075235187
Short name T1480
Test name
Test status
Simulation time 16403406718 ps
CPU time 46.52 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 01:54:57 PM PST 23
Peak memory 257372 kb
Host smart-6846159d-7ddd-49a6-9ba2-8131ce348ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075235187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.4075235187
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4194767773
Short name T333
Test name
Test status
Simulation time 610711173122 ps
CPU time 430.93 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 02:01:17 PM PST 23
Peak memory 266736 kb
Host smart-793493be-40d9-483c-a067-f976b705243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194767773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4194767773
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1017994220
Short name T1231
Test name
Test status
Simulation time 1557720556 ps
CPU time 24.64 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:40 PM PST 23
Peak memory 249760 kb
Host smart-7d8bbab8-d7b7-47f5-9708-bfe6e30b6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017994220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1017994220
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2631007347
Short name T1390
Test name
Test status
Simulation time 6242441089 ps
CPU time 21.49 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 248552 kb
Host smart-7f9a24b0-4717-4566-bf68-24168c1d8924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631007347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2631007347
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2488201311
Short name T312
Test name
Test status
Simulation time 1414237833 ps
CPU time 3.86 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:54:18 PM PST 23
Peak memory 225096 kb
Host smart-3471e5d1-c36f-4962-a3c8-cb772fab8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488201311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2488201311
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intr.3249296248
Short name T1311
Test name
Test status
Simulation time 154118539549 ps
CPU time 124.22 seconds
Started Dec 24 01:54:06 PM PST 23
Finished Dec 24 01:56:13 PM PST 23
Peak memory 252504 kb
Host smart-f30ebcf8-1f38-4917-a7c8-5e45855bf9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249296248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intr.3249296248
Directory /workspace/2.spi_device_intr/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.166168092
Short name T1588
Test name
Test status
Simulation time 1247953604 ps
CPU time 11.01 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 230964 kb
Host smart-4dcc5955-f8e4-49c8-aa46-0442b1fd5886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166168092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.166168092
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2655947547
Short name T1739
Test name
Test status
Simulation time 69284772 ps
CPU time 1.07 seconds
Started Dec 24 01:53:55 PM PST 23
Finished Dec 24 01:53:58 PM PST 23
Peak memory 218932 kb
Host smart-fe683f65-30cf-4ad8-8444-8a4365e11038
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655947547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2655947547
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4045474393
Short name T1330
Test name
Test status
Simulation time 2276088889 ps
CPU time 8.33 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:54:04 PM PST 23
Peak memory 257904 kb
Host smart-dc731755-a29a-4dc4-89d8-95a29832a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045474393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4045474393
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2127779061
Short name T249
Test name
Test status
Simulation time 902645763 ps
CPU time 7.11 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:13 PM PST 23
Peak memory 229332 kb
Host smart-4edeaa10-bc31-4532-b708-afd93244e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127779061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2127779061
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_perf.588917565
Short name T657
Test name
Test status
Simulation time 17898826491 ps
CPU time 328.99 seconds
Started Dec 24 01:53:56 PM PST 23
Finished Dec 24 01:59:28 PM PST 23
Peak memory 266188 kb
Host smart-87cd510a-6a9b-477b-a320-60b994d0b549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588917565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_perf.588917565
Directory /workspace/2.spi_device_perf/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.1340253492
Short name T1488
Test name
Test status
Simulation time 27426991 ps
CPU time 0.79 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:53:57 PM PST 23
Peak memory 216740 kb
Host smart-80d3d947-90b7-48df-b955-2f3d28eee613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340253492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1340253492
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2450256732
Short name T1620
Test name
Test status
Simulation time 504396149 ps
CPU time 4.47 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:18 PM PST 23
Peak memory 220160 kb
Host smart-90cf9b1f-4a75-4644-a638-547498fcbbeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2450256732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2450256732
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_rx_async_fifo_reset.896437400
Short name T1355
Test name
Test status
Simulation time 18916487 ps
CPU time 0.9 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:07 PM PST 23
Peak memory 208456 kb
Host smart-fb1f394e-9d76-4b7a-b4db-93e897cada64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896437400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_async_fifo_reset.896437400
Directory /workspace/2.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_rx_timeout.1378487852
Short name T1516
Test name
Test status
Simulation time 436823639 ps
CPU time 5.39 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:54:01 PM PST 23
Peak memory 216756 kb
Host smart-4b49ba9b-0d65-46ee-905c-ba00e7c6e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378487852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_timeout.1378487852
Directory /workspace/2.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2091464403
Short name T91
Test name
Test status
Simulation time 82884635 ps
CPU time 1.19 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:17 PM PST 23
Peak memory 238148 kb
Host smart-9bf47a7c-980c-4650-90c6-eadcaa1dcb8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091464403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2091464403
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_smoke.608588111
Short name T1297
Test name
Test status
Simulation time 181698599 ps
CPU time 1.09 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:07 PM PST 23
Peak memory 208336 kb
Host smart-b54892ce-35ca-476c-8655-4ac26bd5b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608588111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_smoke.608588111
Directory /workspace/2.spi_device_smoke/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3749608970
Short name T1701
Test name
Test status
Simulation time 860178830374 ps
CPU time 2077.13 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 02:28:48 PM PST 23
Peak memory 510132 kb
Host smart-4f304469-b8c4-4b51-837f-91200b3957bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749608970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3749608970
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1510417425
Short name T1669
Test name
Test status
Simulation time 27584353706 ps
CPU time 110.52 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:55:46 PM PST 23
Peak memory 216968 kb
Host smart-eb799b5a-1ad1-4a9d-8f23-a0430d3a387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510417425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1510417425
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.450799942
Short name T359
Test name
Test status
Simulation time 2002035736 ps
CPU time 2.63 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:53:58 PM PST 23
Peak memory 216808 kb
Host smart-069921e1-5fb2-404d-8819-934337795dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450799942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.450799942
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1600189747
Short name T1681
Test name
Test status
Simulation time 152204530 ps
CPU time 1.68 seconds
Started Dec 24 01:54:03 PM PST 23
Finished Dec 24 01:54:06 PM PST 23
Peak memory 216636 kb
Host smart-ed9374ef-a4cc-4430-99bd-cbb8624e0fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600189747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1600189747
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3228912119
Short name T485
Test name
Test status
Simulation time 121127510 ps
CPU time 0.85 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 01:54:11 PM PST 23
Peak memory 206904 kb
Host smart-3ef0e80d-3a10-41af-99c0-220ecf29f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228912119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3228912119
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tx_async_fifo_reset.1696218130
Short name T133
Test name
Test status
Simulation time 18919318 ps
CPU time 0.78 seconds
Started Dec 24 01:53:55 PM PST 23
Finished Dec 24 01:53:57 PM PST 23
Peak memory 208496 kb
Host smart-dc1ebee5-790a-4435-b5c6-3d9ea93053d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696218130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tx_async_fifo_reset.1696218130
Directory /workspace/2.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/2.spi_device_txrx.680138257
Short name T142
Test name
Test status
Simulation time 66337589722 ps
CPU time 164.28 seconds
Started Dec 24 01:53:54 PM PST 23
Finished Dec 24 01:56:40 PM PST 23
Peak memory 267300 kb
Host smart-7276b000-fda1-4a21-8f98-ac4d2c9273fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680138257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_txrx.680138257
Directory /workspace/2.spi_device_txrx/latest

Test location /workspace/coverage/default/2.spi_device_upload.4133526016
Short name T788
Test name
Test status
Simulation time 14782271269 ps
CPU time 21 seconds
Started Dec 24 01:54:05 PM PST 23
Finished Dec 24 01:54:28 PM PST 23
Peak memory 249704 kb
Host smart-abed5eed-a47f-407f-8e9c-e52396a659ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133526016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4133526016
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_abort.2311655372
Short name T810
Test name
Test status
Simulation time 15224960 ps
CPU time 0.82 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 206584 kb
Host smart-70239469-2b13-4c30-a6d6-0b6970ab8aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311655372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_abort.2311655372
Directory /workspace/20.spi_device_abort/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2567621362
Short name T1276
Test name
Test status
Simulation time 43069107 ps
CPU time 0.73 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:06 PM PST 23
Peak memory 206360 kb
Host smart-869e18a1-7e08-48e6-9856-81dfce623202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567621362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2567621362
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_bit_transfer.613414278
Short name T756
Test name
Test status
Simulation time 100353600 ps
CPU time 2.12 seconds
Started Dec 24 01:55:55 PM PST 23
Finished Dec 24 01:55:58 PM PST 23
Peak memory 216736 kb
Host smart-2ddbf3a3-ae10-45e0-b76b-6fabe38f7bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613414278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_bit_transfer.613414278
Directory /workspace/20.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/20.spi_device_byte_transfer.3484407237
Short name T1749
Test name
Test status
Simulation time 901804555 ps
CPU time 2.84 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 216788 kb
Host smart-086984a8-059e-4f2a-86a9-979fb625e58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484407237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_byte_transfer.3484407237
Directory /workspace/20.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.449246915
Short name T856
Test name
Test status
Simulation time 1565521936 ps
CPU time 7.29 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:55:57 PM PST 23
Peak memory 239680 kb
Host smart-90dd2f4a-b28d-4a99-9629-2213d618da9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449246915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.449246915
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3254385750
Short name T1266
Test name
Test status
Simulation time 100413110 ps
CPU time 0.82 seconds
Started Dec 24 01:55:40 PM PST 23
Finished Dec 24 01:55:42 PM PST 23
Peak memory 207556 kb
Host smart-bcd0cd4a-ef8e-4447-8c7d-96f985ea8e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254385750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3254385750
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_dummy_item_extra_dly.1185630312
Short name T1371
Test name
Test status
Simulation time 57638135471 ps
CPU time 257.15 seconds
Started Dec 24 01:55:35 PM PST 23
Finished Dec 24 01:59:53 PM PST 23
Peak memory 282532 kb
Host smart-0388ee9d-f86b-45f7-b478-ac139c999b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185630312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_dummy_item_extra_dly.1185630312
Directory /workspace/20.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/20.spi_device_extreme_fifo_size.2562419073
Short name T782
Test name
Test status
Simulation time 5470052058 ps
CPU time 124.45 seconds
Started Dec 24 01:55:42 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 218704 kb
Host smart-41a40212-d056-4c20-964c-5bbc5c817827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562419073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_extreme_fifo_size.2562419073
Directory /workspace/20.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/20.spi_device_fifo_full.3220087450
Short name T1057
Test name
Test status
Simulation time 36305951453 ps
CPU time 487.08 seconds
Started Dec 24 01:55:53 PM PST 23
Finished Dec 24 02:04:01 PM PST 23
Peak memory 274888 kb
Host smart-35631b5d-b228-4516-89bf-a8c60fdb1849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220087450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_full.3220087450
Directory /workspace/20.spi_device_fifo_full/latest

Test location /workspace/coverage/default/20.spi_device_fifo_underflow_overflow.2063120850
Short name T1100
Test name
Test status
Simulation time 33102781276 ps
CPU time 483.34 seconds
Started Dec 24 01:55:50 PM PST 23
Finished Dec 24 02:03:54 PM PST 23
Peak memory 503664 kb
Host smart-69f4dafc-e60d-44d6-b690-4962db7ae682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063120850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_underflow_overf
low.2063120850
Directory /workspace/20.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1447256875
Short name T1164
Test name
Test status
Simulation time 9182732951 ps
CPU time 74.09 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 257368 kb
Host smart-0ae5ebbb-0cce-4071-8078-55ee2e30cadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447256875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1447256875
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1413577271
Short name T324
Test name
Test status
Simulation time 79287693620 ps
CPU time 109.21 seconds
Started Dec 24 01:55:56 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 225176 kb
Host smart-bc401078-902b-4cf7-ba90-84c644b0cfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413577271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1413577271
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2002843298
Short name T1238
Test name
Test status
Simulation time 1959997869 ps
CPU time 33.75 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 241528 kb
Host smart-1504d8d9-f89a-4971-b5a3-18cd0011173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002843298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2002843298
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3157228987
Short name T1219
Test name
Test status
Simulation time 31547595760 ps
CPU time 39.23 seconds
Started Dec 24 01:55:55 PM PST 23
Finished Dec 24 01:56:36 PM PST 23
Peak memory 247440 kb
Host smart-cd55ea04-dba8-4708-aa8e-412ba04ec7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157228987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3157228987
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3167438709
Short name T988
Test name
Test status
Simulation time 2771350156 ps
CPU time 12.4 seconds
Started Dec 24 01:55:40 PM PST 23
Finished Dec 24 01:55:54 PM PST 23
Peak memory 238108 kb
Host smart-f851702a-1ec5-4d00-b2a2-746b372fb4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167438709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3167438709
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intr.2934207537
Short name T1378
Test name
Test status
Simulation time 31978946804 ps
CPU time 56.16 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:56:35 PM PST 23
Peak memory 240872 kb
Host smart-ec1b3f05-1677-4c87-b17e-e8aa5d63aaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934207537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intr.2934207537
Directory /workspace/20.spi_device_intr/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3269046150
Short name T297
Test name
Test status
Simulation time 5979902378 ps
CPU time 16.97 seconds
Started Dec 24 01:55:42 PM PST 23
Finished Dec 24 01:56:00 PM PST 23
Peak memory 249708 kb
Host smart-2b81d580-300d-4674-b6ca-6f7c22460171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269046150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3269046150
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3418833995
Short name T564
Test name
Test status
Simulation time 7145579624 ps
CPU time 21.85 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 247980 kb
Host smart-126c6fec-681f-4dc1-bb7f-298a10146fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418833995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3418833995
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2494061779
Short name T1474
Test name
Test status
Simulation time 6862280746 ps
CPU time 12.3 seconds
Started Dec 24 01:55:50 PM PST 23
Finished Dec 24 01:56:03 PM PST 23
Peak memory 238364 kb
Host smart-66c2b446-70ec-47f8-b727-6b339f56ed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494061779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2494061779
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_perf.3621756928
Short name T1408
Test name
Test status
Simulation time 8576183310 ps
CPU time 308.32 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 02:00:46 PM PST 23
Peak memory 265716 kb
Host smart-33e726fe-75bc-42d0-a4c1-70e062068007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621756928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_perf.3621756928
Directory /workspace/20.spi_device_perf/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2156700709
Short name T1535
Test name
Test status
Simulation time 588985931 ps
CPU time 4.11 seconds
Started Dec 24 01:55:40 PM PST 23
Finished Dec 24 01:55:46 PM PST 23
Peak memory 234480 kb
Host smart-1b2d5ba8-9b49-4101-b5db-e2871a6afca4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156700709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2156700709
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_rx_async_fifo_reset.505220381
Short name T675
Test name
Test status
Simulation time 36502345 ps
CPU time 0.87 seconds
Started Dec 24 01:55:54 PM PST 23
Finished Dec 24 01:55:56 PM PST 23
Peak memory 208404 kb
Host smart-ce4c73b3-e162-404d-96b2-fbc5e2134430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505220381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_async_fifo_reset.505220381
Directory /workspace/20.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_rx_timeout.2816176622
Short name T1245
Test name
Test status
Simulation time 2626945503 ps
CPU time 5.21 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:42 PM PST 23
Peak memory 216832 kb
Host smart-c69e27c5-b46c-411d-bc4f-2cea103770fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816176622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_timeout.2816176622
Directory /workspace/20.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/20.spi_device_smoke.1892088978
Short name T1288
Test name
Test status
Simulation time 254653973 ps
CPU time 1.13 seconds
Started Dec 24 01:55:56 PM PST 23
Finished Dec 24 01:55:58 PM PST 23
Peak memory 216560 kb
Host smart-db15b563-8106-4f16-8242-07803d7abc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892088978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_smoke.1892088978
Directory /workspace/20.spi_device_smoke/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1139185207
Short name T1104
Test name
Test status
Simulation time 3660871641 ps
CPU time 51.64 seconds
Started Dec 24 01:55:38 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 216720 kb
Host smart-a39efb72-0333-4f52-9aad-6cacceea862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139185207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1139185207
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3985867386
Short name T1683
Test name
Test status
Simulation time 1024486334 ps
CPU time 5.81 seconds
Started Dec 24 01:55:40 PM PST 23
Finished Dec 24 01:55:47 PM PST 23
Peak memory 216732 kb
Host smart-e4898da1-0703-4609-aa71-1e7150a8fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985867386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3985867386
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3759802429
Short name T672
Test name
Test status
Simulation time 278387132 ps
CPU time 3.32 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 01:55:42 PM PST 23
Peak memory 216808 kb
Host smart-a404fe7d-3d56-4f6d-aeb5-4bc0fa508a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759802429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3759802429
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1146483449
Short name T865
Test name
Test status
Simulation time 74845745 ps
CPU time 0.97 seconds
Started Dec 24 01:55:43 PM PST 23
Finished Dec 24 01:55:45 PM PST 23
Peak memory 206904 kb
Host smart-16b655c0-9ed4-4c0f-8f4b-b8d3f98130ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146483449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1146483449
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tx_async_fifo_reset.2312497119
Short name T795
Test name
Test status
Simulation time 41719479 ps
CPU time 0.75 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:55:51 PM PST 23
Peak memory 208456 kb
Host smart-ddeab7d1-7b0d-4148-979e-1344ced91015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312497119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tx_async_fifo_reset.2312497119
Directory /workspace/20.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/20.spi_device_txrx.1630392421
Short name T622
Test name
Test status
Simulation time 12844995359 ps
CPU time 162.79 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 287656 kb
Host smart-c88af5c7-6be0-4010-9f54-7cf129501e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630392421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_txrx.1630392421
Directory /workspace/20.spi_device_txrx/latest

Test location /workspace/coverage/default/20.spi_device_upload.4164660509
Short name T263
Test name
Test status
Simulation time 4246648636 ps
CPU time 15.5 seconds
Started Dec 24 01:55:55 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 251680 kb
Host smart-a1a2afaa-ab9f-4161-abc2-93f4d6bf0423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164660509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4164660509
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_abort.3368280671
Short name T1769
Test name
Test status
Simulation time 49526759 ps
CPU time 0.8 seconds
Started Dec 24 01:56:14 PM PST 23
Finished Dec 24 01:56:18 PM PST 23
Peak memory 206580 kb
Host smart-45762887-e315-44bd-9554-33534eaf5b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368280671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_abort.3368280671
Directory /workspace/21.spi_device_abort/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.742564751
Short name T1706
Test name
Test status
Simulation time 13419463 ps
CPU time 0.77 seconds
Started Dec 24 01:56:27 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 206600 kb
Host smart-4ce61700-9611-468c-8192-e0246708a72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742564751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.742564751
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_bit_transfer.1491106816
Short name T1613
Test name
Test status
Simulation time 169129003 ps
CPU time 2.6 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 216692 kb
Host smart-7d57cda6-3e6d-4d0c-a74a-a6a526d7d3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491106816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_bit_transfer.1491106816
Directory /workspace/21.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/21.spi_device_byte_transfer.225471785
Short name T1036
Test name
Test status
Simulation time 639368090 ps
CPU time 3.02 seconds
Started Dec 24 01:55:52 PM PST 23
Finished Dec 24 01:55:56 PM PST 23
Peak memory 216824 kb
Host smart-f71356f8-455f-4ab6-8566-c00b7fac77ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225471785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_byte_transfer.225471785
Directory /workspace/21.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4175196389
Short name T847
Test name
Test status
Simulation time 36281216 ps
CPU time 2.54 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 218780 kb
Host smart-9269cd4e-8de4-4cd3-8225-a119cf6e9ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175196389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4175196389
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2544319030
Short name T771
Test name
Test status
Simulation time 16957609 ps
CPU time 0.8 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 207448 kb
Host smart-05db061a-fe08-436d-a989-5582c3e12606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544319030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2544319030
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_dummy_item_extra_dly.4277801694
Short name T1249
Test name
Test status
Simulation time 191655590805 ps
CPU time 1158.61 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 02:15:32 PM PST 23
Peak memory 250832 kb
Host smart-1a71574a-0a0f-459a-b44f-1d1f0c41a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277801694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_dummy_item_extra_dly.4277801694
Directory /workspace/21.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/21.spi_device_extreme_fifo_size.4116835759
Short name T846
Test name
Test status
Simulation time 1104436731923 ps
CPU time 945.32 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 02:11:53 PM PST 23
Peak memory 219180 kb
Host smart-3c463ed9-01e0-4359-8174-bd98c2d6da3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116835759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_extreme_fifo_size.4116835759
Directory /workspace/21.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/21.spi_device_fifo_full.1707971352
Short name T660
Test name
Test status
Simulation time 49030139729 ps
CPU time 670.98 seconds
Started Dec 24 01:56:00 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 304132 kb
Host smart-119e0d04-8c35-4ab0-af82-a1d09bf8711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707971352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_full.1707971352
Directory /workspace/21.spi_device_fifo_full/latest

Test location /workspace/coverage/default/21.spi_device_fifo_underflow_overflow.2751323776
Short name T1444
Test name
Test status
Simulation time 115726558982 ps
CPU time 921.75 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 02:11:31 PM PST 23
Peak memory 714188 kb
Host smart-e96972a0-bcc1-461c-af1b-d3de4ddc640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751323776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_underflow_overf
low.2751323776
Directory /workspace/21.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.551024992
Short name T874
Test name
Test status
Simulation time 10454171298 ps
CPU time 31.93 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:56:58 PM PST 23
Peak memory 255212 kb
Host smart-844ec9e1-bf13-4ef8-b265-610c065df361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551024992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.551024992
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.636730328
Short name T320
Test name
Test status
Simulation time 93401644279 ps
CPU time 554.89 seconds
Started Dec 24 01:56:35 PM PST 23
Finished Dec 24 02:05:55 PM PST 23
Peak memory 282188 kb
Host smart-1ad5d040-b93b-4e43-bb2b-fe180235d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636730328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.636730328
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1538266804
Short name T1724
Test name
Test status
Simulation time 62019364812 ps
CPU time 119.39 seconds
Started Dec 24 01:56:34 PM PST 23
Finished Dec 24 01:58:35 PM PST 23
Peak memory 250368 kb
Host smart-2fa6ef5c-75c3-4d43-b092-8eb892b1eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538266804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1538266804
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2027868104
Short name T1785
Test name
Test status
Simulation time 10707445704 ps
CPU time 47.65 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:57:17 PM PST 23
Peak memory 252628 kb
Host smart-aed3e454-c6da-4be5-9fd6-04617e88c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027868104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2027868104
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intr.232242552
Short name T685
Test name
Test status
Simulation time 35212268848 ps
CPU time 32.1 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:56:41 PM PST 23
Peak memory 225184 kb
Host smart-315bde71-bac0-43b5-b159-ecd9d88d48be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232242552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intr.232242552
Directory /workspace/21.spi_device_intr/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4235912298
Short name T277
Test name
Test status
Simulation time 20874320719 ps
CPU time 28.75 seconds
Started Dec 24 01:56:09 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 252868 kb
Host smart-4051b321-0bdf-44ef-8e33-fcfcf893518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235912298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4235912298
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1468983478
Short name T1161
Test name
Test status
Simulation time 51228359 ps
CPU time 3.16 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 239980 kb
Host smart-572627ef-5d8b-4603-b1b4-042d67e00a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468983478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1468983478
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.183108267
Short name T978
Test name
Test status
Simulation time 764175816 ps
CPU time 4.75 seconds
Started Dec 24 01:56:09 PM PST 23
Finished Dec 24 01:56:20 PM PST 23
Peak memory 249528 kb
Host smart-3d353937-745c-4000-851e-b9451a3deb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183108267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.183108267
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_perf.533711386
Short name T55
Test name
Test status
Simulation time 21065938407 ps
CPU time 436.64 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 02:03:38 PM PST 23
Peak memory 247744 kb
Host smart-0d28bd5b-97ce-4b7c-aa19-ee2b8d5c677e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533711386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_perf.533711386
Directory /workspace/21.spi_device_perf/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3834170338
Short name T175
Test name
Test status
Simulation time 6749122555 ps
CPU time 5.15 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 01:56:32 PM PST 23
Peak memory 236852 kb
Host smart-9d773a6c-140c-477d-9183-a264650dd823
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3834170338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3834170338
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_rx_async_fifo_reset.2251715329
Short name T1216
Test name
Test status
Simulation time 173826898 ps
CPU time 0.95 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:11 PM PST 23
Peak memory 208384 kb
Host smart-d956243d-2ef0-4d80-83a4-546b4face66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251715329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_async_fifo_reset.2251715329
Directory /workspace/21.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_rx_timeout.2841055984
Short name T569
Test name
Test status
Simulation time 1965318469 ps
CPU time 5.68 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 216728 kb
Host smart-6698eac3-5203-4059-89c4-2980aace63ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841055984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_timeout.2841055984
Directory /workspace/21.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/21.spi_device_smoke.2111577419
Short name T498
Test name
Test status
Simulation time 56469050 ps
CPU time 1.14 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:56:03 PM PST 23
Peak memory 208332 kb
Host smart-4349b009-ca94-4ef7-bdb2-8ab30438337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111577419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_smoke.2111577419
Directory /workspace/21.spi_device_smoke/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2178591347
Short name T1434
Test name
Test status
Simulation time 50478437488 ps
CPU time 739.54 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 02:11:06 PM PST 23
Peak memory 479492 kb
Host smart-0f173850-7b75-487c-a524-d671b13a2f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178591347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2178591347
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1844514506
Short name T643
Test name
Test status
Simulation time 16114782292 ps
CPU time 124.82 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 217048 kb
Host smart-add73c14-f88c-4e3a-b307-2a636f4b9daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844514506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1844514506
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4166088184
Short name T483
Test name
Test status
Simulation time 859630821 ps
CPU time 5.83 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:30 PM PST 23
Peak memory 216424 kb
Host smart-07f2535b-b075-4601-bfd8-573ae251d292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166088184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4166088184
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.203290040
Short name T1626
Test name
Test status
Simulation time 216460282 ps
CPU time 7.64 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:17 PM PST 23
Peak memory 216776 kb
Host smart-9dbb7f08-edd1-404c-bf17-c09b5230c347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203290040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.203290040
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4227219524
Short name T659
Test name
Test status
Simulation time 98383103 ps
CPU time 0.73 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 01:56:28 PM PST 23
Peak memory 206912 kb
Host smart-df752b3b-4502-4e92-a43b-1ce2a572989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227219524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4227219524
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tx_async_fifo_reset.3982534865
Short name T648
Test name
Test status
Simulation time 17400240 ps
CPU time 0.77 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:09 PM PST 23
Peak memory 208472 kb
Host smart-6a37fea1-4abe-4478-86c4-f80fa206a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982534865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tx_async_fifo_reset.3982534865
Directory /workspace/21.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/21.spi_device_txrx.3916795492
Short name T1281
Test name
Test status
Simulation time 63338649243 ps
CPU time 346.4 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 02:01:57 PM PST 23
Peak memory 297368 kb
Host smart-f1bf96df-2dd1-40f6-98dd-88e1536e6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916795492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_txrx.3916795492
Directory /workspace/21.spi_device_txrx/latest

Test location /workspace/coverage/default/21.spi_device_upload.2417324515
Short name T240
Test name
Test status
Simulation time 9782771517 ps
CPU time 29.83 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 233288 kb
Host smart-e67314f5-4e78-4d84-8146-5130aa5552e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417324515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2417324515
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_abort.2715286721
Short name T1381
Test name
Test status
Simulation time 17057388 ps
CPU time 0.78 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:02 PM PST 23
Peak memory 206544 kb
Host smart-27898fd5-48cd-427d-b19b-859dbd52c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715286721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_abort.2715286721
Directory /workspace/22.spi_device_abort/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4200157411
Short name T1291
Test name
Test status
Simulation time 33979178 ps
CPU time 0.69 seconds
Started Dec 24 01:55:54 PM PST 23
Finished Dec 24 01:55:56 PM PST 23
Peak memory 206476 kb
Host smart-8c80728d-8180-45bb-8ae0-71548d0cbac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200157411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4200157411
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_bit_transfer.2524877959
Short name T1232
Test name
Test status
Simulation time 2161313728 ps
CPU time 2.45 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:56:00 PM PST 23
Peak memory 216904 kb
Host smart-3a598990-f176-4f7d-968c-d01e2bad97fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524877959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_bit_transfer.2524877959
Directory /workspace/22.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/22.spi_device_byte_transfer.108903866
Short name T1372
Test name
Test status
Simulation time 216771060 ps
CPU time 2.9 seconds
Started Dec 24 01:55:39 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 216872 kb
Host smart-7e4f720b-8373-4dab-922f-e6c16730cf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108903866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_byte_transfer.108903866
Directory /workspace/22.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.992096626
Short name T111
Test name
Test status
Simulation time 87651455 ps
CPU time 0.81 seconds
Started Dec 24 01:55:56 PM PST 23
Finished Dec 24 01:55:58 PM PST 23
Peak memory 206608 kb
Host smart-60ef794a-2d8a-490e-8512-c3b1fd96f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992096626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.992096626
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_dummy_item_extra_dly.3959525860
Short name T898
Test name
Test status
Simulation time 84355261169 ps
CPU time 593.51 seconds
Started Dec 24 01:55:25 PM PST 23
Finished Dec 24 02:05:19 PM PST 23
Peak memory 270652 kb
Host smart-09faea8a-88da-4b8c-a8d7-cf7829a7ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959525860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_dummy_item_extra_dly.3959525860
Directory /workspace/22.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/22.spi_device_extreme_fifo_size.683341217
Short name T838
Test name
Test status
Simulation time 69518314801 ps
CPU time 1676.67 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 02:24:24 PM PST 23
Peak memory 216972 kb
Host smart-57eb6979-7b24-4669-80bf-c27a3958adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683341217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_extreme_fifo_size.683341217
Directory /workspace/22.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/22.spi_device_fifo_full.795122764
Short name T38
Test name
Test status
Simulation time 69075294032 ps
CPU time 295.2 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 02:01:24 PM PST 23
Peak memory 282636 kb
Host smart-4e7b919e-4a90-4ff0-bd18-a9e8b8df6d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795122764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_full.795122764
Directory /workspace/22.spi_device_fifo_full/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3526023502
Short name T345
Test name
Test status
Simulation time 19333723117 ps
CPU time 93.84 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 269900 kb
Host smart-5ab6e158-e2df-43af-8a01-c86c32ec7d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526023502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3526023502
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1716631942
Short name T1071
Test name
Test status
Simulation time 5723235285 ps
CPU time 33.44 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:56:23 PM PST 23
Peak memory 254284 kb
Host smart-83ea3c16-52f7-45f1-808b-e5ac0139c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716631942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1716631942
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.201776800
Short name T283
Test name
Test status
Simulation time 1021136914 ps
CPU time 6.23 seconds
Started Dec 24 01:55:54 PM PST 23
Finished Dec 24 01:56:02 PM PST 23
Peak memory 241464 kb
Host smart-0549a87a-0c57-4720-8f0d-5c984c1928be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201776800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.201776800
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intr.2039548490
Short name T1713
Test name
Test status
Simulation time 34736969349 ps
CPU time 33.48 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 219096 kb
Host smart-4e419d81-76d4-4379-88cc-c32c72fe49d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039548490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intr.2039548490
Directory /workspace/22.spi_device_intr/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1486138136
Short name T853
Test name
Test status
Simulation time 17331501014 ps
CPU time 12.78 seconds
Started Dec 24 01:55:49 PM PST 23
Finished Dec 24 01:56:03 PM PST 23
Peak memory 232880 kb
Host smart-600ee277-c3e7-42da-9c1a-f64ca2c5b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486138136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1486138136
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.920944242
Short name T851
Test name
Test status
Simulation time 7088124397 ps
CPU time 7.45 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:56:05 PM PST 23
Peak memory 237724 kb
Host smart-3dc431d6-406a-461d-aaae-277c3a5e3345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920944242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.920944242
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.560603846
Short name T1425
Test name
Test status
Simulation time 385618406 ps
CPU time 4.12 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:05 PM PST 23
Peak memory 240160 kb
Host smart-2abbf8b7-8164-4ccb-8475-7c5ca5929f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560603846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.560603846
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_perf.107101823
Short name T1772
Test name
Test status
Simulation time 19749419826 ps
CPU time 1262.55 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 02:17:04 PM PST 23
Peak memory 283688 kb
Host smart-4600077c-ccc3-4c00-97c6-17c5e4d20d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107101823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_perf.107101823
Directory /workspace/22.spi_device_perf/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1190898083
Short name T1551
Test name
Test status
Simulation time 2499028385 ps
CPU time 4.62 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:16 PM PST 23
Peak memory 220316 kb
Host smart-dc4b72bb-f919-4f46-a81a-a3b0c4715aa1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1190898083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1190898083
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_rx_async_fifo_reset.1034315195
Short name T710
Test name
Test status
Simulation time 47257468 ps
CPU time 0.94 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:02 PM PST 23
Peak memory 208388 kb
Host smart-a417328d-ac38-4c23-8713-cba9af8fdd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034315195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_async_fifo_reset.1034315195
Directory /workspace/22.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_rx_timeout.838567522
Short name T1263
Test name
Test status
Simulation time 639110203 ps
CPU time 5.53 seconds
Started Dec 24 01:55:36 PM PST 23
Finished Dec 24 01:55:44 PM PST 23
Peak memory 216808 kb
Host smart-c18381ad-1bf9-4b61-8e07-5fd2391f0eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838567522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_timeout.838567522
Directory /workspace/22.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/22.spi_device_smoke.884358650
Short name T1398
Test name
Test status
Simulation time 29877676 ps
CPU time 1.17 seconds
Started Dec 24 01:55:37 PM PST 23
Finished Dec 24 01:55:40 PM PST 23
Peak memory 216808 kb
Host smart-3e644b76-a9f9-46ac-809d-ddbdc7fd801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884358650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_smoke.884358650
Directory /workspace/22.spi_device_smoke/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1721632641
Short name T1646
Test name
Test status
Simulation time 137500683426 ps
CPU time 575.95 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 02:05:43 PM PST 23
Peak memory 348124 kb
Host smart-abc723cb-f942-4df2-8208-da1b267bdce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721632641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1721632641
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3113056592
Short name T1645
Test name
Test status
Simulation time 23782778905 ps
CPU time 97.5 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:57:58 PM PST 23
Peak memory 216856 kb
Host smart-b73c2e43-78d7-4e9a-83bf-595610c36c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113056592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3113056592
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.571074811
Short name T1783
Test name
Test status
Simulation time 730614617 ps
CPU time 5.47 seconds
Started Dec 24 01:55:39 PM PST 23
Finished Dec 24 01:55:45 PM PST 23
Peak memory 216864 kb
Host smart-c2485232-ed87-4713-95d8-b4c4b2f6885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571074811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.571074811
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1013339900
Short name T703
Test name
Test status
Simulation time 70113070 ps
CPU time 1.24 seconds
Started Dec 24 01:55:48 PM PST 23
Finished Dec 24 01:55:50 PM PST 23
Peak memory 208560 kb
Host smart-7697898e-9496-41b6-927f-ce2f16035696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013339900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1013339900
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1177733823
Short name T1506
Test name
Test status
Simulation time 105218642 ps
CPU time 0.99 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:56:03 PM PST 23
Peak memory 207796 kb
Host smart-86a08ea5-1b76-4e46-bf7b-82398a8a0d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177733823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1177733823
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tx_async_fifo_reset.3339948504
Short name T135
Test name
Test status
Simulation time 16281955 ps
CPU time 0.78 seconds
Started Dec 24 01:55:51 PM PST 23
Finished Dec 24 01:55:52 PM PST 23
Peak memory 208360 kb
Host smart-ba6e1e72-095e-4d7d-81b1-26d49cb3e667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339948504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tx_async_fifo_reset.3339948504
Directory /workspace/22.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/22.spi_device_txrx.3003564040
Short name T139
Test name
Test status
Simulation time 51465935028 ps
CPU time 250.28 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 02:02:57 PM PST 23
Peak memory 317800 kb
Host smart-9052a27c-3ea3-4582-80ea-28aa62abaebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003564040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_txrx.3003564040
Directory /workspace/22.spi_device_txrx/latest

Test location /workspace/coverage/default/22.spi_device_upload.564904098
Short name T996
Test name
Test status
Simulation time 27050644806 ps
CPU time 28.31 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:46 PM PST 23
Peak memory 232308 kb
Host smart-a2dd4806-704b-4ccf-8500-4a5bd331afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564904098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.564904098
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_abort.2399775397
Short name T879
Test name
Test status
Simulation time 54006546 ps
CPU time 0.77 seconds
Started Dec 24 01:55:51 PM PST 23
Finished Dec 24 01:55:53 PM PST 23
Peak memory 206564 kb
Host smart-8376a54a-a6dd-4628-abb4-f58247a837a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399775397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_abort.2399775397
Directory /workspace/23.spi_device_abort/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3604798024
Short name T940
Test name
Test status
Simulation time 20097566 ps
CPU time 0.74 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:11 PM PST 23
Peak memory 206420 kb
Host smart-304cc066-f22c-4572-97f7-19df397ae82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604798024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3604798024
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_bit_transfer.2153852071
Short name T571
Test name
Test status
Simulation time 121123947 ps
CPU time 2.56 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:56:00 PM PST 23
Peak memory 216908 kb
Host smart-c5804f9c-f2f6-458b-8db4-e5fdba623c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153852071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_bit_transfer.2153852071
Directory /workspace/23.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/23.spi_device_byte_transfer.1879808064
Short name T783
Test name
Test status
Simulation time 211969667 ps
CPU time 2.9 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:24 PM PST 23
Peak memory 216788 kb
Host smart-8db58254-71d3-4c70-87c3-0b67d7c36e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879808064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_byte_transfer.1879808064
Directory /workspace/23.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.535281230
Short name T1172
Test name
Test status
Simulation time 2393458628 ps
CPU time 5.83 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:56:09 PM PST 23
Peak memory 222316 kb
Host smart-50e72dba-ef89-4b67-8fd7-8f7029645b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535281230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.535281230
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3038040122
Short name T927
Test name
Test status
Simulation time 13923931 ps
CPU time 0.79 seconds
Started Dec 24 01:55:52 PM PST 23
Finished Dec 24 01:55:54 PM PST 23
Peak memory 207580 kb
Host smart-8e7b222a-adf1-4b42-a3c4-ee428a115ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038040122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3038040122
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_dummy_item_extra_dly.79692655
Short name T670
Test name
Test status
Simulation time 47625629976 ps
CPU time 409.76 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 02:02:56 PM PST 23
Peak memory 273980 kb
Host smart-ba1d690b-219b-4764-9a02-faabe8be4f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79692655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_dummy_item_extra_dly.79692655
Directory /workspace/23.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/23.spi_device_extreme_fifo_size.3450227387
Short name T257
Test name
Test status
Simulation time 122254199334 ps
CPU time 61.97 seconds
Started Dec 24 01:55:51 PM PST 23
Finished Dec 24 01:56:54 PM PST 23
Peak memory 233448 kb
Host smart-2bd055cc-08c7-4b65-b136-c8f1531498b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450227387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_extreme_fifo_size.3450227387
Directory /workspace/23.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/23.spi_device_fifo_full.3479576119
Short name T1202
Test name
Test status
Simulation time 205826858452 ps
CPU time 797.91 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:09:29 PM PST 23
Peak memory 249776 kb
Host smart-b1ec054b-7cdf-4447-a7db-331f4faa240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479576119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_full.3479576119
Directory /workspace/23.spi_device_fifo_full/latest

Test location /workspace/coverage/default/23.spi_device_fifo_underflow_overflow.2074873821
Short name T1566
Test name
Test status
Simulation time 3434008372 ps
CPU time 54.12 seconds
Started Dec 24 01:55:48 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 267856 kb
Host smart-7eeb7215-e550-4178-9a42-b916c3b4f667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074873821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_underflow_overf
low.2074873821
Directory /workspace/23.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2697195324
Short name T314
Test name
Test status
Simulation time 69590623731 ps
CPU time 20.86 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:56:18 PM PST 23
Peak memory 241388 kb
Host smart-f076a59f-ad36-418c-8881-9bb702cd6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697195324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2697195324
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3610691278
Short name T334
Test name
Test status
Simulation time 29734493848 ps
CPU time 58.09 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:57:20 PM PST 23
Peak memory 252548 kb
Host smart-f16af82a-8a40-4a78-83ff-84e12344cd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610691278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3610691278
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.534638846
Short name T1304
Test name
Test status
Simulation time 5332875014 ps
CPU time 32.64 seconds
Started Dec 24 01:56:00 PM PST 23
Finished Dec 24 01:56:34 PM PST 23
Peak memory 229136 kb
Host smart-6b68478a-a69b-4d7f-b894-cc8e223a94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534638846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.534638846
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.383075881
Short name T1766
Test name
Test status
Simulation time 356593731 ps
CPU time 4.81 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:10 PM PST 23
Peak memory 239588 kb
Host smart-b415c3f8-3a5c-4aa1-aed0-8975b256f49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383075881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.383075881
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intr.3979134832
Short name T1200
Test name
Test status
Simulation time 28842139745 ps
CPU time 76.84 seconds
Started Dec 24 01:56:00 PM PST 23
Finished Dec 24 01:57:19 PM PST 23
Peak memory 236216 kb
Host smart-b3fc70e5-0bca-4dc8-856d-5e247eda66e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979134832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intr.3979134832
Directory /workspace/23.spi_device_intr/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.275707860
Short name T1424
Test name
Test status
Simulation time 427140275 ps
CPU time 5.78 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:06 PM PST 23
Peak memory 241124 kb
Host smart-0a428509-e25c-4a67-8f67-2ebf23e58d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275707860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.275707860
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2623164860
Short name T1781
Test name
Test status
Simulation time 12775042995 ps
CPU time 21.46 seconds
Started Dec 24 01:55:54 PM PST 23
Finished Dec 24 01:56:17 PM PST 23
Peak memory 248824 kb
Host smart-9b859722-affd-4a95-a687-ac6841489bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623164860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2623164860
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3604641380
Short name T284
Test name
Test status
Simulation time 178666497 ps
CPU time 3.29 seconds
Started Dec 24 01:55:39 PM PST 23
Finished Dec 24 01:55:43 PM PST 23
Peak memory 233384 kb
Host smart-ce868bc5-3875-4bdb-a6cc-c616996443a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604641380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3604641380
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_perf.827329908
Short name T613
Test name
Test status
Simulation time 75833315059 ps
CPU time 2189.35 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:32:40 PM PST 23
Peak memory 241040 kb
Host smart-d8a054de-cb6b-4fa5-ac45-928b21d982dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827329908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_perf.827329908
Directory /workspace/23.spi_device_perf/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3369544415
Short name T1510
Test name
Test status
Simulation time 475006991 ps
CPU time 4.59 seconds
Started Dec 24 01:55:53 PM PST 23
Finished Dec 24 01:55:58 PM PST 23
Peak memory 220828 kb
Host smart-58210064-4648-46ac-8822-60ca8d35aeff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3369544415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3369544415
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_rx_async_fifo_reset.1953393736
Short name T553
Test name
Test status
Simulation time 77044145 ps
CPU time 0.92 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 01:56:00 PM PST 23
Peak memory 208524 kb
Host smart-caf356c3-f820-4e1e-83ac-d2f64e2d5593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953393736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_async_fifo_reset.1953393736
Directory /workspace/23.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_rx_timeout.3899148586
Short name T114
Test name
Test status
Simulation time 2441604382 ps
CPU time 5.37 seconds
Started Dec 24 01:56:02 PM PST 23
Finished Dec 24 01:56:11 PM PST 23
Peak memory 216864 kb
Host smart-100544f6-845d-4c99-b149-b298cb16d2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899148586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_timeout.3899148586
Directory /workspace/23.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/23.spi_device_smoke.3581677498
Short name T721
Test name
Test status
Simulation time 136485501 ps
CPU time 1.18 seconds
Started Dec 24 01:56:16 PM PST 23
Finished Dec 24 01:56:20 PM PST 23
Peak memory 216384 kb
Host smart-13f849cd-0aa2-4ffe-9abe-a5dba5dc230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581677498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_smoke.3581677498
Directory /workspace/23.spi_device_smoke/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3868906311
Short name T1240
Test name
Test status
Simulation time 3775080935 ps
CPU time 16.21 seconds
Started Dec 24 01:55:48 PM PST 23
Finished Dec 24 01:56:05 PM PST 23
Peak memory 216900 kb
Host smart-245185a1-fb6a-444a-ac42-647e8920ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868906311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3868906311
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1419034215
Short name T545
Test name
Test status
Simulation time 713147724 ps
CPU time 4.15 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:28 PM PST 23
Peak memory 216836 kb
Host smart-5f46b018-b5c3-44dd-a64b-284578b09a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419034215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1419034215
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3835231099
Short name T552
Test name
Test status
Simulation time 83919352 ps
CPU time 1.54 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:01 PM PST 23
Peak memory 216712 kb
Host smart-533cde39-f6ca-45fb-b713-7147780bcfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835231099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3835231099
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3311220632
Short name T1346
Test name
Test status
Simulation time 52299879 ps
CPU time 0.87 seconds
Started Dec 24 01:55:54 PM PST 23
Finished Dec 24 01:55:57 PM PST 23
Peak memory 206952 kb
Host smart-87544937-0798-4b91-94b9-994feabf4fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311220632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3311220632
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tx_async_fifo_reset.3239478391
Short name T673
Test name
Test status
Simulation time 23000064 ps
CPU time 0.77 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:11 PM PST 23
Peak memory 208452 kb
Host smart-c487e438-bbba-4bc6-8b0f-b08fb0d34656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239478391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tx_async_fifo_reset.3239478391
Directory /workspace/23.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/23.spi_device_txrx.1205724052
Short name T1779
Test name
Test status
Simulation time 182535286895 ps
CPU time 180.94 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:59:12 PM PST 23
Peak memory 269992 kb
Host smart-2ec6f582-b53e-4f88-9c42-a131a4abf81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205724052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_txrx.1205724052
Directory /workspace/23.spi_device_txrx/latest

Test location /workspace/coverage/default/23.spi_device_upload.4158662628
Short name T270
Test name
Test status
Simulation time 146340953 ps
CPU time 4.03 seconds
Started Dec 24 01:55:52 PM PST 23
Finished Dec 24 01:55:56 PM PST 23
Peak memory 221124 kb
Host smart-fc945cc8-2ebc-49ad-9a83-8c6f6320b3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158662628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4158662628
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_abort.1113735658
Short name T664
Test name
Test status
Simulation time 52664440 ps
CPU time 0.75 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:11 PM PST 23
Peak memory 206660 kb
Host smart-dc2c4d39-66ee-43e1-a661-406831ca02e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113735658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_abort.1113735658
Directory /workspace/24.spi_device_abort/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2355626778
Short name T1001
Test name
Test status
Simulation time 14389030 ps
CPU time 0.74 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:22 PM PST 23
Peak memory 206504 kb
Host smart-e7f05458-b984-4330-8453-0f20bab823f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355626778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2355626778
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_bit_transfer.2437847564
Short name T650
Test name
Test status
Simulation time 332986611 ps
CPU time 3.45 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 216788 kb
Host smart-5e180d6a-ee87-489f-835d-c53e41d41054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437847564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_bit_transfer.2437847564
Directory /workspace/24.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/24.spi_device_byte_transfer.191654128
Short name T1606
Test name
Test status
Simulation time 188858437 ps
CPU time 2.88 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:56:06 PM PST 23
Peak memory 216776 kb
Host smart-808c7228-dd71-42ad-8d82-3b747848d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191654128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_byte_transfer.191654128
Directory /workspace/24.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2258546813
Short name T1682
Test name
Test status
Simulation time 18306748836 ps
CPU time 11.8 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:35 PM PST 23
Peak memory 222160 kb
Host smart-21813979-268f-4860-9617-2420a1ca764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258546813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2258546813
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4214151139
Short name T1218
Test name
Test status
Simulation time 40263101 ps
CPU time 0.77 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 206572 kb
Host smart-3835e49f-94c3-4d47-9f32-81016fc33ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214151139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4214151139
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_dummy_item_extra_dly.4026507819
Short name T1165
Test name
Test status
Simulation time 58176110711 ps
CPU time 432.92 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 02:03:20 PM PST 23
Peak memory 274048 kb
Host smart-9cf35651-7a55-4f88-88e6-a754fe5198e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026507819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_dummy_item_extra_dly.4026507819
Directory /workspace/24.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/24.spi_device_extreme_fifo_size.880304099
Short name T1768
Test name
Test status
Simulation time 57616138414 ps
CPU time 1850.51 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 02:26:52 PM PST 23
Peak memory 219196 kb
Host smart-9b273443-20d0-4f83-a24f-656e57add591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880304099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_extreme_fifo_size.880304099
Directory /workspace/24.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/24.spi_device_fifo_full.3159524985
Short name T9
Test name
Test status
Simulation time 86404653135 ps
CPU time 750.34 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 303752 kb
Host smart-bd7ef0b8-9bef-4d95-9308-f45b76ccaa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159524985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_full.3159524985
Directory /workspace/24.spi_device_fifo_full/latest

Test location /workspace/coverage/default/24.spi_device_fifo_underflow_overflow.2982678043
Short name T888
Test name
Test status
Simulation time 255690892036 ps
CPU time 340.78 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 02:01:44 PM PST 23
Peak memory 340232 kb
Host smart-e5073e1d-2bca-4aad-b330-e3ca008aba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982678043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_underflow_overf
low.2982678043
Directory /workspace/24.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1063575294
Short name T1582
Test name
Test status
Simulation time 9101120527 ps
CPU time 23.24 seconds
Started Dec 24 01:56:09 PM PST 23
Finished Dec 24 01:56:38 PM PST 23
Peak memory 247880 kb
Host smart-bce667de-6e34-4401-91dc-895d33b8ddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063575294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1063575294
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2927472728
Short name T1636
Test name
Test status
Simulation time 34500518727 ps
CPU time 120.21 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:58:25 PM PST 23
Peak memory 249728 kb
Host smart-5f3ad251-ddff-4a7c-a5fa-78d8e9fd79ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927472728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2927472728
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.775641426
Short name T110
Test name
Test status
Simulation time 11411511614 ps
CPU time 41 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 253644 kb
Host smart-f1c7c2b3-0df3-4ffd-a30d-8d4c05ed4e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775641426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.775641426
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3797022596
Short name T1156
Test name
Test status
Simulation time 8040352770 ps
CPU time 40.26 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:57:10 PM PST 23
Peak memory 241400 kb
Host smart-3572aa5c-38ed-4cf5-8830-c33af3385da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797022596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3797022596
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3463166886
Short name T236
Test name
Test status
Simulation time 1022811850 ps
CPU time 5.07 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 220252 kb
Host smart-708c63cd-76b6-4462-b64d-7de2937b0ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463166886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3463166886
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intr.2680911051
Short name T1733
Test name
Test status
Simulation time 46935151169 ps
CPU time 58.19 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:57:08 PM PST 23
Peak memory 225196 kb
Host smart-fdf17215-9007-4367-9c4c-c520313c9744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680911051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intr.2680911051
Directory /workspace/24.spi_device_intr/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3778797318
Short name T1303
Test name
Test status
Simulation time 13796149609 ps
CPU time 44.54 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:57:08 PM PST 23
Peak memory 232536 kb
Host smart-b0212315-ed35-4211-aca3-af76eacc7ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778797318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3778797318
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2669251942
Short name T1406
Test name
Test status
Simulation time 1194222070 ps
CPU time 6.08 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 220668 kb
Host smart-c94d696f-49cb-4594-bc04-2c5c24565af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669251942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2669251942
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.859620886
Short name T1463
Test name
Test status
Simulation time 1297971182 ps
CPU time 4.26 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 225188 kb
Host smart-7e8584f6-1537-4837-81f2-98fc47a6862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859620886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.859620886
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_perf.4086217671
Short name T716
Test name
Test status
Simulation time 20783389527 ps
CPU time 600.32 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 02:06:14 PM PST 23
Peak memory 276084 kb
Host smart-562f6d6d-beeb-4158-b9fe-0893d073ddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086217671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_perf.4086217671
Directory /workspace/24.spi_device_perf/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4150488356
Short name T1067
Test name
Test status
Simulation time 1595754292 ps
CPU time 4.54 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:14 PM PST 23
Peak memory 234396 kb
Host smart-08af691e-920f-4022-9cc2-a648ca5858c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4150488356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4150488356
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_rx_async_fifo_reset.684862997
Short name T1326
Test name
Test status
Simulation time 59967111 ps
CPU time 0.87 seconds
Started Dec 24 01:56:17 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 208452 kb
Host smart-b8789a95-7af0-43ca-936f-4b9be0653594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684862997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_async_fifo_reset.684862997
Directory /workspace/24.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_rx_timeout.2234110202
Short name T582
Test name
Test status
Simulation time 2518435222 ps
CPU time 5.05 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 216872 kb
Host smart-5dd36460-a20b-4304-945b-596ce8071bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234110202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_timeout.2234110202
Directory /workspace/24.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/24.spi_device_smoke.3004931104
Short name T999
Test name
Test status
Simulation time 101451319 ps
CPU time 1.13 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:25 PM PST 23
Peak memory 216788 kb
Host smart-cfc538d8-12f3-4de7-9a74-a13198e70612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004931104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_smoke.3004931104
Directory /workspace/24.spi_device_smoke/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1792195275
Short name T1427
Test name
Test status
Simulation time 2021727755514 ps
CPU time 1275.09 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 02:17:39 PM PST 23
Peak memory 354164 kb
Host smart-8b4db20d-fba8-47a4-a0bf-91bdd08ea16e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792195275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1792195275
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3874554273
Short name T1477
Test name
Test status
Simulation time 470728941 ps
CPU time 6.99 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:07 PM PST 23
Peak memory 219640 kb
Host smart-473c0799-2040-4dac-80e9-69051afac4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874554273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3874554273
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3863780579
Short name T864
Test name
Test status
Simulation time 4544881018 ps
CPU time 15.63 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:34 PM PST 23
Peak memory 216840 kb
Host smart-b685b3d3-d760-4dae-ae04-4f8d9cc4ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863780579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3863780579
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.123464934
Short name T772
Test name
Test status
Simulation time 204197610 ps
CPU time 1.47 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:07 PM PST 23
Peak memory 216808 kb
Host smart-389f8a2e-edac-4e4e-ab73-808bdd3d6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123464934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.123464934
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2254361956
Short name T748
Test name
Test status
Simulation time 85781661 ps
CPU time 1.04 seconds
Started Dec 24 01:56:02 PM PST 23
Finished Dec 24 01:56:05 PM PST 23
Peak memory 208040 kb
Host smart-d5a26d56-0fca-4ae1-8c9d-4e8b93dd1a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254361956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2254361956
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tx_async_fifo_reset.1210858493
Short name T74
Test name
Test status
Simulation time 38667385 ps
CPU time 0.74 seconds
Started Dec 24 01:55:58 PM PST 23
Finished Dec 24 01:56:00 PM PST 23
Peak memory 208488 kb
Host smart-c339c284-38c5-4ed7-a713-5319efa8640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210858493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tx_async_fifo_reset.1210858493
Directory /workspace/24.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/24.spi_device_txrx.2246472232
Short name T1647
Test name
Test status
Simulation time 21019323782 ps
CPU time 256.69 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:00:28 PM PST 23
Peak memory 269352 kb
Host smart-281c0afc-14d7-43c7-8dea-a388e79bcbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246472232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_txrx.2246472232
Directory /workspace/24.spi_device_txrx/latest

Test location /workspace/coverage/default/24.spi_device_upload.559752693
Short name T1688
Test name
Test status
Simulation time 9724970927 ps
CPU time 17.38 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 235804 kb
Host smart-89ef545a-180f-4465-b8e9-b471e5f47dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559752693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.559752693
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2837218825
Short name T495
Test name
Test status
Simulation time 12743531 ps
CPU time 0.73 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:55:58 PM PST 23
Peak memory 206412 kb
Host smart-eee8214d-c8f4-4aec-a926-8a886dba8db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837218825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2837218825
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_bit_transfer.3742722126
Short name T1486
Test name
Test status
Simulation time 354455236 ps
CPU time 3.04 seconds
Started Dec 24 01:58:46 PM PST 23
Finished Dec 24 01:58:51 PM PST 23
Peak memory 216624 kb
Host smart-7f39195e-f3b2-4429-98c0-f75bb07c8bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742722126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_bit_transfer.3742722126
Directory /workspace/25.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/25.spi_device_byte_transfer.1170336400
Short name T472
Test name
Test status
Simulation time 141453001 ps
CPU time 2.76 seconds
Started Dec 24 01:56:28 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 216860 kb
Host smart-efa3019a-fbae-4ab3-b519-888a301917ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170336400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_byte_transfer.1170336400
Directory /workspace/25.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2483602345
Short name T282
Test name
Test status
Simulation time 652321061 ps
CPU time 5.09 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:19 PM PST 23
Peak memory 241516 kb
Host smart-dfbf80a4-8827-4764-bb0b-e46c96e2a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483602345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2483602345
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.244237413
Short name T934
Test name
Test status
Simulation time 41350444 ps
CPU time 0.77 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 01:58:47 PM PST 23
Peak memory 206216 kb
Host smart-f7d3e9d4-22b6-49eb-91e4-43f2caf92bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244237413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.244237413
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_dummy_item_extra_dly.4161905203
Short name T1761
Test name
Test status
Simulation time 84625570790 ps
CPU time 115.74 seconds
Started Dec 24 01:58:46 PM PST 23
Finished Dec 24 02:00:44 PM PST 23
Peak memory 256652 kb
Host smart-f055f152-d912-4a47-a680-aad4efadd474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161905203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_dummy_item_extra_dly.4161905203
Directory /workspace/25.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/25.spi_device_extreme_fifo_size.1329062707
Short name T1354
Test name
Test status
Simulation time 73052497159 ps
CPU time 621.09 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 02:06:49 PM PST 23
Peak memory 224816 kb
Host smart-727ce46b-1326-4fa4-9d9a-dc6aa952ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329062707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_extreme_fifo_size.1329062707
Directory /workspace/25.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/25.spi_device_fifo_full.1912940137
Short name T1426
Test name
Test status
Simulation time 17365198717 ps
CPU time 418.05 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 02:03:25 PM PST 23
Peak memory 267576 kb
Host smart-6eb5e4dc-6b19-4a09-99da-f68ff649f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912940137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_full.1912940137
Directory /workspace/25.spi_device_fifo_full/latest

Test location /workspace/coverage/default/25.spi_device_fifo_underflow_overflow.1095288956
Short name T1282
Test name
Test status
Simulation time 282345470310 ps
CPU time 361.75 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 02:02:29 PM PST 23
Peak memory 340284 kb
Host smart-2e6e1055-92c2-436b-8206-f5d5fe89864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095288956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_underflow_overf
low.1095288956
Directory /workspace/25.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3287046684
Short name T205
Test name
Test status
Simulation time 1497026107 ps
CPU time 19.74 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 257676 kb
Host smart-fe1740c5-f08a-4fe8-8c42-19882b328fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287046684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3287046684
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.282466478
Short name T48
Test name
Test status
Simulation time 90020799924 ps
CPU time 279.67 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 02:00:50 PM PST 23
Peak memory 257996 kb
Host smart-69f9cf05-c98b-4c3b-a4c1-715708e8ea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282466478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.282466478
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3627110473
Short name T1255
Test name
Test status
Simulation time 16853418453 ps
CPU time 91.44 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:57:37 PM PST 23
Peak memory 223912 kb
Host smart-15a2bb75-6407-46de-9296-2a9ea8f59f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627110473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3627110473
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4228441600
Short name T998
Test name
Test status
Simulation time 1440227658 ps
CPU time 14.69 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:25 PM PST 23
Peak memory 235456 kb
Host smart-e035612f-16c9-42f5-89e8-e7af879324a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228441600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4228441600
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.154434672
Short name T1495
Test name
Test status
Simulation time 3699750377 ps
CPU time 4.22 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:56:28 PM PST 23
Peak memory 218508 kb
Host smart-865c5eaa-dbbf-4415-86ca-64f16d2240aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154434672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.154434672
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intr.2840704202
Short name T129
Test name
Test status
Simulation time 3336197955 ps
CPU time 19.67 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 01:59:06 PM PST 23
Peak memory 223940 kb
Host smart-abd6f822-f1e6-4f39-a570-9e2298f43d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840704202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intr.2840704202
Directory /workspace/25.spi_device_intr/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2371669072
Short name T1047
Test name
Test status
Simulation time 5656960753 ps
CPU time 17.31 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:29 PM PST 23
Peak memory 252400 kb
Host smart-73a30779-f844-4ebf-9a5c-56dd15f18c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371669072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2371669072
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.61624780
Short name T1577
Test name
Test status
Simulation time 37005464 ps
CPU time 3.07 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:56:32 PM PST 23
Peak memory 234224 kb
Host smart-8f11aae7-af14-48c1-bc53-b0d5b1ede12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61624780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.61624780
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2652293126
Short name T1290
Test name
Test status
Simulation time 4456671978 ps
CPU time 9.13 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:56:38 PM PST 23
Peak memory 218528 kb
Host smart-c44e7120-a5d2-44d2-b583-407e57e8b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652293126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2652293126
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_perf.2519024353
Short name T714
Test name
Test status
Simulation time 2743870210 ps
CPU time 190.69 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:59:41 PM PST 23
Peak memory 239496 kb
Host smart-8d64301f-7fb8-4600-bd21-86916e334106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519024353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_perf.2519024353
Directory /workspace/25.spi_device_perf/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3767170053
Short name T1085
Test name
Test status
Simulation time 1437642856 ps
CPU time 4.26 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 219756 kb
Host smart-388ebf65-7486-457b-a454-5d18398c4540
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3767170053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3767170053
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_rx_async_fifo_reset.3828237383
Short name T1021
Test name
Test status
Simulation time 84397740 ps
CPU time 0.84 seconds
Started Dec 24 01:56:27 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 208544 kb
Host smart-e44568a9-1baf-4f60-ba6d-ec38c8c54dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828237383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_async_fifo_reset.3828237383
Directory /workspace/25.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_rx_timeout.1918304476
Short name T521
Test name
Test status
Simulation time 545017227 ps
CPU time 5.33 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 01:58:52 PM PST 23
Peak memory 216564 kb
Host smart-f6e036f3-8bb7-4221-b9a7-5a5a6245bd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918304476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_timeout.1918304476
Directory /workspace/25.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/25.spi_device_smoke.2477702008
Short name T596
Test name
Test status
Simulation time 67506893 ps
CPU time 1.12 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:23 PM PST 23
Peak memory 216548 kb
Host smart-235a141d-d0d9-43cf-8cea-9d01c88882f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477702008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_smoke.2477702008
Directory /workspace/25.spi_device_smoke/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2262538741
Short name T1309
Test name
Test status
Simulation time 2809885817 ps
CPU time 22.92 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 01:59:09 PM PST 23
Peak memory 220336 kb
Host smart-431772ae-eb54-4d6c-8a72-7b7f5e952589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262538741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2262538741
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.262735228
Short name T489
Test name
Test status
Simulation time 4476235757 ps
CPU time 13.48 seconds
Started Dec 24 01:56:28 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 217984 kb
Host smart-036d7991-9e98-4cb1-a5a1-7fbc160af3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262735228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.262735228
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2084370183
Short name T1019
Test name
Test status
Simulation time 153630143 ps
CPU time 2.16 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:56:32 PM PST 23
Peak memory 216752 kb
Host smart-737f48a2-d262-447a-aef8-d0fcc918c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084370183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2084370183
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.283152347
Short name T1139
Test name
Test status
Simulation time 46421774 ps
CPU time 0.9 seconds
Started Dec 24 01:56:28 PM PST 23
Finished Dec 24 01:56:32 PM PST 23
Peak memory 206880 kb
Host smart-28f061ce-bc12-4e19-a43e-03f3d4394234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283152347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.283152347
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tx_async_fifo_reset.1836017126
Short name T743
Test name
Test status
Simulation time 68369366 ps
CPU time 0.78 seconds
Started Dec 24 01:57:58 PM PST 23
Finished Dec 24 01:58:00 PM PST 23
Peak memory 208240 kb
Host smart-03ace96f-ba4a-4c96-8f2d-e8b28471de99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836017126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tx_async_fifo_reset.1836017126
Directory /workspace/25.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/25.spi_device_txrx.1213983696
Short name T475
Test name
Test status
Simulation time 22766061329 ps
CPU time 394.16 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 02:02:55 PM PST 23
Peak memory 289492 kb
Host smart-6f8a2515-6a22-49f3-813c-7a15a8e61bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213983696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_txrx.1213983696
Directory /workspace/25.spi_device_txrx/latest

Test location /workspace/coverage/default/25.spi_device_upload.1486481626
Short name T309
Test name
Test status
Simulation time 2843610015 ps
CPU time 9.29 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:30 PM PST 23
Peak memory 241552 kb
Host smart-5f9e7248-3981-4781-a621-9769b9afe4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486481626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1486481626
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_abort.1282925347
Short name T526
Test name
Test status
Simulation time 22818139 ps
CPU time 0.77 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:07 PM PST 23
Peak memory 206624 kb
Host smart-65317edb-527e-4a2a-800b-8efbe7560be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282925347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_abort.1282925347
Directory /workspace/26.spi_device_abort/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.786305203
Short name T727
Test name
Test status
Simulation time 54129246 ps
CPU time 0.74 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:56:23 PM PST 23
Peak memory 206528 kb
Host smart-496b2173-79aa-44b3-bad6-7bf48f148a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786305203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.786305203
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_bit_transfer.1809505513
Short name T1479
Test name
Test status
Simulation time 753452052 ps
CPU time 3.14 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:17 PM PST 23
Peak memory 216816 kb
Host smart-863333a3-0bfc-40fb-ade4-e57bdb22874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809505513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_bit_transfer.1809505513
Directory /workspace/26.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/26.spi_device_byte_transfer.4032243055
Short name T537
Test name
Test status
Simulation time 591055743 ps
CPU time 3.02 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 216788 kb
Host smart-94f104e0-44c4-4499-804e-2aac704293dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032243055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_byte_transfer.4032243055
Directory /workspace/26.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4179922725
Short name T306
Test name
Test status
Simulation time 101618895 ps
CPU time 3.17 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:17 PM PST 23
Peak memory 239932 kb
Host smart-d7f48b26-2dff-4163-bb1b-1f22bb7437ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179922725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4179922725
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1374828246
Short name T742
Test name
Test status
Simulation time 139634763 ps
CPU time 0.8 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 206608 kb
Host smart-ec2109ed-3ebc-4c1a-b40d-600214356f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374828246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1374828246
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_dummy_item_extra_dly.3523027320
Short name T492
Test name
Test status
Simulation time 809941773664 ps
CPU time 1100.09 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 02:14:28 PM PST 23
Peak memory 303540 kb
Host smart-e80092ba-5236-4e6f-b0da-ed03c261b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523027320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_dummy_item_extra_dly.3523027320
Directory /workspace/26.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/26.spi_device_extreme_fifo_size.4101720170
Short name T256
Test name
Test status
Simulation time 416284420503 ps
CPU time 1365.85 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 02:18:47 PM PST 23
Peak memory 225104 kb
Host smart-cba2e74f-871d-46d3-b510-521788ea1b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101720170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_extreme_fifo_size.4101720170
Directory /workspace/26.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/26.spi_device_fifo_full.1193441983
Short name T1482
Test name
Test status
Simulation time 57528188785 ps
CPU time 1036.76 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 02:13:19 PM PST 23
Peak memory 250724 kb
Host smart-4f5a8f7a-e38d-41af-b5b5-8d57f4b520f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193441983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_full.1193441983
Directory /workspace/26.spi_device_fifo_full/latest

Test location /workspace/coverage/default/26.spi_device_fifo_underflow_overflow.2704438916
Short name T512
Test name
Test status
Simulation time 184381066690 ps
CPU time 869.95 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 02:10:36 PM PST 23
Peak memory 579028 kb
Host smart-c66ef3e3-113b-421f-8828-bce905f89b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704438916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_underflow_overf
low.2704438916
Directory /workspace/26.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.707609463
Short name T332
Test name
Test status
Simulation time 49064853399 ps
CPU time 236.69 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 02:00:09 PM PST 23
Peak memory 249764 kb
Host smart-605d230b-4873-42fb-96a4-8f1b66e78724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707609463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.707609463
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1149142869
Short name T645
Test name
Test status
Simulation time 88337621464 ps
CPU time 197.83 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:59:26 PM PST 23
Peak memory 256852 kb
Host smart-972385c2-9cb9-46bd-8972-a50742797d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149142869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1149142869
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4008406683
Short name T245
Test name
Test status
Simulation time 4707986755 ps
CPU time 80.92 seconds
Started Dec 24 01:56:04 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 249852 kb
Host smart-e31d0b72-60ff-4ae4-a9af-043b38c0e9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008406683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4008406683
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1307746337
Short name T1182
Test name
Test status
Simulation time 3738364281 ps
CPU time 11.4 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:32 PM PST 23
Peak memory 241172 kb
Host smart-67f5d1b0-3dd2-4466-aa33-77228b943149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307746337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1307746337
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.951091387
Short name T1742
Test name
Test status
Simulation time 567141482 ps
CPU time 3.78 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:09 PM PST 23
Peak memory 237952 kb
Host smart-644d39d7-dc14-43e7-b976-c6f02ebfba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951091387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.951091387
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intr.3051732864
Short name T789
Test name
Test status
Simulation time 37366785838 ps
CPU time 37.69 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 232420 kb
Host smart-fccccf9c-4dcc-4bf1-88fe-0c714a896f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051732864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intr.3051732864
Directory /workspace/26.spi_device_intr/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2357022853
Short name T220
Test name
Test status
Simulation time 9612604394 ps
CPU time 38.3 seconds
Started Dec 24 01:56:09 PM PST 23
Finished Dec 24 01:56:53 PM PST 23
Peak memory 255312 kb
Host smart-50c763d2-ea50-4fc4-94b9-e541a404e624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357022853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2357022853
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.106245687
Short name T223
Test name
Test status
Simulation time 10883702518 ps
CPU time 23.45 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:34 PM PST 23
Peak memory 230848 kb
Host smart-79b03912-6c29-4ccf-a389-3f8e29a60bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106245687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.106245687
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2709846804
Short name T1400
Test name
Test status
Simulation time 3975628613 ps
CPU time 18.15 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 233292 kb
Host smart-d04b3ef6-11d9-4544-ae23-487b7b42b3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709846804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2709846804
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_perf.1071612407
Short name T1190
Test name
Test status
Simulation time 2074535498 ps
CPU time 57.31 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:57:00 PM PST 23
Peak memory 231488 kb
Host smart-9ebe3306-6551-4d8a-a171-20ae833a27b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071612407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_perf.1071612407
Directory /workspace/26.spi_device_perf/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3209114995
Short name T1374
Test name
Test status
Simulation time 4948164536 ps
CPU time 7.2 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 236580 kb
Host smart-9ad60cb9-c589-4b83-b9ac-051fa86c62f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3209114995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3209114995
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_rx_async_fifo_reset.2980243473
Short name T746
Test name
Test status
Simulation time 34325811 ps
CPU time 0.87 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:13 PM PST 23
Peak memory 208508 kb
Host smart-9757c1df-5e48-4b11-a582-46741146d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980243473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_async_fifo_reset.2980243473
Directory /workspace/26.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_rx_timeout.1167246621
Short name T532
Test name
Test status
Simulation time 550468801 ps
CPU time 5.39 seconds
Started Dec 24 01:56:10 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 216868 kb
Host smart-42d587d2-574b-4f73-8938-0bca171a7c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167246621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_timeout.1167246621
Directory /workspace/26.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/26.spi_device_smoke.23405620
Short name T1257
Test name
Test status
Simulation time 44930995 ps
CPU time 0.94 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:07 PM PST 23
Peak memory 207856 kb
Host smart-52d462b1-baec-4f8b-ba97-6616f605f739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23405620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_smoke.23405620
Directory /workspace/26.spi_device_smoke/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1689262037
Short name T1055
Test name
Test status
Simulation time 164664187618 ps
CPU time 2949.38 seconds
Started Dec 24 01:56:06 PM PST 23
Finished Dec 24 02:45:20 PM PST 23
Peak memory 266332 kb
Host smart-5389e7a7-2ae3-45fe-a3ba-0341aea9a3f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689262037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1689262037
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2226512194
Short name T1176
Test name
Test status
Simulation time 27427659196 ps
CPU time 86.97 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 216796 kb
Host smart-9fb867de-d3f5-4fc8-97e6-298f84d479cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226512194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2226512194
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.337693995
Short name T1448
Test name
Test status
Simulation time 93856076399 ps
CPU time 26.14 seconds
Started Dec 24 01:55:59 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 216804 kb
Host smart-fead3054-bbef-4044-8a78-4e8310055cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337693995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.337693995
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.243640681
Short name T621
Test name
Test status
Simulation time 44401454 ps
CPU time 1.16 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:07 PM PST 23
Peak memory 208036 kb
Host smart-4e0264d6-aeb2-492a-902d-551c04578129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243640681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.243640681
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.512039573
Short name T1719
Test name
Test status
Simulation time 34735832 ps
CPU time 0.83 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 01:56:07 PM PST 23
Peak memory 206920 kb
Host smart-3cef680e-be3c-4b1c-8c21-9f02aff0337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512039573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.512039573
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tx_async_fifo_reset.3284778645
Short name T1437
Test name
Test status
Simulation time 15081319 ps
CPU time 0.78 seconds
Started Dec 24 01:55:57 PM PST 23
Finished Dec 24 01:55:59 PM PST 23
Peak memory 208408 kb
Host smart-8d672ffb-8577-4541-b5f5-509c1dfa85df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284778645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tx_async_fifo_reset.3284778645
Directory /workspace/26.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/26.spi_device_txrx.1706920633
Short name T1666
Test name
Test status
Simulation time 37031481213 ps
CPU time 112.2 seconds
Started Dec 24 01:56:16 PM PST 23
Finished Dec 24 01:58:12 PM PST 23
Peak memory 267364 kb
Host smart-b26dc7d1-de0e-4770-8e6d-56e7604a774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706920633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_txrx.1706920633
Directory /workspace/26.spi_device_txrx/latest

Test location /workspace/coverage/default/26.spi_device_upload.905648616
Short name T1032
Test name
Test status
Simulation time 944826039 ps
CPU time 8.39 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:56:17 PM PST 23
Peak memory 227900 kb
Host smart-5acfcfee-d177-4ca6-bb6b-8a9d45959954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905648616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.905648616
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_abort.2121787349
Short name T1732
Test name
Test status
Simulation time 45335833 ps
CPU time 0.77 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 01:56:14 PM PST 23
Peak memory 206628 kb
Host smart-e87d2cdf-f91c-44c1-9493-1418a0a45e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121787349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_abort.2121787349
Directory /workspace/27.spi_device_abort/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1010951048
Short name T1487
Test name
Test status
Simulation time 25060587 ps
CPU time 0.71 seconds
Started Dec 24 01:56:35 PM PST 23
Finished Dec 24 01:56:41 PM PST 23
Peak memory 206404 kb
Host smart-bdd26c06-175e-4f1f-8c6d-a9434ae73227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010951048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1010951048
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_bit_transfer.1528254336
Short name T1711
Test name
Test status
Simulation time 479916344 ps
CPU time 2.44 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:23 PM PST 23
Peak memory 216792 kb
Host smart-e650739a-67c4-4d85-9efc-55b9eda9f505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528254336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_bit_transfer.1528254336
Directory /workspace/27.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/27.spi_device_byte_transfer.2081659026
Short name T732
Test name
Test status
Simulation time 514388247 ps
CPU time 3.21 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 216768 kb
Host smart-6a2cbf08-d8dc-48ae-b71d-0dbf9c18d2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081659026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_byte_transfer.2081659026
Directory /workspace/27.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1591213850
Short name T921
Test name
Test status
Simulation time 776788319 ps
CPU time 3.71 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:56:29 PM PST 23
Peak memory 224468 kb
Host smart-60edbce5-621e-4404-8f28-fe4985cfe41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591213850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1591213850
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3620712178
Short name T547
Test name
Test status
Simulation time 26747236 ps
CPU time 0.74 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:12 PM PST 23
Peak memory 206608 kb
Host smart-be3da6ef-9ee4-4dbb-b8cc-dc8f15d8a097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620712178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3620712178
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_dummy_item_extra_dly.3188939607
Short name T580
Test name
Test status
Simulation time 137501840598 ps
CPU time 221.35 seconds
Started Dec 24 01:56:01 PM PST 23
Finished Dec 24 01:59:44 PM PST 23
Peak memory 287788 kb
Host smart-a79f1483-e714-47cf-ad64-aa963a9ad207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188939607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_dummy_item_extra_dly.3188939607
Directory /workspace/27.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/27.spi_device_extreme_fifo_size.397116995
Short name T1740
Test name
Test status
Simulation time 184057171688 ps
CPU time 767.63 seconds
Started Dec 24 01:56:03 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 219080 kb
Host smart-642ed342-3827-438f-b5fb-3c4f47822583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397116995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_extreme_fifo_size.397116995
Directory /workspace/27.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/27.spi_device_fifo_full.1957471901
Short name T2
Test name
Test status
Simulation time 50866191311 ps
CPU time 663.4 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 272888 kb
Host smart-b107b208-78f7-44ec-b2df-1fcdff4ed25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957471901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_full.1957471901
Directory /workspace/27.spi_device_fifo_full/latest

Test location /workspace/coverage/default/27.spi_device_fifo_underflow_overflow.3822501317
Short name T586
Test name
Test status
Simulation time 66024426287 ps
CPU time 159.94 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:58:58 PM PST 23
Peak memory 320196 kb
Host smart-c7576f9f-9e9a-4bc4-bfe1-23a253dac4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822501317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_underflow_overf
low.3822501317
Directory /workspace/27.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2967886299
Short name T992
Test name
Test status
Simulation time 15391519785 ps
CPU time 46.61 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:57:13 PM PST 23
Peak memory 249688 kb
Host smart-3b062cf3-b069-49fa-80b1-cc6ac583d831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967886299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2967886299
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.100512667
Short name T20
Test name
Test status
Simulation time 6387725163 ps
CPU time 78.72 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 251360 kb
Host smart-a930194b-3513-4298-9e72-34f522722fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100512667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.100512667
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.569494000
Short name T216
Test name
Test status
Simulation time 3929273496 ps
CPU time 78.16 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 267524 kb
Host smart-951f838b-5630-426e-8f1c-449248af2ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569494000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.569494000
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4091965230
Short name T351
Test name
Test status
Simulation time 12424513736 ps
CPU time 14.5 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:56:36 PM PST 23
Peak memory 238944 kb
Host smart-0ec25a59-06b2-40c7-85fe-d8f50ceec9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091965230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4091965230
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4222836598
Short name T1759
Test name
Test status
Simulation time 7733773345 ps
CPU time 5.47 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:28 PM PST 23
Peak memory 220812 kb
Host smart-5d93493d-a3a0-44cf-b236-9ac86fc02af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222836598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4222836598
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intr.2178843073
Short name T1217
Test name
Test status
Simulation time 9416709493 ps
CPU time 50.06 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:57:02 PM PST 23
Peak memory 235324 kb
Host smart-3a71ef37-3b93-4991-90ce-87357b4b0b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178843073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intr.2178843073
Directory /workspace/27.spi_device_intr/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1424971048
Short name T803
Test name
Test status
Simulation time 2068437402 ps
CPU time 9.67 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 233224 kb
Host smart-b83bcd4f-694d-4601-bec1-079283839d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424971048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1424971048
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3942824272
Short name T293
Test name
Test status
Simulation time 1366433429 ps
CPU time 8.98 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 249076 kb
Host smart-c9df2990-98bc-4782-9174-043f58c034b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942824272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3942824272
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.357493399
Short name T1157
Test name
Test status
Simulation time 280778323 ps
CPU time 4.44 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 234288 kb
Host smart-bc854c98-7611-416f-96d9-2b1e81728f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357493399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.357493399
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_perf.1848971390
Short name T1113
Test name
Test status
Simulation time 85571112536 ps
CPU time 1349.62 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 02:18:40 PM PST 23
Peak memory 272548 kb
Host smart-7baeb775-93fd-4bde-8298-a0371d69be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848971390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_perf.1848971390
Directory /workspace/27.spi_device_perf/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2182779744
Short name T1273
Test name
Test status
Simulation time 6753990743 ps
CPU time 7.99 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 234800 kb
Host smart-2e7eebf8-9504-41f9-bdb0-dd8a8fa3afc0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2182779744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2182779744
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_rx_async_fifo_reset.1794776092
Short name T1500
Test name
Test status
Simulation time 21807641 ps
CPU time 0.91 seconds
Started Dec 24 01:56:09 PM PST 23
Finished Dec 24 01:56:15 PM PST 23
Peak memory 207932 kb
Host smart-ebba5158-f1c5-4345-8015-6e7959dcb823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794776092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_async_fifo_reset.1794776092
Directory /workspace/27.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_rx_timeout.3725752825
Short name T961
Test name
Test status
Simulation time 428377946 ps
CPU time 5.57 seconds
Started Dec 24 01:56:09 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 216888 kb
Host smart-c552df22-0afc-4659-bbf8-a53e556a888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725752825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_timeout.3725752825
Directory /workspace/27.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/27.spi_device_smoke.2978075689
Short name T1659
Test name
Test status
Simulation time 245522931 ps
CPU time 1 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:19 PM PST 23
Peak memory 208052 kb
Host smart-bd70268e-3262-40d7-bb6b-73f5eeac131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978075689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_smoke.2978075689
Directory /workspace/27.spi_device_smoke/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3507493995
Short name T355
Test name
Test status
Simulation time 3957127271 ps
CPU time 35.33 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:56 PM PST 23
Peak memory 217012 kb
Host smart-7546a67e-ba92-4a60-931c-8715938bc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507493995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3507493995
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2437699880
Short name T499
Test name
Test status
Simulation time 1673626250 ps
CPU time 4.31 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 216716 kb
Host smart-025cba92-764a-424f-abaf-0790ed8702ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437699880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2437699880
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2495376033
Short name T830
Test name
Test status
Simulation time 562696907 ps
CPU time 21.35 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 216880 kb
Host smart-c062c2f1-13a6-4c35-9f45-078a809a8523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495376033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2495376033
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.247189142
Short name T775
Test name
Test status
Simulation time 27468551 ps
CPU time 0.81 seconds
Started Dec 24 01:56:17 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 206856 kb
Host smart-75303c30-f108-4d3c-9a69-dac334dd238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247189142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.247189142
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tx_async_fifo_reset.3781737884
Short name T14
Test name
Test status
Simulation time 16678044 ps
CPU time 0.79 seconds
Started Dec 24 01:56:09 PM PST 23
Finished Dec 24 01:56:16 PM PST 23
Peak memory 208484 kb
Host smart-7ca2a6cf-46e1-43cb-a663-074d7e579f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781737884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tx_async_fifo_reset.3781737884
Directory /workspace/27.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/27.spi_device_txrx.4268009806
Short name T1691
Test name
Test status
Simulation time 39852943481 ps
CPU time 300 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 02:01:09 PM PST 23
Peak memory 267124 kb
Host smart-07a5c5a3-52a8-4ca8-a0c1-393ecab2b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268009806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_txrx.4268009806
Directory /workspace/27.spi_device_txrx/latest

Test location /workspace/coverage/default/27.spi_device_upload.2912771312
Short name T887
Test name
Test status
Simulation time 599269272 ps
CPU time 6.97 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 224828 kb
Host smart-773676a1-0bdb-48e4-9fe5-fc75136653d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912771312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2912771312
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_abort.3473231296
Short name T947
Test name
Test status
Simulation time 23269532 ps
CPU time 0.74 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:19 PM PST 23
Peak memory 206668 kb
Host smart-62c25c1c-c0e8-4d2f-a701-db7a8f98d420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473231296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_abort.3473231296
Directory /workspace/28.spi_device_abort/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.641357756
Short name T880
Test name
Test status
Simulation time 42387555 ps
CPU time 0.76 seconds
Started Dec 24 01:56:14 PM PST 23
Finished Dec 24 01:56:18 PM PST 23
Peak memory 206424 kb
Host smart-46999a97-f155-4f9b-957e-461d43c97882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641357756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.641357756
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_bit_transfer.524733405
Short name T1780
Test name
Test status
Simulation time 656301258 ps
CPU time 2.48 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 216804 kb
Host smart-9ac25cfc-0c31-499c-93ed-875629396923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524733405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_bit_transfer.524733405
Directory /workspace/28.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/28.spi_device_byte_transfer.1101379720
Short name T581
Test name
Test status
Simulation time 207461427 ps
CPU time 3.2 seconds
Started Dec 24 01:56:14 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 216824 kb
Host smart-2d42073d-06cd-42b5-ae8a-3caffce647e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101379720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_byte_transfer.1101379720
Directory /workspace/28.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.651659623
Short name T1052
Test name
Test status
Simulation time 2677924051 ps
CPU time 9.88 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 241512 kb
Host smart-efa9d555-8c9c-454c-838d-ac80304e25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651659623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.651659623
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.119942718
Short name T41
Test name
Test status
Simulation time 26579778 ps
CPU time 0.81 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 01:56:09 PM PST 23
Peak memory 206464 kb
Host smart-d935f763-e1f4-4033-babc-61d404ab1f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119942718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.119942718
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_dummy_item_extra_dly.3743369159
Short name T902
Test name
Test status
Simulation time 349187763633 ps
CPU time 266.75 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 02:00:49 PM PST 23
Peak memory 249796 kb
Host smart-8dd802a9-2c77-4c6e-bd28-2e764620e1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743369159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_dummy_item_extra_dly.3743369159
Directory /workspace/28.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/28.spi_device_extreme_fifo_size.2324622527
Short name T1726
Test name
Test status
Simulation time 53267450657 ps
CPU time 2644.2 seconds
Started Dec 24 01:56:12 PM PST 23
Finished Dec 24 02:40:21 PM PST 23
Peak memory 220116 kb
Host smart-23ca1119-0f8a-4dce-84f9-44b9b5a7e3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324622527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_extreme_fifo_size.2324622527
Directory /workspace/28.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/28.spi_device_fifo_full.2965744418
Short name T1449
Test name
Test status
Simulation time 90534415148 ps
CPU time 1281.02 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 02:17:45 PM PST 23
Peak memory 258868 kb
Host smart-16bdbec2-4323-4e83-8f53-746c8a11b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965744418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_full.2965744418
Directory /workspace/28.spi_device_fifo_full/latest

Test location /workspace/coverage/default/28.spi_device_fifo_underflow_overflow.2709224599
Short name T15
Test name
Test status
Simulation time 347544991166 ps
CPU time 1018.6 seconds
Started Dec 24 01:56:08 PM PST 23
Finished Dec 24 02:13:10 PM PST 23
Peak memory 803660 kb
Host smart-b4b361dc-9fb1-4f73-b0be-f5dbcb7037ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709224599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_underflow_overf
low.2709224599
Directory /workspace/28.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2439411189
Short name T968
Test name
Test status
Simulation time 7963601928 ps
CPU time 88.6 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 01:57:57 PM PST 23
Peak memory 255412 kb
Host smart-967104f2-6d40-45ad-b3dd-02475e9436e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439411189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2439411189
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1213758774
Short name T1767
Test name
Test status
Simulation time 59269497859 ps
CPU time 44.85 seconds
Started Dec 24 01:56:28 PM PST 23
Finished Dec 24 01:57:16 PM PST 23
Peak memory 251040 kb
Host smart-6451aeab-ebe6-48b9-8b34-4ab802ecec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213758774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1213758774
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3946939215
Short name T177
Test name
Test status
Simulation time 18871221594 ps
CPU time 90.76 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:57:56 PM PST 23
Peak memory 249728 kb
Host smart-10a4b037-f79b-4a9a-9376-9b1b2beecd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946939215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3946939215
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.915775079
Short name T1028
Test name
Test status
Simulation time 62330869 ps
CPU time 2.87 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 218448 kb
Host smart-070945bb-92a5-473c-a433-99d513a9fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915775079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.915775079
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intr.3373207605
Short name T474
Test name
Test status
Simulation time 1275210460 ps
CPU time 5.42 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 218136 kb
Host smart-96da84e6-c76d-4e6b-a24d-01fe68f535df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373207605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intr.3373207605
Directory /workspace/28.spi_device_intr/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1518598995
Short name T1108
Test name
Test status
Simulation time 9566764546 ps
CPU time 25.4 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 249624 kb
Host smart-8e3fa22c-d193-48f6-86f3-16a9f3c87ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518598995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1518598995
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2657619358
Short name T899
Test name
Test status
Simulation time 44573183566 ps
CPU time 29.6 seconds
Started Dec 24 01:56:13 PM PST 23
Finished Dec 24 01:56:47 PM PST 23
Peak memory 257052 kb
Host smart-f24770f9-19d5-4a50-9641-a3c47a0ebe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657619358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2657619358
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.77767052
Short name T254
Test name
Test status
Simulation time 9555079741 ps
CPU time 30.69 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 01:56:59 PM PST 23
Peak memory 231036 kb
Host smart-050ecee6-182c-43c0-baf7-d29213d01db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77767052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.77767052
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_perf.1946909177
Short name T1313
Test name
Test status
Simulation time 26844993534 ps
CPU time 159.18 seconds
Started Dec 24 01:56:14 PM PST 23
Finished Dec 24 01:58:57 PM PST 23
Peak memory 266960 kb
Host smart-a45daba4-9681-467b-b0cd-ff30775a1573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946909177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_perf.1946909177
Directory /workspace/28.spi_device_perf/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3429934124
Short name T976
Test name
Test status
Simulation time 2161583142 ps
CPU time 6.88 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:56:36 PM PST 23
Peak memory 220844 kb
Host smart-3fc182b8-20cd-4b3f-a7d5-b3591638bf8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3429934124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3429934124
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_rx_async_fifo_reset.1036067387
Short name T1604
Test name
Test status
Simulation time 59930207 ps
CPU time 1.03 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:20 PM PST 23
Peak memory 208512 kb
Host smart-4cb28aa6-34ae-4ba7-9792-080ad9794c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036067387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_async_fifo_reset.1036067387
Directory /workspace/28.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_rx_timeout.3778217797
Short name T598
Test name
Test status
Simulation time 1518867528 ps
CPU time 6.16 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:24 PM PST 23
Peak memory 216740 kb
Host smart-7ab707e2-b46b-40ad-b74e-63d5bdddd681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778217797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_timeout.3778217797
Directory /workspace/28.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/28.spi_device_smoke.563276822
Short name T1777
Test name
Test status
Simulation time 165936069 ps
CPU time 1.11 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 01:56:28 PM PST 23
Peak memory 216492 kb
Host smart-b2adec77-1037-4f3f-bbbc-c2ff1faca9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563276822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_smoke.563276822
Directory /workspace/28.spi_device_smoke/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2720234104
Short name T572
Test name
Test status
Simulation time 419758785 ps
CPU time 7.34 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 01:56:33 PM PST 23
Peak memory 217048 kb
Host smart-8c7aa6ca-5e0b-4e18-9443-32846142ed58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720234104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2720234104
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1902039362
Short name T897
Test name
Test status
Simulation time 1355862830 ps
CPU time 4.58 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:29 PM PST 23
Peak memory 216844 kb
Host smart-9869d81f-6fc0-4c5d-9989-8b14e5a7dfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902039362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1902039362
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2921743617
Short name T823
Test name
Test status
Simulation time 720015132 ps
CPU time 3.3 seconds
Started Dec 24 01:56:10 PM PST 23
Finished Dec 24 01:56:19 PM PST 23
Peak memory 216896 kb
Host smart-8480db64-163e-4ff1-824f-1944f963e994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921743617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2921743617
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2457172071
Short name T1029
Test name
Test status
Simulation time 94251646 ps
CPU time 0.78 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:56:26 PM PST 23
Peak memory 206956 kb
Host smart-4543bbe4-cd0d-461d-81ee-1975d0149bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457172071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2457172071
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tx_async_fifo_reset.600888445
Short name T1333
Test name
Test status
Simulation time 161767473 ps
CPU time 0.76 seconds
Started Dec 24 01:56:15 PM PST 23
Finished Dec 24 01:56:20 PM PST 23
Peak memory 208392 kb
Host smart-f12e1b80-df2b-48b1-afd7-597e880140f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600888445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tx_async_fifo_reset.600888445
Directory /workspace/28.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/28.spi_device_txrx.2081508355
Short name T1143
Test name
Test status
Simulation time 52790179028 ps
CPU time 169.34 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 01:59:17 PM PST 23
Peak memory 285956 kb
Host smart-843dc4ab-af39-4c14-921e-16296e9c3db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081508355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_txrx.2081508355
Directory /workspace/28.spi_device_txrx/latest

Test location /workspace/coverage/default/28.spi_device_upload.2859663239
Short name T958
Test name
Test status
Simulation time 4309019481 ps
CPU time 10.11 seconds
Started Dec 24 01:56:14 PM PST 23
Finished Dec 24 01:56:28 PM PST 23
Peak memory 225196 kb
Host smart-fe4f6c46-bf34-4c8b-9357-b96b49c1c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859663239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2859663239
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_abort.2337487228
Short name T578
Test name
Test status
Simulation time 29463344 ps
CPU time 0.74 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 01:56:28 PM PST 23
Peak memory 206596 kb
Host smart-4a05ad25-db52-4689-95ac-8e841fbecbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337487228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_abort.2337487228
Directory /workspace/29.spi_device_abort/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.630113846
Short name T1655
Test name
Test status
Simulation time 82701368 ps
CPU time 0.72 seconds
Started Dec 24 01:56:20 PM PST 23
Finished Dec 24 01:56:24 PM PST 23
Peak memory 206472 kb
Host smart-d61cdc0c-35db-4744-a033-12ddf5927d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630113846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.630113846
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_bit_transfer.3544141648
Short name T493
Test name
Test status
Simulation time 713514274 ps
CPU time 3.18 seconds
Started Dec 24 01:56:18 PM PST 23
Finished Dec 24 01:56:24 PM PST 23
Peak memory 216800 kb
Host smart-8f9c5045-9a6b-400f-8a9d-1a7bd4f2a176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544141648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_bit_transfer.3544141648
Directory /workspace/29.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/29.spi_device_byte_transfer.2618525951
Short name T975
Test name
Test status
Simulation time 795175930 ps
CPU time 2.98 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:14 PM PST 23
Peak memory 216864 kb
Host smart-77472bcc-f77d-4f05-9769-0c0e64e173f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618525951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_byte_transfer.2618525951
Directory /workspace/29.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1264546030
Short name T1512
Test name
Test status
Simulation time 3373707134 ps
CPU time 6.05 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 01:56:34 PM PST 23
Peak memory 221544 kb
Host smart-5dfb72e3-a34e-47af-b986-4cc4d65372a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264546030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1264546030
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1676756317
Short name T695
Test name
Test status
Simulation time 36422822 ps
CPU time 0.8 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 01:56:25 PM PST 23
Peak memory 207576 kb
Host smart-cd24138d-4661-46bb-b5d5-0bdf795ba73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676756317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1676756317
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_dummy_item_extra_dly.553033956
Short name T1737
Test name
Test status
Simulation time 104123700381 ps
CPU time 410.52 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 02:03:14 PM PST 23
Peak memory 271668 kb
Host smart-82eb6568-4568-4481-8076-4462e0654104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553033956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_dummy_item_extra_dly.553033956
Directory /workspace/29.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/29.spi_device_extreme_fifo_size.2528763266
Short name T543
Test name
Test status
Simulation time 672407314752 ps
CPU time 1027.02 seconds
Started Dec 24 01:56:22 PM PST 23
Finished Dec 24 02:13:32 PM PST 23
Peak memory 220412 kb
Host smart-17a9f719-e0f5-469b-b1d7-6c39b143dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528763266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_extreme_fifo_size.2528763266
Directory /workspace/29.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/29.spi_device_fifo_full.2428464074
Short name T1361
Test name
Test status
Simulation time 185271075061 ps
CPU time 2263.81 seconds
Started Dec 24 01:56:05 PM PST 23
Finished Dec 24 02:33:53 PM PST 23
Peak memory 245636 kb
Host smart-09142b76-fbec-47a8-9035-60b9449838df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428464074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_full.2428464074
Directory /workspace/29.spi_device_fifo_full/latest

Test location /workspace/coverage/default/29.spi_device_fifo_underflow_overflow.1468220367
Short name T599
Test name
Test status
Simulation time 70259579586 ps
CPU time 620.53 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 02:06:50 PM PST 23
Peak memory 621852 kb
Host smart-808ad857-735d-455b-800a-a72ef7dbde94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468220367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_underflow_overf
low.1468220367
Directory /workspace/29.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1101806790
Short name T1376
Test name
Test status
Simulation time 7370499758 ps
CPU time 78.74 seconds
Started Dec 24 01:56:19 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 267132 kb
Host smart-34d3b547-4b60-4a09-a536-5fac617f24e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101806790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1101806790
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1002878954
Short name T197
Test name
Test status
Simulation time 366344411444 ps
CPU time 605.26 seconds
Started Dec 24 01:56:28 PM PST 23
Finished Dec 24 02:06:36 PM PST 23
Peak memory 257164 kb
Host smart-6c068eac-4d9a-4af0-891c-bd0f62b9d6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002878954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1002878954
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.670464338
Short name T790
Test name
Test status
Simulation time 10406314912 ps
CPU time 64.18 seconds
Started Dec 24 01:57:58 PM PST 23
Finished Dec 24 01:59:03 PM PST 23
Peak memory 257540 kb
Host smart-f99fbb30-6ce6-4aad-bbf7-f46db0c3ab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670464338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.670464338
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4075536832
Short name T1075
Test name
Test status
Simulation time 1859185314 ps
CPU time 11.12 seconds
Started Dec 24 01:56:28 PM PST 23
Finished Dec 24 01:56:42 PM PST 23
Peak memory 249700 kb
Host smart-72027d15-16b8-4a8e-a110-8e3d0978cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075536832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4075536832
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.434639056
Short name T1308
Test name
Test status
Simulation time 620386346 ps
CPU time 4.37 seconds
Started Dec 24 01:56:28 PM PST 23
Finished Dec 24 01:56:35 PM PST 23
Peak memory 241420 kb
Host smart-af264cd2-3158-4bbe-aadb-dd4397f030d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434639056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.434639056
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intr.1345072765
Short name T37
Test name
Test status
Simulation time 64743659484 ps
CPU time 52.85 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:57:17 PM PST 23
Peak memory 237408 kb
Host smart-0c9faeaf-65f5-4107-9907-39dcafd9472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345072765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intr.1345072765
Directory /workspace/29.spi_device_intr/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2902398342
Short name T1150
Test name
Test status
Simulation time 21774281639 ps
CPU time 30.71 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:57:00 PM PST 23
Peak memory 229720 kb
Host smart-80f52ee4-5b43-4bb4-a7a5-6a7c765d318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902398342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2902398342
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3646391092
Short name T292
Test name
Test status
Simulation time 15523280927 ps
CPU time 10.03 seconds
Started Dec 24 01:58:14 PM PST 23
Finished Dec 24 01:58:26 PM PST 23
Peak memory 234292 kb
Host smart-aab891c6-0a99-4802-b405-59ae774ba1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646391092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3646391092
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4198059018
Short name T1703
Test name
Test status
Simulation time 605353621 ps
CPU time 2.86 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 01:56:30 PM PST 23
Peak memory 224764 kb
Host smart-e3174e87-58ac-4b23-ab8b-0e5313593692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198059018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4198059018
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_perf.699699120
Short name T471
Test name
Test status
Simulation time 68184952606 ps
CPU time 820.24 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 02:10:06 PM PST 23
Peak memory 249356 kb
Host smart-b4c81f32-f4fa-49e3-a6ed-9c3c83ea8a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699699120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_perf.699699120
Directory /workspace/29.spi_device_perf/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1482736019
Short name T1274
Test name
Test status
Simulation time 2775500126 ps
CPU time 6.36 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 01:58:53 PM PST 23
Peak memory 220960 kb
Host smart-05b754b8-cec4-4f13-aa5b-9220ea3aafe2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1482736019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1482736019
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_rx_async_fifo_reset.1466584541
Short name T1065
Test name
Test status
Simulation time 25217876 ps
CPU time 0.84 seconds
Started Dec 24 01:56:24 PM PST 23
Finished Dec 24 01:56:27 PM PST 23
Peak memory 208364 kb
Host smart-d4e6d0ef-70f2-496e-97fc-68e747c9d2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466584541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_async_fifo_reset.1466584541
Directory /workspace/29.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_rx_timeout.1204823446
Short name T1718
Test name
Test status
Simulation time 947607078 ps
CPU time 6.81 seconds
Started Dec 24 01:56:21 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 216716 kb
Host smart-ef626853-6a28-4885-bc2b-b4dae3e69cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204823446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_timeout.1204823446
Directory /workspace/29.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/29.spi_device_smoke.766868632
Short name T1483
Test name
Test status
Simulation time 541927768 ps
CPU time 1.23 seconds
Started Dec 24 01:56:14 PM PST 23
Finished Dec 24 01:56:19 PM PST 23
Peak memory 216796 kb
Host smart-65b16385-309f-497e-900b-a32c5e5761b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766868632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_smoke.766868632
Directory /workspace/29.spi_device_smoke/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.163914635
Short name T340
Test name
Test status
Simulation time 133942893656 ps
CPU time 778.02 seconds
Started Dec 24 01:57:57 PM PST 23
Finished Dec 24 02:10:57 PM PST 23
Peak memory 354644 kb
Host smart-e899cd87-6a29-4163-92f6-b89d4c6bf46c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163914635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.163914635
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3829559836
Short name T1417
Test name
Test status
Simulation time 2610894315 ps
CPU time 32.11 seconds
Started Dec 24 01:56:16 PM PST 23
Finished Dec 24 01:56:51 PM PST 23
Peak memory 221032 kb
Host smart-0fb6aa1a-e16b-48ad-9399-dd5f8c877110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829559836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3829559836
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.508686975
Short name T666
Test name
Test status
Simulation time 1009341417 ps
CPU time 3.85 seconds
Started Dec 24 01:56:07 PM PST 23
Finished Dec 24 01:56:15 PM PST 23
Peak memory 216892 kb
Host smart-fe11296a-aa1f-46f5-9f7c-431ae03508c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508686975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.508686975
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2119837021
Short name T1432
Test name
Test status
Simulation time 171705620 ps
CPU time 7.45 seconds
Started Dec 24 01:56:33 PM PST 23
Finished Dec 24 01:56:42 PM PST 23
Peak memory 216708 kb
Host smart-37d46ff8-537f-4bbb-967f-c8d47552ec29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119837021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2119837021
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1699712321
Short name T570
Test name
Test status
Simulation time 378102141 ps
CPU time 0.97 seconds
Started Dec 24 01:58:43 PM PST 23
Finished Dec 24 01:58:47 PM PST 23
Peak memory 206672 kb
Host smart-4e1f67f4-0e9f-42c0-8b5c-bc75d19f5b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699712321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1699712321
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tx_async_fifo_reset.2961752959
Short name T723
Test name
Test status
Simulation time 30919239 ps
CPU time 0.76 seconds
Started Dec 24 01:56:34 PM PST 23
Finished Dec 24 01:56:36 PM PST 23
Peak memory 208372 kb
Host smart-53acb05b-821f-44ab-9249-36b33f8ba749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961752959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tx_async_fifo_reset.2961752959
Directory /workspace/29.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/29.spi_device_txrx.813403323
Short name T477
Test name
Test status
Simulation time 156947154111 ps
CPU time 979.41 seconds
Started Dec 24 01:56:23 PM PST 23
Finished Dec 24 02:12:45 PM PST 23
Peak memory 241900 kb
Host smart-b9951a00-0e36-4d2b-83d0-13f1c67c33e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813403323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_txrx.813403323
Directory /workspace/29.spi_device_txrx/latest

Test location /workspace/coverage/default/29.spi_device_upload.3778040958
Short name T1705
Test name
Test status
Simulation time 338320730 ps
CPU time 6.17 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 01:56:36 PM PST 23
Peak memory 237012 kb
Host smart-73701d5c-2368-4adf-8c93-5cacec9c2765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778040958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3778040958
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_abort.3010986286
Short name T619
Test name
Test status
Simulation time 52781379 ps
CPU time 0.73 seconds
Started Dec 24 01:54:11 PM PST 23
Finished Dec 24 01:54:19 PM PST 23
Peak memory 206560 kb
Host smart-d7e7135f-9d20-4c98-bfaa-fdbfbba0b16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010986286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_abort.3010986286
Directory /workspace/3.spi_device_abort/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.727429060
Short name T1246
Test name
Test status
Simulation time 19964005 ps
CPU time 0.71 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 206584 kb
Host smart-3d7c6ace-f21f-412a-b549-77b7fe235986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727429060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.727429060
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_bit_transfer.1168809119
Short name T1520
Test name
Test status
Simulation time 108201427 ps
CPU time 2.16 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:54:17 PM PST 23
Peak memory 216940 kb
Host smart-b79319f2-91ae-404d-9532-7465e356edbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168809119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_bit_transfer.1168809119
Directory /workspace/3.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/3.spi_device_byte_transfer.2138598630
Short name T490
Test name
Test status
Simulation time 1182056486 ps
CPU time 2.64 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:14 PM PST 23
Peak memory 216704 kb
Host smart-9d58ca25-d943-406e-810a-17505d873012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138598630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_byte_transfer.2138598630
Directory /workspace/3.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1262360683
Short name T1142
Test name
Test status
Simulation time 48270235 ps
CPU time 3.2 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:54:23 PM PST 23
Peak memory 238296 kb
Host smart-6d650349-c5f7-4517-ab52-96fe3d4f50ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262360683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1262360683
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4072363609
Short name T1092
Test name
Test status
Simulation time 31206554 ps
CPU time 0.79 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:13 PM PST 23
Peak memory 206592 kb
Host smart-8bff6d29-638b-457f-a4da-96a0a4120ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072363609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4072363609
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_dummy_item_extra_dly.821661955
Short name T1322
Test name
Test status
Simulation time 153524697056 ps
CPU time 428.29 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 02:01:23 PM PST 23
Peak memory 283912 kb
Host smart-b5b10f82-c05c-4247-b5d9-414ce711790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821661955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_dummy_item_extra_dly.821661955
Directory /workspace/3.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/3.spi_device_extreme_fifo_size.4258809931
Short name T54
Test name
Test status
Simulation time 213424677425 ps
CPU time 2652.09 seconds
Started Dec 24 01:54:06 PM PST 23
Finished Dec 24 02:38:22 PM PST 23
Peak memory 218008 kb
Host smart-1d8c1504-1399-49bb-8331-08065f2f8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258809931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_extreme_fifo_size.4258809931
Directory /workspace/3.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/3.spi_device_fifo_full.2680702763
Short name T514
Test name
Test status
Simulation time 44884470603 ps
CPU time 226.67 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:58:01 PM PST 23
Peak memory 282176 kb
Host smart-fb65233d-9309-4846-a6bb-69f8ac6c158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680702763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_full.2680702763
Directory /workspace/3.spi_device_fifo_full/latest

Test location /workspace/coverage/default/3.spi_device_fifo_underflow_overflow.4118431908
Short name T1539
Test name
Test status
Simulation time 42020498577 ps
CPU time 125.65 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:56:21 PM PST 23
Peak memory 309084 kb
Host smart-f81c3544-1156-4978-a985-278e1dafd9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118431908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_underflow_overfl
ow.4118431908
Directory /workspace/3.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1850039341
Short name T1323
Test name
Test status
Simulation time 6161883436 ps
CPU time 31.19 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:54:51 PM PST 23
Peak memory 241444 kb
Host smart-e392204b-fcd9-4f6a-adf3-99ae955d471a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850039341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1850039341
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1003043943
Short name T1168
Test name
Test status
Simulation time 76285889161 ps
CPU time 150.55 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 249752 kb
Host smart-2332b9eb-60dc-42a2-bab9-00ea6fd2daae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003043943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1003043943
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.743481949
Short name T350
Test name
Test status
Simulation time 2991892453 ps
CPU time 19.6 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:41 PM PST 23
Peak memory 233472 kb
Host smart-8d35bb88-7ff1-420c-b588-a2bdc5e780ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743481949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.743481949
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4105733183
Short name T23
Test name
Test status
Simulation time 3067019124 ps
CPU time 10.49 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 221676 kb
Host smart-859154de-54be-4078-b7a7-0de83401cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105733183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4105733183
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.801818210
Short name T1382
Test name
Test status
Simulation time 386999404 ps
CPU time 3.44 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 218360 kb
Host smart-02a0afc0-0d77-4c5c-9dad-8e600e3dc4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801818210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.801818210
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2809533516
Short name T827
Test name
Test status
Simulation time 31557444 ps
CPU time 1.02 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 218816 kb
Host smart-432c1eb5-2c9e-4615-8f6f-7abf6914a37e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809533516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2809533516
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1368601133
Short name T1140
Test name
Test status
Simulation time 19653183085 ps
CPU time 16.61 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:36 PM PST 23
Peak memory 240908 kb
Host smart-64b02647-9e0b-4d40-9fe7-162e71ea104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368601133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1368601133
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1936026224
Short name T1127
Test name
Test status
Simulation time 3306674896 ps
CPU time 6.84 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:54:29 PM PST 23
Peak memory 241420 kb
Host smart-f3d16efe-c622-4d4b-a727-b805ed113c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936026224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1936026224
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_perf.2096983163
Short name T826
Test name
Test status
Simulation time 7035041272 ps
CPU time 178.02 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:57:12 PM PST 23
Peak memory 274312 kb
Host smart-f4fa4d13-f12b-42c4-b80f-4d3ae67bd17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096983163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_perf.2096983163
Directory /workspace/3.spi_device_perf/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.4231723497
Short name T1596
Test name
Test status
Simulation time 26328141 ps
CPU time 0.78 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 216624 kb
Host smart-7b9c0e3a-4f46-4d63-8f2e-5659f0cb041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231723497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.4231723497
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3773493412
Short name T1635
Test name
Test status
Simulation time 6069294535 ps
CPU time 7.16 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 237260 kb
Host smart-16b27bc1-8503-4126-a455-e69233200dc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3773493412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3773493412
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_rx_async_fifo_reset.2813702552
Short name T1317
Test name
Test status
Simulation time 68585603 ps
CPU time 0.86 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 208572 kb
Host smart-cf260dd5-5227-480a-bfb7-aa4f4de294eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813702552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_async_fifo_reset.2813702552
Directory /workspace/3.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_rx_timeout.1574798027
Short name T1524
Test name
Test status
Simulation time 3268328245 ps
CPU time 6.61 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:18 PM PST 23
Peak memory 216776 kb
Host smart-4078ccf2-9a08-4e1b-96cb-e9cdcb734b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574798027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_timeout.1574798027
Directory /workspace/3.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.524266207
Short name T93
Test name
Test status
Simulation time 270538615 ps
CPU time 1.09 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:54:23 PM PST 23
Peak memory 235936 kb
Host smart-6a896d10-c1a8-43e1-86cb-83a88087c4eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524266207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.524266207
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_smoke.3627082
Short name T473
Test name
Test status
Simulation time 86264292 ps
CPU time 1.23 seconds
Started Dec 24 01:54:06 PM PST 23
Finished Dec 24 01:54:09 PM PST 23
Peak memory 216860 kb
Host smart-a01443ec-8e8b-4e2d-9f12-9280d8bdf2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_smoke.3627082
Directory /workspace/3.spi_device_smoke/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2167136675
Short name T786
Test name
Test status
Simulation time 56776677279 ps
CPU time 96.77 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:55:50 PM PST 23
Peak memory 217120 kb
Host smart-e8519452-6822-481d-bc17-4bd76f86c6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167136675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2167136675
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.751473863
Short name T1533
Test name
Test status
Simulation time 1032306527 ps
CPU time 6.64 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 216760 kb
Host smart-febbf711-e9c4-43a4-a72e-3ab067f06898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751473863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.751473863
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.313707001
Short name T1010
Test name
Test status
Simulation time 51149019 ps
CPU time 1.05 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:21 PM PST 23
Peak memory 208008 kb
Host smart-a93ca817-a6b9-4f40-a3b9-e7960a2f9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313707001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.313707001
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1487692558
Short name T702
Test name
Test status
Simulation time 296136736 ps
CPU time 0.88 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:54:16 PM PST 23
Peak memory 206908 kb
Host smart-5723a5a3-166c-4df6-9349-3bc76d2db93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487692558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1487692558
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tx_async_fifo_reset.744725300
Short name T1324
Test name
Test status
Simulation time 29276782 ps
CPU time 0.79 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:54:16 PM PST 23
Peak memory 208488 kb
Host smart-949c2e86-0a39-4b19-8fb1-fc36d54bdd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744725300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tx_async_fifo_reset.744725300
Directory /workspace/3.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/3.spi_device_txrx.3749102444
Short name T722
Test name
Test status
Simulation time 19479226713 ps
CPU time 365.32 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 02:00:20 PM PST 23
Peak memory 249424 kb
Host smart-80cc8eb8-d60c-4008-8bc2-676b7bfde13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749102444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_txrx.3749102444
Directory /workspace/3.spi_device_txrx/latest

Test location /workspace/coverage/default/3.spi_device_upload.4079859848
Short name T244
Test name
Test status
Simulation time 4052924875 ps
CPU time 6.21 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:54:26 PM PST 23
Peak memory 218580 kb
Host smart-19f4d4be-1782-427c-960a-9fcfd8b6f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079859848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4079859848
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_abort.2882538788
Short name T510
Test name
Test status
Simulation time 17428301 ps
CPU time 0.75 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 206680 kb
Host smart-02371eef-aff4-4962-883b-62170437883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882538788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_abort.2882538788
Directory /workspace/30.spi_device_abort/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.846861590
Short name T1753
Test name
Test status
Simulation time 28936525 ps
CPU time 0.72 seconds
Started Dec 24 01:56:36 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 206480 kb
Host smart-0ee6b15e-188a-4f9a-bf82-f9a7370706e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846861590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.846861590
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_byte_transfer.1753884348
Short name T1676
Test name
Test status
Simulation time 220696304 ps
CPU time 2.66 seconds
Started Dec 24 01:56:37 PM PST 23
Finished Dec 24 01:56:45 PM PST 23
Peak memory 216788 kb
Host smart-9dd7a26f-9dad-4459-9e3b-aaf2a243773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753884348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_byte_transfer.1753884348
Directory /workspace/30.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.70662120
Short name T1033
Test name
Test status
Simulation time 563672929 ps
CPU time 4 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:47 PM PST 23
Peak memory 219300 kb
Host smart-662047e6-8ccb-40a3-a8c5-d82bc21f96a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70662120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.70662120
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3426521757
Short name T1723
Test name
Test status
Simulation time 36632389 ps
CPU time 0.77 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 207572 kb
Host smart-97c86e99-20f8-4163-a76e-d2023f29eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426521757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3426521757
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_dummy_item_extra_dly.2274820656
Short name T1654
Test name
Test status
Simulation time 46759127670 ps
CPU time 1227.95 seconds
Started Dec 24 01:56:44 PM PST 23
Finished Dec 24 02:17:18 PM PST 23
Peak memory 249824 kb
Host smart-69f60982-e846-4356-b3a8-69e86fed0347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274820656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_dummy_item_extra_dly.2274820656
Directory /workspace/30.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/30.spi_device_extreme_fifo_size.472225305
Short name T1069
Test name
Test status
Simulation time 96089676509 ps
CPU time 1617.75 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 02:23:42 PM PST 23
Peak memory 221504 kb
Host smart-d8d5c1c4-ac15-4b44-84af-c5bed58aa47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472225305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_extreme_fifo_size.472225305
Directory /workspace/30.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/30.spi_device_fifo_full.1522522484
Short name T1195
Test name
Test status
Simulation time 297855204471 ps
CPU time 758.8 seconds
Started Dec 24 01:56:25 PM PST 23
Finished Dec 24 02:09:08 PM PST 23
Peak memory 269272 kb
Host smart-2b8ec1ab-348a-4dc2-83d3-14ffe9e038d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522522484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_full.1522522484
Directory /workspace/30.spi_device_fifo_full/latest

Test location /workspace/coverage/default/30.spi_device_fifo_underflow_overflow.913039043
Short name T1583
Test name
Test status
Simulation time 7321343401 ps
CPU time 48.76 seconds
Started Dec 24 01:56:42 PM PST 23
Finished Dec 24 01:57:37 PM PST 23
Peak memory 265768 kb
Host smart-250c835d-a8a9-4942-8049-ae0add196800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913039043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_underflow_overfl
ow.913039043
Directory /workspace/30.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2910608700
Short name T99
Test name
Test status
Simulation time 57891884569 ps
CPU time 111.06 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:58:34 PM PST 23
Peak memory 242868 kb
Host smart-d101b6ea-804d-4363-88fc-67194a698e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910608700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2910608700
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.876417350
Short name T212
Test name
Test status
Simulation time 22614060240 ps
CPU time 76.89 seconds
Started Dec 24 01:56:43 PM PST 23
Finished Dec 24 01:58:06 PM PST 23
Peak memory 257932 kb
Host smart-c97dc3f6-e2db-4ec5-8262-3d7f3b223aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876417350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.876417350
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3773365246
Short name T1757
Test name
Test status
Simulation time 1181527363 ps
CPU time 5.27 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 219472 kb
Host smart-f3095432-b66a-445c-8d87-bbcbe4b478ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773365246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3773365246
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3249368111
Short name T1061
Test name
Test status
Simulation time 736172388 ps
CPU time 5.15 seconds
Started Dec 24 01:56:44 PM PST 23
Finished Dec 24 01:56:55 PM PST 23
Peak memory 224860 kb
Host smart-4fb21494-5eb4-4103-99e0-1159ed4d2bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249368111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3249368111
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.77836538
Short name T804
Test name
Test status
Simulation time 8113422484 ps
CPU time 15.19 seconds
Started Dec 24 01:56:37 PM PST 23
Finished Dec 24 01:56:57 PM PST 23
Peak memory 238444 kb
Host smart-023496fc-f932-4d12-b339-bac84bfd96b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77836538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.77836538
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1114653242
Short name T835
Test name
Test status
Simulation time 5077754990 ps
CPU time 19.7 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 01:57:02 PM PST 23
Peak memory 230552 kb
Host smart-eeb1603e-942e-457d-a65c-198b9ad04bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114653242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1114653242
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_perf.4258319061
Short name T1169
Test name
Test status
Simulation time 14839316854 ps
CPU time 393.15 seconds
Started Dec 24 01:56:42 PM PST 23
Finished Dec 24 02:03:21 PM PST 23
Peak memory 306252 kb
Host smart-e528564f-9949-4762-8f9b-ac823c50782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258319061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_perf.4258319061
Directory /workspace/30.spi_device_perf/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.329483711
Short name T1628
Test name
Test status
Simulation time 2806083680 ps
CPU time 5.98 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 219008 kb
Host smart-30a5872b-2060-4c0d-b3dd-e4f5ce222237
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=329483711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.329483711
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_rx_async_fifo_reset.2889205456
Short name T1116
Test name
Test status
Simulation time 49017244 ps
CPU time 0.86 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:56:47 PM PST 23
Peak memory 208492 kb
Host smart-fc33610b-bf08-41ac-b9f8-0ba9cf2d4805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889205456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_async_fifo_reset.2889205456
Directory /workspace/30.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_rx_timeout.3579291732
Short name T689
Test name
Test status
Simulation time 1149646254 ps
CPU time 5.7 seconds
Started Dec 24 01:56:47 PM PST 23
Finished Dec 24 01:56:57 PM PST 23
Peak memory 216836 kb
Host smart-f716f77a-c715-469e-87bf-e1c9b1d7d7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579291732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_timeout.3579291732
Directory /workspace/30.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/30.spi_device_smoke.1358963122
Short name T624
Test name
Test status
Simulation time 24175088 ps
CPU time 0.93 seconds
Started Dec 24 01:57:58 PM PST 23
Finished Dec 24 01:58:00 PM PST 23
Peak memory 207844 kb
Host smart-e4cf1bb6-ccda-4190-8bce-8db1d37b8796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358963122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_smoke.1358963122
Directory /workspace/30.spi_device_smoke/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3217678501
Short name T1694
Test name
Test status
Simulation time 1752508691 ps
CPU time 9.73 seconds
Started Dec 24 01:56:45 PM PST 23
Finished Dec 24 01:57:00 PM PST 23
Peak memory 216788 kb
Host smart-0f636b58-921c-4638-9fb3-a98e556e7dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217678501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3217678501
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1314748754
Short name T1644
Test name
Test status
Simulation time 795043754 ps
CPU time 1.84 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 208044 kb
Host smart-1330cd79-d417-4133-bd50-1e981517799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314748754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1314748754
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1506629418
Short name T1675
Test name
Test status
Simulation time 154156322 ps
CPU time 1.77 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:45 PM PST 23
Peak memory 216784 kb
Host smart-5c1076ef-8e84-4524-84fa-2d3dda7cf6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506629418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1506629418
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1682340953
Short name T1399
Test name
Test status
Simulation time 93296563 ps
CPU time 0.96 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 206932 kb
Host smart-dea5a12b-9c35-4ec6-8190-2e758ecd3b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682340953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1682340953
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tx_async_fifo_reset.1460482720
Short name T556
Test name
Test status
Simulation time 30871790 ps
CPU time 0.79 seconds
Started Dec 24 01:56:43 PM PST 23
Finished Dec 24 01:56:50 PM PST 23
Peak memory 208364 kb
Host smart-c89d9fd4-d069-464c-8d70-ae631e22cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460482720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tx_async_fifo_reset.1460482720
Directory /workspace/30.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/30.spi_device_txrx.3051614997
Short name T1493
Test name
Test status
Simulation time 64545580660 ps
CPU time 277.7 seconds
Started Dec 24 01:56:26 PM PST 23
Finished Dec 24 02:01:07 PM PST 23
Peak memory 255532 kb
Host smart-2a983557-aa0b-42b7-aa42-7729f757dfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051614997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_txrx.3051614997
Directory /workspace/30.spi_device_txrx/latest

Test location /workspace/coverage/default/30.spi_device_upload.149176339
Short name T928
Test name
Test status
Simulation time 7236503828 ps
CPU time 8.2 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 01:56:50 PM PST 23
Peak memory 241456 kb
Host smart-2d6a0e2f-a8dc-42cb-a813-d3aee6c5532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149176339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.149176339
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_abort.1607382438
Short name T1223
Test name
Test status
Simulation time 43715421 ps
CPU time 0.76 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 206584 kb
Host smart-e153888c-214d-444b-8ed7-64878224082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607382438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_abort.1607382438
Directory /workspace/31.spi_device_abort/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4275672121
Short name T1207
Test name
Test status
Simulation time 14253454 ps
CPU time 0.74 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 206408 kb
Host smart-ea410b77-c14b-4875-992c-29abac648e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275672121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4275672121
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_bit_transfer.3170409026
Short name T546
Test name
Test status
Simulation time 1905616835 ps
CPU time 3.48 seconds
Started Dec 24 01:56:53 PM PST 23
Finished Dec 24 01:57:02 PM PST 23
Peak memory 216860 kb
Host smart-148ffd9e-121f-427a-8b47-e16bb0c06122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170409026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_bit_transfer.3170409026
Directory /workspace/31.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/31.spi_device_byte_transfer.3389605709
Short name T1564
Test name
Test status
Simulation time 120321173 ps
CPU time 2.37 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:46 PM PST 23
Peak memory 216916 kb
Host smart-89761f41-6285-48e7-89c6-37b17b3db8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389605709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_byte_transfer.3389605709
Directory /workspace/31.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1610342333
Short name T1776
Test name
Test status
Simulation time 172921767 ps
CPU time 4.52 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 238084 kb
Host smart-3549872b-4ecf-49b4-b7f6-6bb6800552cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610342333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1610342333
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4073964719
Short name T588
Test name
Test status
Simulation time 47450512 ps
CPU time 0.76 seconds
Started Dec 24 01:56:53 PM PST 23
Finished Dec 24 01:57:00 PM PST 23
Peak memory 206496 kb
Host smart-2b653c25-c9f3-418a-83b6-96c0bed16b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073964719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4073964719
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_dummy_item_extra_dly.4164400325
Short name T1341
Test name
Test status
Simulation time 49032811976 ps
CPU time 403.39 seconds
Started Dec 24 01:56:45 PM PST 23
Finished Dec 24 02:03:34 PM PST 23
Peak memory 282428 kb
Host smart-309452d0-b0ec-4725-b136-8c5ee7333351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164400325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_dummy_item_extra_dly.4164400325
Directory /workspace/31.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/31.spi_device_extreme_fifo_size.4234424693
Short name T57
Test name
Test status
Simulation time 212851655276 ps
CPU time 610.08 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 02:06:53 PM PST 23
Peak memory 219044 kb
Host smart-0d971ea5-b720-4c32-93e9-5985d8007ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234424693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_extreme_fifo_size.4234424693
Directory /workspace/31.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/31.spi_device_fifo_full.3165170937
Short name T1684
Test name
Test status
Simulation time 211559093337 ps
CPU time 3034.69 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 02:47:18 PM PST 23
Peak memory 306152 kb
Host smart-c22d7ea4-01e7-4b1e-befd-f9c84ff8e89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165170937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_full.3165170937
Directory /workspace/31.spi_device_fifo_full/latest

Test location /workspace/coverage/default/31.spi_device_fifo_underflow_overflow.3062376533
Short name T687
Test name
Test status
Simulation time 30025520079 ps
CPU time 554.53 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 02:06:01 PM PST 23
Peak memory 507484 kb
Host smart-f92b04be-805b-42db-bdcb-8bdc88a8184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062376533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_underflow_overf
low.3062376533
Directory /workspace/31.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.902689328
Short name T326
Test name
Test status
Simulation time 34686277631 ps
CPU time 106.6 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:58:30 PM PST 23
Peak memory 257800 kb
Host smart-d282011e-55e3-422a-88ab-5d3fd6cdc51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902689328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.902689328
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4030245492
Short name T224
Test name
Test status
Simulation time 236947061486 ps
CPU time 775.85 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 02:09:42 PM PST 23
Peak memory 274428 kb
Host smart-f5e16c59-9b06-4f6d-aa97-951f39c682a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030245492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4030245492
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3250906765
Short name T294
Test name
Test status
Simulation time 212033940938 ps
CPU time 380.8 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 02:03:03 PM PST 23
Peak memory 273356 kb
Host smart-fdf5c623-ac3a-4577-9228-9515996a2807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250906765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3250906765
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3040058864
Short name T1446
Test name
Test status
Simulation time 6897785223 ps
CPU time 23.2 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 239064 kb
Host smart-0494aaa3-3cd0-4a20-9c79-5ab10a1696a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040058864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3040058864
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3736511414
Short name T883
Test name
Test status
Simulation time 266684959 ps
CPU time 4.16 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:47 PM PST 23
Peak memory 225036 kb
Host smart-1be7e005-a7fe-4b78-9f1f-9e3b665c86aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736511414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3736511414
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intr.3321371069
Short name T1562
Test name
Test status
Simulation time 30070631475 ps
CPU time 109.97 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:58:34 PM PST 23
Peak memory 241040 kb
Host smart-fff569b4-c05d-4458-bc5d-db35bba886ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321371069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intr.3321371069
Directory /workspace/31.spi_device_intr/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1444486528
Short name T800
Test name
Test status
Simulation time 62530063896 ps
CPU time 28.37 seconds
Started Dec 24 01:56:53 PM PST 23
Finished Dec 24 01:57:26 PM PST 23
Peak memory 246436 kb
Host smart-a45691a6-d8b9-40d4-94da-c1a4174b845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444486528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1444486528
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3995418767
Short name T302
Test name
Test status
Simulation time 913860449 ps
CPU time 3.72 seconds
Started Dec 24 01:56:54 PM PST 23
Finished Dec 24 01:57:10 PM PST 23
Peak memory 225080 kb
Host smart-12aaf73a-147e-4108-8a7d-8f89e3dc67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995418767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3995418767
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.468347401
Short name T222
Test name
Test status
Simulation time 600228945 ps
CPU time 4.63 seconds
Started Dec 24 01:56:52 PM PST 23
Finished Dec 24 01:57:03 PM PST 23
Peak memory 218188 kb
Host smart-a2b5fd90-f55a-45f1-be7e-781bd3d27685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468347401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.468347401
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_perf.383344524
Short name T630
Test name
Test status
Simulation time 91083540263 ps
CPU time 595.45 seconds
Started Dec 24 01:56:44 PM PST 23
Finished Dec 24 02:06:46 PM PST 23
Peak memory 282452 kb
Host smart-b10a8030-1a1c-4634-9a11-deaf10459519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383344524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_perf.383344524
Directory /workspace/31.spi_device_perf/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1137541193
Short name T590
Test name
Test status
Simulation time 170316964 ps
CPU time 3.78 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:46 PM PST 23
Peak memory 218800 kb
Host smart-ca9dcbae-189a-4183-b5cf-420e91309152
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1137541193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1137541193
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_rx_async_fifo_reset.1649322657
Short name T1062
Test name
Test status
Simulation time 183459686 ps
CPU time 0.92 seconds
Started Dec 24 01:56:46 PM PST 23
Finished Dec 24 01:56:52 PM PST 23
Peak memory 208432 kb
Host smart-2d1b7ede-4df9-4c2a-b890-8ad19655b7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649322657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_async_fifo_reset.1649322657
Directory /workspace/31.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_rx_timeout.341055450
Short name T995
Test name
Test status
Simulation time 3308875764 ps
CPU time 5.84 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 216844 kb
Host smart-3b6692cd-c608-48cd-84cc-fa2002abb9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341055450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_timeout.341055450
Directory /workspace/31.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/31.spi_device_smoke.1694084017
Short name T1095
Test name
Test status
Simulation time 30741321 ps
CPU time 0.99 seconds
Started Dec 24 01:56:42 PM PST 23
Finished Dec 24 01:56:49 PM PST 23
Peak memory 208324 kb
Host smart-68a9b0c6-ba02-4da2-978c-86fee139317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694084017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_smoke.1694084017
Directory /workspace/31.spi_device_smoke/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4208979499
Short name T1472
Test name
Test status
Simulation time 4772806992 ps
CPU time 13.49 seconds
Started Dec 24 01:56:53 PM PST 23
Finished Dec 24 01:57:12 PM PST 23
Peak memory 216880 kb
Host smart-474d6967-dd73-4b84-9144-25b8fb6ed17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208979499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4208979499
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.115370853
Short name T662
Test name
Test status
Simulation time 1920152800 ps
CPU time 9.88 seconds
Started Dec 24 01:56:53 PM PST 23
Finished Dec 24 01:57:08 PM PST 23
Peak memory 216776 kb
Host smart-bef9685c-934b-45f3-939e-e0a5a1b567d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115370853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.115370853
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1811264716
Short name T509
Test name
Test status
Simulation time 66809098 ps
CPU time 1.04 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:56:46 PM PST 23
Peak memory 207964 kb
Host smart-c8e6420b-a7d6-4f30-98b3-0c0b63f78354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811264716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1811264716
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.909971028
Short name T1630
Test name
Test status
Simulation time 26764074 ps
CPU time 0.81 seconds
Started Dec 24 01:56:42 PM PST 23
Finished Dec 24 01:56:49 PM PST 23
Peak memory 206924 kb
Host smart-108bd6d0-a73a-4f42-98b8-ef7c8b732672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909971028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.909971028
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tx_async_fifo_reset.2795723111
Short name T96
Test name
Test status
Simulation time 57220579 ps
CPU time 0.78 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 208488 kb
Host smart-aea79a9a-f9b8-4efb-9f8c-7981413332aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795723111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tx_async_fifo_reset.2795723111
Directory /workspace/31.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/31.spi_device_txrx.1976874081
Short name T1543
Test name
Test status
Simulation time 61419009648 ps
CPU time 185.55 seconds
Started Dec 24 01:56:42 PM PST 23
Finished Dec 24 01:59:53 PM PST 23
Peak memory 251724 kb
Host smart-0750adf2-b517-4cd4-91f3-a42c1f82f23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976874081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_txrx.1976874081
Directory /workspace/31.spi_device_txrx/latest

Test location /workspace/coverage/default/31.spi_device_upload.1894879410
Short name T1215
Test name
Test status
Simulation time 61361228 ps
CPU time 3.06 seconds
Started Dec 24 01:56:42 PM PST 23
Finished Dec 24 01:56:51 PM PST 23
Peak memory 226408 kb
Host smart-fdda7e74-1fa1-45a5-8ed7-86188b026eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894879410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1894879410
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_abort.3407843996
Short name T479
Test name
Test status
Simulation time 16074028 ps
CPU time 0.75 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 206560 kb
Host smart-859a6445-833b-42d1-a502-34376f155cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407843996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_abort.3407843996
Directory /workspace/32.spi_device_abort/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.827982870
Short name T548
Test name
Test status
Simulation time 13849353 ps
CPU time 0.75 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 206516 kb
Host smart-809a9bd4-6074-4ccb-8881-cd5f66061194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827982870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.827982870
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_bit_transfer.187271043
Short name T1020
Test name
Test status
Simulation time 290056837 ps
CPU time 1.9 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:45 PM PST 23
Peak memory 216780 kb
Host smart-573db17c-80a0-412f-8a52-b1f0b12e41b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187271043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_bit_transfer.187271043
Directory /workspace/32.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/32.spi_device_byte_transfer.3836341888
Short name T1122
Test name
Test status
Simulation time 235242636 ps
CPU time 2.88 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:45 PM PST 23
Peak memory 216872 kb
Host smart-c57369b4-8f84-4edf-975f-537ba55ce837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836341888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_byte_transfer.3836341888
Directory /workspace/32.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2934271184
Short name T885
Test name
Test status
Simulation time 436934192 ps
CPU time 2.48 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:56:49 PM PST 23
Peak memory 218260 kb
Host smart-a9516725-f31b-4a47-b0c8-dbac7d0109dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934271184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2934271184
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2881761413
Short name T1078
Test name
Test status
Simulation time 12605465 ps
CPU time 0.8 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 206524 kb
Host smart-dd8a3ce9-56ac-4490-a3e7-6b08ced02d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881761413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2881761413
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_dummy_item_extra_dly.2018621916
Short name T678
Test name
Test status
Simulation time 472955035186 ps
CPU time 949.19 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 02:12:32 PM PST 23
Peak memory 263060 kb
Host smart-952a2151-631c-43be-b54f-0b64ea8ce9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018621916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_dummy_item_extra_dly.2018621916
Directory /workspace/32.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/32.spi_device_extreme_fifo_size.3161895511
Short name T950
Test name
Test status
Simulation time 22159373134 ps
CPU time 70.48 seconds
Started Dec 24 01:56:37 PM PST 23
Finished Dec 24 01:57:53 PM PST 23
Peak memory 232884 kb
Host smart-3426c32f-c357-40c0-a6ef-75fe1f4df3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161895511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_extreme_fifo_size.3161895511
Directory /workspace/32.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/32.spi_device_fifo_full.3645641522
Short name T923
Test name
Test status
Simulation time 45227332163 ps
CPU time 934.24 seconds
Started Dec 24 01:56:45 PM PST 23
Finished Dec 24 02:12:25 PM PST 23
Peak memory 273596 kb
Host smart-e646b282-35c0-47fa-bf06-79b3f658ba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645641522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_full.3645641522
Directory /workspace/32.spi_device_fifo_full/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4023303562
Short name T729
Test name
Test status
Simulation time 9998418383 ps
CPU time 33.07 seconds
Started Dec 24 01:56:43 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 249692 kb
Host smart-4549eb57-e2ad-4e35-8275-4e61a714f81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023303562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4023303562
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4138565149
Short name T1556
Test name
Test status
Simulation time 7977769718 ps
CPU time 39.64 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 241600 kb
Host smart-97c6a44c-ca6d-48e4-84ad-ebd619f0ccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138565149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4138565149
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.522577696
Short name T652
Test name
Test status
Simulation time 5594746093 ps
CPU time 68.38 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:57:55 PM PST 23
Peak memory 249860 kb
Host smart-004043b3-7801-44e9-872d-47a52f9241fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522577696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.522577696
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2954092726
Short name T1712
Test name
Test status
Simulation time 10109314760 ps
CPU time 24.37 seconds
Started Dec 24 01:56:38 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 256848 kb
Host smart-f5b5f0d0-715a-4359-b618-f4e9b351b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954092726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2954092726
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1918199816
Short name T231
Test name
Test status
Simulation time 10270296985 ps
CPU time 7.97 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:52 PM PST 23
Peak memory 222160 kb
Host smart-a0feafc6-d655-4ea9-adb9-7028ba13f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918199816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1918199816
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intr.2267940811
Short name T1102
Test name
Test status
Simulation time 35727168827 ps
CPU time 24.74 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 217956 kb
Host smart-f5eea194-2791-4963-8ae2-2452c34683f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267940811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intr.2267940811
Directory /workspace/32.spi_device_intr/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4034518190
Short name T1180
Test name
Test status
Simulation time 82874427 ps
CPU time 3.12 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:46 PM PST 23
Peak memory 226176 kb
Host smart-b83bf6f9-6409-49ed-b11f-1bbb25094c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034518190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4034518190
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2561606840
Short name T1421
Test name
Test status
Simulation time 699185024 ps
CPU time 12.74 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:57 PM PST 23
Peak memory 255624 kb
Host smart-768d757e-59b2-4b32-b897-540953fb63f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561606840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2561606840
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3935585030
Short name T1593
Test name
Test status
Simulation time 8751496101 ps
CPU time 29.38 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:57:15 PM PST 23
Peak memory 257864 kb
Host smart-e0e518d0-8b28-47a0-b729-cc8593e0b040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935585030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3935585030
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_perf.3611833495
Short name T575
Test name
Test status
Simulation time 21519741329 ps
CPU time 574.4 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 02:06:21 PM PST 23
Peak memory 289888 kb
Host smart-461ec981-40ea-4ea5-9b7b-1433fc8fe797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611833495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_perf.3611833495
Directory /workspace/32.spi_device_perf/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1268180998
Short name T597
Test name
Test status
Simulation time 1596509523 ps
CPU time 5.86 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:48 PM PST 23
Peak memory 234460 kb
Host smart-5e90f328-d0b9-4372-a13a-a66c603d9388
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1268180998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1268180998
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_rx_async_fifo_reset.1465814640
Short name T77
Test name
Test status
Simulation time 34288123 ps
CPU time 0.87 seconds
Started Dec 24 01:56:39 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 208400 kb
Host smart-d8ebb1d8-cc74-4452-ab83-9996f02f3dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465814640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_async_fifo_reset.1465814640
Directory /workspace/32.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_rx_timeout.3484596298
Short name T1418
Test name
Test status
Simulation time 2023828206 ps
CPU time 6.3 seconds
Started Dec 24 01:56:41 PM PST 23
Finished Dec 24 01:56:53 PM PST 23
Peak memory 216844 kb
Host smart-f45d7691-3d19-44a3-a7ef-4336ad5b3115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484596298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_timeout.3484596298
Directory /workspace/32.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/32.spi_device_smoke.1114722373
Short name T813
Test name
Test status
Simulation time 29665184 ps
CPU time 1.07 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:44 PM PST 23
Peak memory 208004 kb
Host smart-364ea2e7-8ed2-43eb-a1cc-c11a20c5afce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114722373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_smoke.1114722373
Directory /workspace/32.spi_device_smoke/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1819541730
Short name T1698
Test name
Test status
Simulation time 1164814317 ps
CPU time 18.03 seconds
Started Dec 24 01:56:37 PM PST 23
Finished Dec 24 01:57:00 PM PST 23
Peak memory 216852 kb
Host smart-cf50269d-941d-4281-a85b-e21f21e351ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819541730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1819541730
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.156716729
Short name T709
Test name
Test status
Simulation time 18491266771 ps
CPU time 17.85 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:57:01 PM PST 23
Peak memory 216872 kb
Host smart-ce97b2d5-ef35-44d9-83b6-e928ea884567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156716729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.156716729
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.736397895
Short name T882
Test name
Test status
Simulation time 343885187 ps
CPU time 2.88 seconds
Started Dec 24 01:56:40 PM PST 23
Finished Dec 24 01:56:47 PM PST 23
Peak memory 216800 kb
Host smart-27b9e6d5-fd06-4720-8cb0-45b5ffc9c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736397895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.736397895
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3379583763
Short name T1592
Test name
Test status
Simulation time 73338419 ps
CPU time 1.03 seconds
Started Dec 24 01:56:45 PM PST 23
Finished Dec 24 01:56:51 PM PST 23
Peak memory 208048 kb
Host smart-458ad5d5-c853-4deb-a481-eb28d62088c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379583763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3379583763
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tx_async_fifo_reset.2718520816
Short name T504
Test name
Test status
Simulation time 24586251 ps
CPU time 0.79 seconds
Started Dec 24 01:56:44 PM PST 23
Finished Dec 24 01:56:51 PM PST 23
Peak memory 208564 kb
Host smart-a434c747-0593-4ef0-8392-ffe62296b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718520816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tx_async_fifo_reset.2718520816
Directory /workspace/32.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/32.spi_device_txrx.2201818113
Short name T1348
Test name
Test status
Simulation time 24970814018 ps
CPU time 247.5 seconds
Started Dec 24 01:56:44 PM PST 23
Finished Dec 24 02:00:57 PM PST 23
Peak memory 289876 kb
Host smart-9d1f6ed0-72e2-4303-bcab-814faa43f1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201818113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_txrx.2201818113
Directory /workspace/32.spi_device_txrx/latest

Test location /workspace/coverage/default/32.spi_device_upload.844167607
Short name T1585
Test name
Test status
Simulation time 10214774103 ps
CPU time 10.74 seconds
Started Dec 24 01:56:43 PM PST 23
Finished Dec 24 01:57:00 PM PST 23
Peak memory 219968 kb
Host smart-6b847b4f-2bd6-434c-a792-9170c53ecc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844167607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.844167607
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_abort.1433788853
Short name T1173
Test name
Test status
Simulation time 245612761 ps
CPU time 0.74 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 206576 kb
Host smart-15303c68-346d-4b95-98fb-a5ed2f86ee3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433788853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_abort.1433788853
Directory /workspace/33.spi_device_abort/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1628848310
Short name T80
Test name
Test status
Simulation time 41739036 ps
CPU time 0.76 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 206496 kb
Host smart-9b4f9004-71cc-4136-b367-f3ec12aee6e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628848310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1628848310
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_bit_transfer.2025656788
Short name T1185
Test name
Test status
Simulation time 595098590 ps
CPU time 2.79 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:09 PM PST 23
Peak memory 216832 kb
Host smart-33efb5d6-d99f-4656-bcf1-36557da031e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025656788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_bit_transfer.2025656788
Directory /workspace/33.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/33.spi_device_byte_transfer.1618402550
Short name T633
Test name
Test status
Simulation time 2465353398 ps
CPU time 3.37 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 216856 kb
Host smart-fc798a50-c148-47c2-9466-6917ccf643bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618402550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_byte_transfer.1618402550
Directory /workspace/33.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4241612616
Short name T262
Test name
Test status
Simulation time 2418020362 ps
CPU time 3.64 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 225128 kb
Host smart-0de4a640-ba56-4393-8418-1ca776f25ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241612616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4241612616
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.546760356
Short name T1447
Test name
Test status
Simulation time 43917273 ps
CPU time 0.84 seconds
Started Dec 24 01:56:54 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 206616 kb
Host smart-f30c59ab-bd4a-4e92-b342-cde251d3966f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546760356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.546760356
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_dummy_item_extra_dly.412859105
Short name T1544
Test name
Test status
Simulation time 29306530566 ps
CPU time 596.73 seconds
Started Dec 24 01:56:59 PM PST 23
Finished Dec 24 02:07:09 PM PST 23
Peak memory 248880 kb
Host smart-71b0a5fb-259a-4a89-a24a-24939fb57c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412859105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_dummy_item_extra_dly.412859105
Directory /workspace/33.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/33.spi_device_extreme_fifo_size.2490943551
Short name T1318
Test name
Test status
Simulation time 412465615367 ps
CPU time 578.08 seconds
Started Dec 24 01:56:54 PM PST 23
Finished Dec 24 02:06:44 PM PST 23
Peak memory 218056 kb
Host smart-dc86e0c0-f2fc-4e70-b6d2-1be4c70cfa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490943551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_extreme_fifo_size.2490943551
Directory /workspace/33.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/33.spi_device_fifo_full.2196498942
Short name T194
Test name
Test status
Simulation time 12538722797 ps
CPU time 252.98 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 02:01:21 PM PST 23
Peak memory 299056 kb
Host smart-40b08d40-9176-4b89-a151-cc9d443cb9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196498942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_full.2196498942
Directory /workspace/33.spi_device_fifo_full/latest

Test location /workspace/coverage/default/33.spi_device_fifo_underflow_overflow.607099849
Short name T51
Test name
Test status
Simulation time 144594816812 ps
CPU time 716.03 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 633588 kb
Host smart-90d4cedf-bec0-4de7-bf83-3dea2d1aa32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607099849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_underflow_overfl
ow.607099849
Directory /workspace/33.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1322373265
Short name T344
Test name
Test status
Simulation time 35571198468 ps
CPU time 109.62 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:58:56 PM PST 23
Peak memory 251264 kb
Host smart-e3a7faf2-540a-438b-81b2-5d49792ca102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322373265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1322373265
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.54132609
Short name T1697
Test name
Test status
Simulation time 4859691016 ps
CPU time 112.39 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:59:00 PM PST 23
Peak memory 274184 kb
Host smart-2d12d0a4-db6a-400f-a998-b6a1e6b744ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54132609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.54132609
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1458704656
Short name T317
Test name
Test status
Simulation time 23201119021 ps
CPU time 155.48 seconds
Started Dec 24 01:56:54 PM PST 23
Finished Dec 24 01:59:42 PM PST 23
Peak memory 259808 kb
Host smart-89c67f5d-186a-4bc6-b6ab-fc32746dd4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458704656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1458704656
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3268775338
Short name T353
Test name
Test status
Simulation time 21510367489 ps
CPU time 34.66 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 241200 kb
Host smart-494ace9d-4f4a-48c1-8117-c0be507a849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268775338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3268775338
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2513683041
Short name T1197
Test name
Test status
Simulation time 12465014794 ps
CPU time 9.61 seconds
Started Dec 24 01:56:54 PM PST 23
Finished Dec 24 01:57:16 PM PST 23
Peak memory 238252 kb
Host smart-f29c25f9-35a3-4154-b4d1-d74450e9db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513683041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2513683041
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intr.3830944486
Short name T1561
Test name
Test status
Simulation time 6558816724 ps
CPU time 12.95 seconds
Started Dec 24 01:56:51 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 217120 kb
Host smart-ec0af59a-cfd4-46b5-b885-67066fc006cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830944486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intr.3830944486
Directory /workspace/33.spi_device_intr/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2739123833
Short name T1045
Test name
Test status
Simulation time 1300808449 ps
CPU time 10.34 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:18 PM PST 23
Peak memory 241500 kb
Host smart-765c4ef6-e78f-4f19-b108-56376037a72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739123833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2739123833
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1619512178
Short name T218
Test name
Test status
Simulation time 366765655 ps
CPU time 5.78 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:57:12 PM PST 23
Peak memory 218620 kb
Host smart-1ebe11b4-15c9-47be-9e7c-639f1f8ba789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619512178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1619512178
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1287137938
Short name T849
Test name
Test status
Simulation time 297472166 ps
CPU time 3.31 seconds
Started Dec 24 01:56:52 PM PST 23
Finished Dec 24 01:57:01 PM PST 23
Peak memory 218736 kb
Host smart-887b234d-840f-4b49-b1d0-6bf330481584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287137938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1287137938
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_perf.2169339889
Short name T1066
Test name
Test status
Simulation time 10804613936 ps
CPU time 309.36 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 02:02:15 PM PST 23
Peak memory 271984 kb
Host smart-9352c6fe-a748-4570-9eea-fe7ec08e5444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169339889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_perf.2169339889
Directory /workspace/33.spi_device_perf/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.285543203
Short name T997
Test name
Test status
Simulation time 72521745 ps
CPU time 3.53 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 01:57:10 PM PST 23
Peak memory 220388 kb
Host smart-b6b64c00-5b48-4243-b790-d058e6421100
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=285543203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.285543203
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_rx_async_fifo_reset.3126433663
Short name T668
Test name
Test status
Simulation time 210777539 ps
CPU time 0.91 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:09 PM PST 23
Peak memory 208384 kb
Host smart-7fb4db04-ec4f-4800-ac06-5c8e223ca531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126433663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_async_fifo_reset.3126433663
Directory /workspace/33.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_rx_timeout.2876450998
Short name T562
Test name
Test status
Simulation time 1962235455 ps
CPU time 5.84 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:13 PM PST 23
Peak memory 216860 kb
Host smart-49aa8682-e012-4839-bbda-21bf8baf7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876450998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_timeout.2876450998
Directory /workspace/33.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/33.spi_device_smoke.2296671310
Short name T763
Test name
Test status
Simulation time 230134073 ps
CPU time 1.19 seconds
Started Dec 24 01:56:42 PM PST 23
Finished Dec 24 01:56:49 PM PST 23
Peak memory 216552 kb
Host smart-8bbc4498-6c56-4201-9485-22fcf7b35a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296671310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_smoke.2296671310
Directory /workspace/33.spi_device_smoke/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1999784745
Short name T1515
Test name
Test status
Simulation time 648850297314 ps
CPU time 1548.67 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 02:22:56 PM PST 23
Peak memory 513364 kb
Host smart-e2b855fd-79dc-4e4b-a50b-62b2800398ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999784745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1999784745
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2966414725
Short name T1722
Test name
Test status
Simulation time 4416982146 ps
CPU time 35.96 seconds
Started Dec 24 01:56:59 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 220788 kb
Host smart-8c5fce06-e32b-40c2-9dc8-3229af5c320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966414725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2966414725
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2198563449
Short name T1151
Test name
Test status
Simulation time 1236834328 ps
CPU time 3.82 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 216864 kb
Host smart-42bc630a-3691-4e47-9b9f-7d58cd91d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198563449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2198563449
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.760086119
Short name T1547
Test name
Test status
Simulation time 43955182 ps
CPU time 1.21 seconds
Started Dec 24 01:57:03 PM PST 23
Finished Dec 24 01:57:14 PM PST 23
Peak memory 208484 kb
Host smart-567c14c8-1f98-457c-9105-9acc16ac754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760086119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.760086119
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1094579350
Short name T1321
Test name
Test status
Simulation time 98635911 ps
CPU time 1.04 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:10 PM PST 23
Peak memory 207956 kb
Host smart-71a1e1e2-3ea5-49b5-a405-9a179a059ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094579350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1094579350
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tx_async_fifo_reset.3223584324
Short name T1132
Test name
Test status
Simulation time 93599405 ps
CPU time 0.77 seconds
Started Dec 24 01:57:00 PM PST 23
Finished Dec 24 01:57:13 PM PST 23
Peak memory 208472 kb
Host smart-a6f620f4-a3d6-4ca8-9c9d-242466c9bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223584324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tx_async_fifo_reset.3223584324
Directory /workspace/33.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/33.spi_device_txrx.2889162800
Short name T1054
Test name
Test status
Simulation time 54969597784 ps
CPU time 199.31 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 02:00:25 PM PST 23
Peak memory 288028 kb
Host smart-523f9aa1-b13c-4734-9c67-5eda72e48a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889162800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_txrx.2889162800
Directory /workspace/33.spi_device_txrx/latest

Test location /workspace/coverage/default/33.spi_device_upload.3254512599
Short name T1009
Test name
Test status
Simulation time 11474689160 ps
CPU time 39.6 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 239200 kb
Host smart-e7f4bcdd-4fca-45da-aca7-f6715f6c52ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254512599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3254512599
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_abort.680274301
Short name T506
Test name
Test status
Simulation time 25258417 ps
CPU time 0.74 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 206668 kb
Host smart-601d092e-d4b6-4744-b62e-51f23c335e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680274301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_abort.680274301
Directory /workspace/34.spi_device_abort/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3985138367
Short name T1758
Test name
Test status
Simulation time 14704471 ps
CPU time 0.74 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 206464 kb
Host smart-3993dffb-2f36-40e5-8df6-6eb2f32d9c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985138367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3985138367
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_bit_transfer.2528686538
Short name T966
Test name
Test status
Simulation time 134301972 ps
CPU time 2.47 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 216700 kb
Host smart-35fd7d90-b035-4880-8ac1-92a62415b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528686538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_bit_transfer.2528686538
Directory /workspace/34.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/34.spi_device_byte_transfer.550428823
Short name T774
Test name
Test status
Simulation time 65308256 ps
CPU time 2.54 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 216884 kb
Host smart-b3aabaf2-5bf2-4c08-9869-4e6fdf152b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550428823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_byte_transfer.550428823
Directory /workspace/34.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3977603411
Short name T1344
Test name
Test status
Simulation time 7606975196 ps
CPU time 7.83 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 01:57:14 PM PST 23
Peak memory 220292 kb
Host smart-9eb15740-c6a9-4ca6-b3ed-c1b615b2591d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977603411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3977603411
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1030093365
Short name T1760
Test name
Test status
Simulation time 17655690 ps
CPU time 0.76 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 206584 kb
Host smart-8271224d-7210-45f7-8c20-dc1b05ec61bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030093365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1030093365
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_dummy_item_extra_dly.570048805
Short name T930
Test name
Test status
Simulation time 228086587320 ps
CPU time 298.84 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 02:02:07 PM PST 23
Peak memory 306384 kb
Host smart-af5b9d30-213b-4d28-94b3-f989fff7363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570048805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_dummy_item_extra_dly.570048805
Directory /workspace/34.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/34.spi_device_extreme_fifo_size.310129924
Short name T533
Test name
Test status
Simulation time 238289285638 ps
CPU time 2317.47 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 02:35:48 PM PST 23
Peak memory 220272 kb
Host smart-0afe924e-c1f4-48ab-93d4-42af9bfefc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310129924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_extreme_fifo_size.310129924
Directory /workspace/34.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/34.spi_device_fifo_full.2262153357
Short name T1438
Test name
Test status
Simulation time 43093400155 ps
CPU time 861.39 seconds
Started Dec 24 01:57:02 PM PST 23
Finished Dec 24 02:11:33 PM PST 23
Peak memory 249744 kb
Host smart-3edfb765-a78e-4565-9201-80ecf88fe8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262153357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_full.2262153357
Directory /workspace/34.spi_device_fifo_full/latest

Test location /workspace/coverage/default/34.spi_device_fifo_underflow_overflow.2062182985
Short name T488
Test name
Test status
Simulation time 122385292712 ps
CPU time 212.27 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 02:00:40 PM PST 23
Peak memory 320664 kb
Host smart-33ecd541-fedc-419a-a53d-230cf3f9bc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062182985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_underflow_overf
low.2062182985
Directory /workspace/34.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1533802890
Short name T1184
Test name
Test status
Simulation time 174575955256 ps
CPU time 209.83 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 02:00:52 PM PST 23
Peak memory 249768 kb
Host smart-df59b879-eca8-4fc2-be60-465444c63aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533802890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1533802890
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4084093014
Short name T1011
Test name
Test status
Simulation time 9467189842 ps
CPU time 51.98 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:59 PM PST 23
Peak memory 249540 kb
Host smart-c5b0ab7e-b44e-41c5-b746-59213283e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084093014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4084093014
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2387021149
Short name T1672
Test name
Test status
Simulation time 1222475308 ps
CPU time 4.4 seconds
Started Dec 24 01:56:59 PM PST 23
Finished Dec 24 01:57:16 PM PST 23
Peak memory 238036 kb
Host smart-73ad30c1-6bdf-43d9-a2b3-ffccb5b12550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387021149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2387021149
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intr.1589463424
Short name T1612
Test name
Test status
Simulation time 1825530922 ps
CPU time 9.21 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:57:15 PM PST 23
Peak memory 216948 kb
Host smart-7184f35d-1319-4e83-85ec-f399131c5c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589463424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intr.1589463424
Directory /workspace/34.spi_device_intr/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1677486974
Short name T870
Test name
Test status
Simulation time 4272676743 ps
CPU time 10.73 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 01:57:17 PM PST 23
Peak memory 219168 kb
Host smart-fa112fee-625e-4a7b-9d08-3d86d35e9217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677486974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1677486974
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1081944040
Short name T251
Test name
Test status
Simulation time 502382003 ps
CPU time 9.34 seconds
Started Dec 24 01:57:00 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 248704 kb
Host smart-e953a0c1-ce12-410c-98df-46bd41c2c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081944040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1081944040
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.180383846
Short name T1076
Test name
Test status
Simulation time 9657598175 ps
CPU time 28.83 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:36 PM PST 23
Peak memory 230400 kb
Host smart-9857e999-b03d-4434-8314-31c3383994fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180383846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.180383846
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_perf.4112751723
Short name T1791
Test name
Test status
Simulation time 117566221663 ps
CPU time 218.85 seconds
Started Dec 24 01:56:54 PM PST 23
Finished Dec 24 02:00:45 PM PST 23
Peak memory 234428 kb
Host smart-8fcded0c-cf2a-4de1-911e-0795b93c2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112751723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_perf.4112751723
Directory /workspace/34.spi_device_perf/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2349200685
Short name T174
Test name
Test status
Simulation time 2068491741 ps
CPU time 4.42 seconds
Started Dec 24 01:56:59 PM PST 23
Finished Dec 24 01:57:16 PM PST 23
Peak memory 219812 kb
Host smart-265b27be-8512-40fa-af8c-20741ef576ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349200685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2349200685
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_rx_async_fifo_reset.856246164
Short name T910
Test name
Test status
Simulation time 36236310 ps
CPU time 0.91 seconds
Started Dec 24 01:56:59 PM PST 23
Finished Dec 24 01:57:13 PM PST 23
Peak memory 208484 kb
Host smart-a2dfef55-4a6e-4dbe-a2f7-bedb8ade96bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856246164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_async_fifo_reset.856246164
Directory /workspace/34.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_rx_timeout.908129938
Short name T1392
Test name
Test status
Simulation time 2005673444 ps
CPU time 5.64 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:12 PM PST 23
Peak memory 216896 kb
Host smart-6459936c-840b-45a4-94bb-3f02c2bc38b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908129938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_timeout.908129938
Directory /workspace/34.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/34.spi_device_smoke.3465117469
Short name T1736
Test name
Test status
Simulation time 114079591 ps
CPU time 1.08 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 207928 kb
Host smart-0a9e5bdf-6ab9-49bd-971b-b894e57985e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465117469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_smoke.3465117469
Directory /workspace/34.spi_device_smoke/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2261001350
Short name T557
Test name
Test status
Simulation time 32288674705 ps
CPU time 114.43 seconds
Started Dec 24 01:57:02 PM PST 23
Finished Dec 24 01:59:06 PM PST 23
Peak memory 217000 kb
Host smart-0f792184-a46b-44e0-bac8-8c74cfb439cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261001350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2261001350
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1284760170
Short name T1765
Test name
Test status
Simulation time 136630719759 ps
CPU time 23.67 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 01:57:30 PM PST 23
Peak memory 216844 kb
Host smart-f79cdc0f-5a4f-475d-9d5f-253e8865073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284760170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1284760170
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3190563581
Short name T1667
Test name
Test status
Simulation time 482933443 ps
CPU time 6.95 seconds
Started Dec 24 01:57:01 PM PST 23
Finished Dec 24 01:57:19 PM PST 23
Peak memory 216764 kb
Host smart-78524e40-9b71-47df-9dd5-ce6325df322d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190563581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3190563581
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.147377597
Short name T1741
Test name
Test status
Simulation time 121877656 ps
CPU time 1.07 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:08 PM PST 23
Peak memory 208024 kb
Host smart-94f4f445-66b8-478f-96cd-074751052db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147377597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.147377597
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tx_async_fifo_reset.2048524898
Short name T1289
Test name
Test status
Simulation time 17031834 ps
CPU time 0.8 seconds
Started Dec 24 01:56:56 PM PST 23
Finished Dec 24 01:57:07 PM PST 23
Peak memory 208504 kb
Host smart-867a12ae-8132-4a1f-8ed3-aa6c58ce8f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048524898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tx_async_fifo_reset.2048524898
Directory /workspace/34.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/34.spi_device_txrx.4063493483
Short name T1731
Test name
Test status
Simulation time 95355290579 ps
CPU time 199.37 seconds
Started Dec 24 01:56:53 PM PST 23
Finished Dec 24 02:00:23 PM PST 23
Peak memory 292732 kb
Host smart-a2759ca6-a078-48dc-828d-4c7e4391feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063493483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_txrx.4063493483
Directory /workspace/34.spi_device_txrx/latest

Test location /workspace/coverage/default/34.spi_device_upload.4157732006
Short name T278
Test name
Test status
Simulation time 101473559 ps
CPU time 2.52 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:10 PM PST 23
Peak memory 217068 kb
Host smart-ccd6e5b8-5666-4e4f-8218-5c6f3cdddc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157732006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4157732006
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_abort.3891271661
Short name T1373
Test name
Test status
Simulation time 45520813 ps
CPU time 0.74 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 206640 kb
Host smart-9362deab-b941-49fa-aec6-829bafd593d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891271661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_abort.3891271661
Directory /workspace/35.spi_device_abort/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2724981555
Short name T778
Test name
Test status
Simulation time 12194048 ps
CPU time 0.75 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 206444 kb
Host smart-0c683446-5ed2-4a29-9c9d-b31c1163970a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724981555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2724981555
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_bit_transfer.1161186062
Short name T765
Test name
Test status
Simulation time 320043479 ps
CPU time 3.1 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 216808 kb
Host smart-363897f3-4474-464d-96b4-450a35f991ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161186062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_bit_transfer.1161186062
Directory /workspace/35.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/35.spi_device_byte_transfer.1418260003
Short name T610
Test name
Test status
Simulation time 422901424 ps
CPU time 2.23 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:20 PM PST 23
Peak memory 216808 kb
Host smart-099cc117-58eb-44de-aa21-4b594694b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418260003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_byte_transfer.1418260003
Directory /workspace/35.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3932362508
Short name T265
Test name
Test status
Simulation time 568352199 ps
CPU time 3.4 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:10 PM PST 23
Peak memory 233312 kb
Host smart-ba1e316a-ef65-49d9-a377-0eef79210683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932362508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3932362508
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.21061181
Short name T1441
Test name
Test status
Simulation time 44120213 ps
CPU time 0.79 seconds
Started Dec 24 01:57:00 PM PST 23
Finished Dec 24 01:57:13 PM PST 23
Peak memory 206608 kb
Host smart-769eb6f9-fa2c-42dd-aa29-0004e0e0e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21061181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.21061181
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_dummy_item_extra_dly.1536752686
Short name T665
Test name
Test status
Simulation time 29065222628 ps
CPU time 206.39 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 02:00:47 PM PST 23
Peak memory 273120 kb
Host smart-89a6cb57-c1e7-45f2-bbcd-1297939e8878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536752686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_dummy_item_extra_dly.1536752686
Directory /workspace/35.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/35.spi_device_extreme_fifo_size.470983785
Short name T1070
Test name
Test status
Simulation time 2206099654 ps
CPU time 28.32 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:38 PM PST 23
Peak memory 238616 kb
Host smart-881b8551-d511-49e3-80fd-a9c46034e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470983785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_extreme_fifo_size.470983785
Directory /workspace/35.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/35.spi_device_fifo_full.455839265
Short name T1634
Test name
Test status
Simulation time 19684283842 ps
CPU time 420.9 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 02:04:18 PM PST 23
Peak memory 297000 kb
Host smart-9231655f-ec6e-4d26-9b3e-ba5993432d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455839265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_full.455839265
Directory /workspace/35.spi_device_fifo_full/latest

Test location /workspace/coverage/default/35.spi_device_fifo_underflow_overflow.918119703
Short name T752
Test name
Test status
Simulation time 136551194437 ps
CPU time 453.81 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 02:04:54 PM PST 23
Peak memory 360956 kb
Host smart-ef65ae04-5410-43d6-a0b2-4e16c2b2dc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918119703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_underflow_overfl
ow.918119703
Directory /workspace/35.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.68459062
Short name T1213
Test name
Test status
Simulation time 494382903 ps
CPU time 8.03 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 233328 kb
Host smart-98ac048b-e753-4c6c-a5f3-128856e4b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68459062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.68459062
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4207547410
Short name T869
Test name
Test status
Simulation time 9160800191 ps
CPU time 47.87 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:58:14 PM PST 23
Peak memory 238656 kb
Host smart-fd6e9434-9726-47e4-ae5e-e985a41c918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207547410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4207547410
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2550019858
Short name T346
Test name
Test status
Simulation time 12126736952 ps
CPU time 121.4 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:59:29 PM PST 23
Peak memory 252560 kb
Host smart-fe63eb38-93eb-4532-9d47-7ebbcd1b993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550019858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2550019858
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2537304181
Short name T855
Test name
Test status
Simulation time 3233985192 ps
CPU time 11.07 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 251632 kb
Host smart-24783062-5fac-455f-ba57-e1ab7605e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537304181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2537304181
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.359851346
Short name T1401
Test name
Test status
Simulation time 3284018693 ps
CPU time 6.89 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 240252 kb
Host smart-66e2adb1-e5dc-4842-8d46-6c0554e479fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359851346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.359851346
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intr.3581754727
Short name T1469
Test name
Test status
Simulation time 8679735652 ps
CPU time 45.73 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:58:05 PM PST 23
Peak memory 232756 kb
Host smart-e171348d-19d4-4d60-a55a-8ad4c9954424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581754727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intr.3581754727
Directory /workspace/35.spi_device_intr/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4225951274
Short name T1491
Test name
Test status
Simulation time 3783396236 ps
CPU time 19.45 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 244240 kb
Host smart-edaa2dbd-6ab8-4e20-ba1b-c2eb17b78bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225951274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4225951274
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2318105313
Short name T252
Test name
Test status
Simulation time 5579299729 ps
CPU time 8.92 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:27 PM PST 23
Peak memory 219344 kb
Host smart-2a10eb3e-49bb-44d3-8596-c523aa3dc07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318105313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2318105313
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1985668547
Short name T1350
Test name
Test status
Simulation time 1543013414 ps
CPU time 12.42 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:34 PM PST 23
Peak memory 238132 kb
Host smart-3c6c9da0-c479-4d91-bd02-01da9abf1cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985668547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1985668547
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_perf.4005248935
Short name T1554
Test name
Test status
Simulation time 94573771021 ps
CPU time 525.2 seconds
Started Dec 24 01:56:59 PM PST 23
Finished Dec 24 02:05:57 PM PST 23
Peak memory 298884 kb
Host smart-920ad261-b028-4805-b603-188391807cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005248935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_perf.4005248935
Directory /workspace/35.spi_device_perf/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2475937295
Short name T1589
Test name
Test status
Simulation time 12270390881 ps
CPU time 5.91 seconds
Started Dec 24 01:57:01 PM PST 23
Finished Dec 24 01:57:18 PM PST 23
Peak memory 221228 kb
Host smart-a41956bd-2823-4e59-9d41-a271165dee58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2475937295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2475937295
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_rx_async_fifo_reset.322876050
Short name T1049
Test name
Test status
Simulation time 179400372 ps
CPU time 0.86 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:24 PM PST 23
Peak memory 208440 kb
Host smart-404e1dff-69a4-484d-bae4-4f936d19000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322876050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_async_fifo_reset.322876050
Directory /workspace/35.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_rx_timeout.883628386
Short name T943
Test name
Test status
Simulation time 3748153642 ps
CPU time 5.32 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 216872 kb
Host smart-247bd556-4488-436f-b101-30d05c2f443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883628386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_timeout.883628386
Directory /workspace/35.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/35.spi_device_smoke.2063022959
Short name T1599
Test name
Test status
Simulation time 186844519 ps
CPU time 1.22 seconds
Started Dec 24 01:57:09 PM PST 23
Finished Dec 24 01:57:18 PM PST 23
Peak memory 216888 kb
Host smart-04d51276-a46b-4f9e-8fd7-3b15b168210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063022959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_smoke.2063022959
Directory /workspace/35.spi_device_smoke/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.126111648
Short name T228
Test name
Test status
Simulation time 225820175303 ps
CPU time 1458.63 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 02:21:25 PM PST 23
Peak memory 303136 kb
Host smart-9557b582-d312-4d24-bfe0-555b8a4548cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126111648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.126111648
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.449442540
Short name T1175
Test name
Test status
Simulation time 1392804342 ps
CPU time 19.99 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:39 PM PST 23
Peak memory 216900 kb
Host smart-57bb7233-d952-42a9-a0dc-5946238d7a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449442540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.449442540
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.966687941
Short name T1707
Test name
Test status
Simulation time 4599258770 ps
CPU time 16.78 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:35 PM PST 23
Peak memory 217984 kb
Host smart-169ec8c1-f1e5-4e11-983d-1f4f2843e902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966687941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.966687941
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2096156311
Short name T561
Test name
Test status
Simulation time 829913415 ps
CPU time 2.91 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 217904 kb
Host smart-4626e3fa-f092-4572-afbb-a2b1660d377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096156311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2096156311
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3892150144
Short name T1550
Test name
Test status
Simulation time 111323431 ps
CPU time 0.78 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 206964 kb
Host smart-004fac3d-67ef-429e-94ab-85cc4596fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892150144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3892150144
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tx_async_fifo_reset.410350238
Short name T1762
Test name
Test status
Simulation time 19195631 ps
CPU time 0.78 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 208460 kb
Host smart-df64b306-281e-4316-9070-2fbe2876a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410350238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tx_async_fifo_reset.410350238
Directory /workspace/35.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/35.spi_device_txrx.2420478851
Short name T1166
Test name
Test status
Simulation time 104706187646 ps
CPU time 238.57 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 02:01:16 PM PST 23
Peak memory 290496 kb
Host smart-eade82cb-7959-4c4c-9997-b13b2558dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420478851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_txrx.2420478851
Directory /workspace/35.spi_device_txrx/latest

Test location /workspace/coverage/default/35.spi_device_upload.611926389
Short name T549
Test name
Test status
Simulation time 12933501520 ps
CPU time 42.89 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:58:03 PM PST 23
Peak memory 233352 kb
Host smart-2ae0d02c-cfd0-4e9e-a6ee-facbd923b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611926389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.611926389
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_abort.2530081586
Short name T1499
Test name
Test status
Simulation time 58229345 ps
CPU time 0.76 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:20 PM PST 23
Peak memory 206644 kb
Host smart-96ff9807-0b32-45a7-a7e5-755103dd2175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530081586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_abort.2530081586
Directory /workspace/36.spi_device_abort/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3232388445
Short name T1625
Test name
Test status
Simulation time 14787174 ps
CPU time 0.75 seconds
Started Dec 24 01:57:07 PM PST 23
Finished Dec 24 01:57:17 PM PST 23
Peak memory 206468 kb
Host smart-ba796bcc-7608-4070-921a-a7239f0ec5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232388445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3232388445
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_bit_transfer.2823670430
Short name T49
Test name
Test status
Simulation time 2168740071 ps
CPU time 2.59 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 216808 kb
Host smart-47655f98-7cd6-41c4-a82c-e45d30456701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823670430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_bit_transfer.2823670430
Directory /workspace/36.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/36.spi_device_byte_transfer.3011112359
Short name T1097
Test name
Test status
Simulation time 460268530 ps
CPU time 2.71 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:31 PM PST 23
Peak memory 216820 kb
Host smart-07577c2b-d5ae-4edf-967c-f3a381d1ffde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011112359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_byte_transfer.3011112359
Directory /workspace/36.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1960760383
Short name T274
Test name
Test status
Simulation time 189676756 ps
CPU time 3.08 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:23 PM PST 23
Peak memory 238096 kb
Host smart-5acf4875-1a65-4cee-8b78-b84190407102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960760383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1960760383
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.249966086
Short name T40
Test name
Test status
Simulation time 46191375 ps
CPU time 0.82 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 207584 kb
Host smart-a8aa519d-2394-4484-946b-41cf7ffb28f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249966086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.249966086
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_dummy_item_extra_dly.1868272158
Short name T191
Test name
Test status
Simulation time 50865461115 ps
CPU time 149.2 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:59:49 PM PST 23
Peak memory 281768 kb
Host smart-bbdbcf71-e6ad-4a2a-9afa-5549b22094ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868272158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_dummy_item_extra_dly.1868272158
Directory /workspace/36.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/36.spi_device_extreme_fifo_size.3782780202
Short name T919
Test name
Test status
Simulation time 79382701942 ps
CPU time 3799.66 seconds
Started Dec 24 01:56:58 PM PST 23
Finished Dec 24 03:00:30 PM PST 23
Peak memory 222008 kb
Host smart-6110e376-5bcd-4e0c-a326-fafc597acc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782780202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_extreme_fifo_size.3782780202
Directory /workspace/36.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/36.spi_device_fifo_full.3143641793
Short name T929
Test name
Test status
Simulation time 58639128428 ps
CPU time 1060.15 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 02:15:07 PM PST 23
Peak memory 290048 kb
Host smart-6fe34be2-b93f-4a2d-bb6f-73c53bd2e8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143641793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_full.3143641793
Directory /workspace/36.spi_device_fifo_full/latest

Test location /workspace/coverage/default/36.spi_device_fifo_underflow_overflow.3579659231
Short name T704
Test name
Test status
Simulation time 332314252794 ps
CPU time 226.09 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 02:01:14 PM PST 23
Peak memory 399628 kb
Host smart-ad598192-fd0d-4996-afae-0964b0f3b669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579659231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_underflow_overf
low.3579659231
Directory /workspace/36.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4122663848
Short name T342
Test name
Test status
Simulation time 9346181703 ps
CPU time 99.71 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:59:01 PM PST 23
Peak memory 257660 kb
Host smart-a1f991fd-ce5f-4112-9c53-51705dee980d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122663848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4122663848
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1788474081
Short name T327
Test name
Test status
Simulation time 3917580629 ps
CPU time 21.39 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:43 PM PST 23
Peak memory 249772 kb
Host smart-df7e35bc-8dc3-480f-a62a-0123a36c4037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788474081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1788474081
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3594098010
Short name T1478
Test name
Test status
Simulation time 720122653 ps
CPU time 10.35 seconds
Started Dec 24 01:57:08 PM PST 23
Finished Dec 24 01:57:27 PM PST 23
Peak memory 247132 kb
Host smart-a73a4c61-297f-47f9-a4b3-0d32f12d3fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594098010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3594098010
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intr.913615854
Short name T1359
Test name
Test status
Simulation time 20317405339 ps
CPU time 34.11 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 233208 kb
Host smart-9f88d0e8-3c97-460b-b3dd-443df607372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913615854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intr.913615854
Directory /workspace/36.spi_device_intr/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3024460324
Short name T1133
Test name
Test status
Simulation time 33338523117 ps
CPU time 31.01 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:49 PM PST 23
Peak memory 250976 kb
Host smart-d693f649-8932-4d78-a476-b59a2cd2f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024460324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3024460324
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3455614017
Short name T308
Test name
Test status
Simulation time 6716038653 ps
CPU time 14.53 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 243948 kb
Host smart-799039c6-0f0c-4346-b2ec-2d9fc58e9ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455614017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3455614017
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.760140358
Short name T1571
Test name
Test status
Simulation time 2773072797 ps
CPU time 8.44 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:27 PM PST 23
Peak memory 225216 kb
Host smart-18d49233-4a83-469a-b507-bb7e4eb9ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760140358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.760140358
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_perf.4029983320
Short name T522
Test name
Test status
Simulation time 78453533025 ps
CPU time 407.12 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 02:04:15 PM PST 23
Peak memory 285256 kb
Host smart-4f60dcb5-c0fb-44f0-9ea5-e66bee3ce793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029983320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_perf.4029983320
Directory /workspace/36.spi_device_perf/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1810806763
Short name T661
Test name
Test status
Simulation time 660861598 ps
CPU time 4.33 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 234424 kb
Host smart-afa86d88-66e6-4024-8576-3268567ad102
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1810806763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1810806763
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_rx_async_fifo_reset.845480762
Short name T626
Test name
Test status
Simulation time 333104710 ps
CPU time 0.9 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:20 PM PST 23
Peak memory 208412 kb
Host smart-3938e9a4-ead9-4158-b87a-73d571a9455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845480762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_async_fifo_reset.845480762
Directory /workspace/36.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_rx_timeout.2016005151
Short name T1087
Test name
Test status
Simulation time 1338518253 ps
CPU time 6.28 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:13 PM PST 23
Peak memory 216744 kb
Host smart-d733776d-5742-4717-b9db-65ebf8417a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016005151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_timeout.2016005151
Directory /workspace/36.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/36.spi_device_smoke.2853193138
Short name T469
Test name
Test status
Simulation time 61976194 ps
CPU time 1.17 seconds
Started Dec 24 01:56:57 PM PST 23
Finished Dec 24 01:57:08 PM PST 23
Peak memory 208348 kb
Host smart-bd4e17ea-167e-4cab-a6d3-6bd540401822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853193138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_smoke.2853193138
Directory /workspace/36.spi_device_smoke/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3290027632
Short name T1234
Test name
Test status
Simulation time 340799208542 ps
CPU time 391.03 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 02:03:51 PM PST 23
Peak memory 307236 kb
Host smart-2ada5f90-cd16-4eca-b2e2-53eb8ef1d48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290027632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3290027632
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3405879345
Short name T1270
Test name
Test status
Simulation time 5128368123 ps
CPU time 53.26 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:58:11 PM PST 23
Peak memory 217116 kb
Host smart-247c8f47-0420-4881-a831-cf8d434b6e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405879345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3405879345
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1057190972
Short name T1262
Test name
Test status
Simulation time 91287077332 ps
CPU time 19.12 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:40 PM PST 23
Peak memory 216828 kb
Host smart-6777c987-47be-4349-8c21-eb2bd486c9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057190972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1057190972
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2403120363
Short name T1328
Test name
Test status
Simulation time 84346875 ps
CPU time 1.47 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:19 PM PST 23
Peak memory 216728 kb
Host smart-59969352-1d72-41db-a124-c67cafa2c883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403120363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2403120363
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.157805312
Short name T107
Test name
Test status
Simulation time 434397102 ps
CPU time 1 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 206908 kb
Host smart-23c5980b-8c0f-4e35-8d8d-7b51cee0cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157805312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.157805312
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tx_async_fifo_reset.2214220323
Short name T100
Test name
Test status
Simulation time 16148926 ps
CPU time 0.79 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 208484 kb
Host smart-64a2dcaa-02ca-4f5c-8863-73d9f78a7159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214220323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tx_async_fifo_reset.2214220323
Directory /workspace/36.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/36.spi_device_txrx.546540923
Short name T1603
Test name
Test status
Simulation time 115144539156 ps
CPU time 672.34 seconds
Started Dec 24 01:56:55 PM PST 23
Finished Dec 24 02:08:18 PM PST 23
Peak memory 265736 kb
Host smart-0bce4787-3eb5-45b9-af94-bb293c5a0c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546540923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_txrx.546540923
Directory /workspace/36.spi_device_txrx/latest

Test location /workspace/coverage/default/36.spi_device_upload.1064266327
Short name T933
Test name
Test status
Simulation time 1691017941 ps
CPU time 6.6 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:26 PM PST 23
Peak memory 241156 kb
Host smart-033f1df7-6d8b-4256-99d1-25279bfda7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064266327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1064266327
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_abort.627270227
Short name T73
Test name
Test status
Simulation time 16314881 ps
CPU time 0.77 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 206592 kb
Host smart-596b8900-bdfc-4dcd-a7a1-ee09f8aa5a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627270227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_abort.627270227
Directory /workspace/37.spi_device_abort/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.509597650
Short name T1764
Test name
Test status
Simulation time 161326315 ps
CPU time 0.72 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 206416 kb
Host smart-6504f098-4b08-48be-a79b-acd9b3ddc94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509597650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.509597650
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_bit_transfer.3341669865
Short name T1633
Test name
Test status
Simulation time 669413006 ps
CPU time 2.96 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:23 PM PST 23
Peak memory 216684 kb
Host smart-c47cb9f3-01a2-45a8-b1c2-40f1972497fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341669865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_bit_transfer.3341669865
Directory /workspace/37.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/37.spi_device_byte_transfer.4215935218
Short name T1560
Test name
Test status
Simulation time 278571120 ps
CPU time 2.78 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 216788 kb
Host smart-60a49594-ec50-42c0-9d91-d4f063e98af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215935218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_byte_transfer.4215935218
Directory /workspace/37.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4199068097
Short name T698
Test name
Test status
Simulation time 91431351 ps
CPU time 2.9 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 219652 kb
Host smart-66d26299-066b-4b07-9083-98100df9ff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199068097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4199068097
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1238849618
Short name T833
Test name
Test status
Simulation time 159272810 ps
CPU time 0.79 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 207596 kb
Host smart-da7914c6-a9b4-4e1c-a9a2-a904b72d5363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238849618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1238849618
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_dummy_item_extra_dly.2076019369
Short name T1594
Test name
Test status
Simulation time 131882231905 ps
CPU time 250.42 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 02:01:32 PM PST 23
Peak memory 266176 kb
Host smart-073f8820-7f43-4b5d-9c5f-081b3168cfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076019369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_dummy_item_extra_dly.2076019369
Directory /workspace/37.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/37.spi_device_extreme_fifo_size.1492864608
Short name T964
Test name
Test status
Simulation time 26890964181 ps
CPU time 65.82 seconds
Started Dec 24 01:57:09 PM PST 23
Finished Dec 24 01:58:23 PM PST 23
Peak memory 238900 kb
Host smart-512d41dd-74dc-4788-927c-caa86017e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492864608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_extreme_fifo_size.1492864608
Directory /workspace/37.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/37.spi_device_fifo_full.130437571
Short name T1468
Test name
Test status
Simulation time 18089801288 ps
CPU time 333.54 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 02:02:51 PM PST 23
Peak memory 307180 kb
Host smart-f46ad630-d1b9-4945-adfb-ffff806483c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130437571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_full.130437571
Directory /workspace/37.spi_device_fifo_full/latest

Test location /workspace/coverage/default/37.spi_device_fifo_underflow_overflow.2367046487
Short name T750
Test name
Test status
Simulation time 122094308119 ps
CPU time 383.53 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 02:03:42 PM PST 23
Peak memory 315292 kb
Host smart-fbd767be-7ea1-4c27-9d8f-cab4d17797ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367046487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_underflow_overf
low.2367046487
Directory /workspace/37.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2751511646
Short name T323
Test name
Test status
Simulation time 6613888970 ps
CPU time 63.53 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:58:25 PM PST 23
Peak memory 252372 kb
Host smart-5b4336a7-29a3-4833-b629-c0c39e402a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751511646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2751511646
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2018584564
Short name T1123
Test name
Test status
Simulation time 75062673480 ps
CPU time 151.09 seconds
Started Dec 24 01:57:18 PM PST 23
Finished Dec 24 01:59:58 PM PST 23
Peak memory 253804 kb
Host smart-4a3dc242-3bda-4ffb-a5b7-7a884c0c94e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018584564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2018584564
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2089333761
Short name T1660
Test name
Test status
Simulation time 4790586061 ps
CPU time 34.77 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:58:03 PM PST 23
Peak memory 232884 kb
Host smart-ac14f7eb-1037-4007-a189-ba88b3508a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089333761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2089333761
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4199634155
Short name T1128
Test name
Test status
Simulation time 13799547582 ps
CPU time 13.68 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:42 PM PST 23
Peak memory 239320 kb
Host smart-f941ce04-07f3-4ebc-b492-312cbb3dd144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199634155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4199634155
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intr.691182552
Short name T793
Test name
Test status
Simulation time 3913828325 ps
CPU time 6.52 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 216908 kb
Host smart-6e77c6fd-b237-402a-89ce-a0b9640728e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691182552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intr.691182552
Directory /workspace/37.spi_device_intr/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.834910170
Short name T1473
Test name
Test status
Simulation time 230118219 ps
CPU time 4.46 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 218476 kb
Host smart-80eebe1b-3c99-4c61-b412-ea4a160043b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834910170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.834910170
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2737358950
Short name T289
Test name
Test status
Simulation time 24616491561 ps
CPU time 16.67 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:45 PM PST 23
Peak memory 221416 kb
Host smart-9774fd27-1ab4-4a5d-869f-e095709d945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737358950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2737358950
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2109921374
Short name T1455
Test name
Test status
Simulation time 12725687167 ps
CPU time 14.66 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:37 PM PST 23
Peak memory 241444 kb
Host smart-f64ee3a5-7ddc-4b06-860b-465105ef06ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109921374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2109921374
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_perf.1278906554
Short name T1598
Test name
Test status
Simulation time 25551723328 ps
CPU time 67.93 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 241584 kb
Host smart-f547a286-6216-4484-87e4-35dd880f67fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278906554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_perf.1278906554
Directory /workspace/37.spi_device_perf/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2833263943
Short name T1532
Test name
Test status
Simulation time 852264087 ps
CPU time 5.99 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 01:57:34 PM PST 23
Peak memory 235912 kb
Host smart-8b77a028-f2e4-437c-8ef5-864f90a4dd5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2833263943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2833263943
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_rx_async_fifo_reset.1810544218
Short name T141
Test name
Test status
Simulation time 48521826 ps
CPU time 0.91 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:24 PM PST 23
Peak memory 208336 kb
Host smart-c368fe01-b4dc-48c0-b47e-15f09d11d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810544218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_async_fifo_reset.1810544218
Directory /workspace/37.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_rx_timeout.1842359380
Short name T1380
Test name
Test status
Simulation time 454954875 ps
CPU time 4.93 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:26 PM PST 23
Peak memory 216884 kb
Host smart-a6277014-c3b9-4444-acd6-fcf0e0610e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842359380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_timeout.1842359380
Directory /workspace/37.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/37.spi_device_smoke.2853454077
Short name T834
Test name
Test status
Simulation time 149461967 ps
CPU time 1.03 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 208244 kb
Host smart-b61a5d4f-4874-4347-bc53-99ae9c95d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853454077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_smoke.2853454077
Directory /workspace/37.spi_device_smoke/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.331543421
Short name T1136
Test name
Test status
Simulation time 276335448485 ps
CPU time 9325.98 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 04:32:53 PM PST 23
Peak memory 314412 kb
Host smart-2459a519-a190-4e30-94bc-439f22a956f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331543421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.331543421
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2044814009
Short name T925
Test name
Test status
Simulation time 9545001678 ps
CPU time 74.22 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:58:36 PM PST 23
Peak memory 216980 kb
Host smart-b0a7ae28-956b-4ca6-87ca-5c5559d36f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044814009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2044814009
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2781018871
Short name T519
Test name
Test status
Simulation time 4948495498 ps
CPU time 20.2 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:42 PM PST 23
Peak memory 216484 kb
Host smart-402c2cce-80b8-4158-9160-d2d0ad2ab0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781018871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2781018871
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1552207920
Short name T567
Test name
Test status
Simulation time 1001682385 ps
CPU time 4.43 seconds
Started Dec 24 01:57:08 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 216692 kb
Host smart-926e4b93-5589-4b17-bad8-8dd7a7438fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552207920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1552207920
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3504341441
Short name T5
Test name
Test status
Simulation time 506436109 ps
CPU time 0.97 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 207116 kb
Host smart-013ccbc0-3637-496b-a8f2-1379d57a25fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504341441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3504341441
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tx_async_fifo_reset.2248192530
Short name T505
Test name
Test status
Simulation time 59028001 ps
CPU time 0.81 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 208416 kb
Host smart-38893899-f097-4a14-beed-24d840799dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248192530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tx_async_fifo_reset.2248192530
Directory /workspace/37.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/37.spi_device_txrx.219349058
Short name T828
Test name
Test status
Simulation time 23256204122 ps
CPU time 197.33 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 02:00:35 PM PST 23
Peak memory 257848 kb
Host smart-35981abc-9c57-431c-af79-4b56e8abfff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219349058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_txrx.219349058
Directory /workspace/37.spi_device_txrx/latest

Test location /workspace/coverage/default/37.spi_device_upload.1989043532
Short name T491
Test name
Test status
Simulation time 241660933 ps
CPU time 3.16 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:31 PM PST 23
Peak memory 219008 kb
Host smart-fc012d72-84e8-4822-afba-c385c13c2795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989043532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1989043532
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_abort.2293891734
Short name T907
Test name
Test status
Simulation time 23954581 ps
CPU time 0.74 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 206652 kb
Host smart-520be31b-7bb4-4ef8-b8f5-5bc5e8243f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293891734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_abort.2293891734
Directory /workspace/38.spi_device_abort/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1848681398
Short name T1738
Test name
Test status
Simulation time 33972881 ps
CPU time 0.74 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:18 PM PST 23
Peak memory 206356 kb
Host smart-85b4fba9-3feb-487d-9b53-3e0b9e3c3c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848681398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1848681398
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_bit_transfer.461881562
Short name T1784
Test name
Test status
Simulation time 375071300 ps
CPU time 2.46 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 216760 kb
Host smart-d6bd7a13-da8e-40f1-af6d-f345d545042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461881562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_bit_transfer.461881562
Directory /workspace/38.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/38.spi_device_byte_transfer.3971373396
Short name T1302
Test name
Test status
Simulation time 311439933 ps
CPU time 3.34 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:23 PM PST 23
Peak memory 216804 kb
Host smart-363b0ebb-7be9-447d-918d-61ba0308d5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971373396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_byte_transfer.3971373396
Directory /workspace/38.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2999890152
Short name T644
Test name
Test status
Simulation time 61474119 ps
CPU time 2.8 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 239536 kb
Host smart-6035a112-c96c-42f3-9dfe-029461aa4d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999890152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2999890152
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2157325459
Short name T1005
Test name
Test status
Simulation time 30127115 ps
CPU time 0.78 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 206584 kb
Host smart-ed316df2-0b20-48cb-ba26-3621e018a263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157325459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2157325459
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_dummy_item_extra_dly.2972098806
Short name T1284
Test name
Test status
Simulation time 41127999363 ps
CPU time 487.05 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 02:05:25 PM PST 23
Peak memory 299648 kb
Host smart-1e25899e-30bf-46a9-b641-4b664ccc2d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972098806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_dummy_item_extra_dly.2972098806
Directory /workspace/38.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/38.spi_device_extreme_fifo_size.1111393355
Short name T1003
Test name
Test status
Simulation time 10924720239 ps
CPU time 23.89 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:50 PM PST 23
Peak memory 233652 kb
Host smart-7075551d-b510-431d-9558-5bd3664cc846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111393355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_extreme_fifo_size.1111393355
Directory /workspace/38.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/38.spi_device_fifo_full.2285958923
Short name T1147
Test name
Test status
Simulation time 41009558194 ps
CPU time 542.82 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 02:06:27 PM PST 23
Peak memory 307024 kb
Host smart-1c4e583d-2b14-4a5b-b5a0-06b7ee049b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285958923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_full.2285958923
Directory /workspace/38.spi_device_fifo_full/latest

Test location /workspace/coverage/default/38.spi_device_fifo_underflow_overflow.1170179723
Short name T889
Test name
Test status
Simulation time 33613361717 ps
CPU time 231.99 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 02:01:12 PM PST 23
Peak memory 358628 kb
Host smart-11f3400a-3a88-45da-b212-ec17f3ebe6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170179723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_underflow_overf
low.1170179723
Directory /workspace/38.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.909175808
Short name T989
Test name
Test status
Simulation time 26508295841 ps
CPU time 119.24 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:59:18 PM PST 23
Peak memory 249764 kb
Host smart-b24f147f-3894-4ec3-9f54-8225873b30d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909175808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.909175808
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2049654889
Short name T1041
Test name
Test status
Simulation time 5358239241 ps
CPU time 59.75 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:58:17 PM PST 23
Peak memory 237452 kb
Host smart-862266c1-7d5e-4e7a-8394-66ea74b8571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049654889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2049654889
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2797779000
Short name T1584
Test name
Test status
Simulation time 14026707035 ps
CPU time 45.78 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:58:06 PM PST 23
Peak memory 238324 kb
Host smart-8a994f07-ed13-49bf-b0f9-22a86e9181a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797779000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2797779000
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3968209253
Short name T25
Test name
Test status
Simulation time 493268419 ps
CPU time 3 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 225016 kb
Host smart-94e9cdca-99a1-4cd0-b5f4-96cd6c3f07a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968209253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3968209253
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intr.245181881
Short name T892
Test name
Test status
Simulation time 35494919528 ps
CPU time 47.71 seconds
Started Dec 24 01:57:09 PM PST 23
Finished Dec 24 01:58:05 PM PST 23
Peak memory 237848 kb
Host smart-2fcc0c32-fc67-4c40-b1b6-cac2271ae256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245181881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intr.245181881
Directory /workspace/38.spi_device_intr/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4279693239
Short name T617
Test name
Test status
Simulation time 41325944 ps
CPU time 2.79 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:24 PM PST 23
Peak memory 234224 kb
Host smart-def62120-1c87-43e9-882b-dbd397bcb5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279693239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4279693239
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.163925305
Short name T850
Test name
Test status
Simulation time 1038502004 ps
CPU time 4.87 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 218656 kb
Host smart-f1dc89ea-b363-46dc-a8d0-7af6100c21d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163925305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.163925305
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2583830888
Short name T1509
Test name
Test status
Simulation time 5466248723 ps
CPU time 13.57 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 218256 kb
Host smart-4aa5308d-9edf-4198-a9b2-96cf7732e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583830888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2583830888
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_perf.2121723315
Short name T1277
Test name
Test status
Simulation time 2725433967 ps
CPU time 212.59 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 02:00:50 PM PST 23
Peak memory 265792 kb
Host smart-373ea5f3-13bf-450d-b6c1-6e26de78dc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121723315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_perf.2121723315
Directory /workspace/38.spi_device_perf/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3661622220
Short name T1115
Test name
Test status
Simulation time 10758742629 ps
CPU time 7.98 seconds
Started Dec 24 01:57:09 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 234816 kb
Host smart-0d799fd2-8a76-4681-94b9-737c3bd42574
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3661622220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3661622220
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_rx_async_fifo_reset.3362468343
Short name T700
Test name
Test status
Simulation time 85607454 ps
CPU time 0.94 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:19 PM PST 23
Peak memory 208480 kb
Host smart-1598b20a-c106-414b-bfbd-6672d3c84d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362468343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_async_fifo_reset.3362468343
Directory /workspace/38.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_rx_timeout.3084247503
Short name T1243
Test name
Test status
Simulation time 4967977196 ps
CPU time 7.2 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 01:57:26 PM PST 23
Peak memory 216924 kb
Host smart-08a090c4-aa4f-48f7-951c-f531d493b5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084247503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_timeout.3084247503
Directory /workspace/38.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/38.spi_device_smoke.2396432131
Short name T566
Test name
Test status
Simulation time 155498140 ps
CPU time 1.04 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:21 PM PST 23
Peak memory 207848 kb
Host smart-5def8b97-100c-4a71-8da7-285ffe902bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396432131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_smoke.2396432131
Directory /workspace/38.spi_device_smoke/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3120521284
Short name T728
Test name
Test status
Simulation time 58696034409 ps
CPU time 815.58 seconds
Started Dec 24 01:57:09 PM PST 23
Finished Dec 24 02:10:53 PM PST 23
Peak memory 356436 kb
Host smart-7307e9cd-0a10-47fe-9a05-b4ca5f77a0a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120521284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3120521284
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.862803938
Short name T755
Test name
Test status
Simulation time 15349256471 ps
CPU time 63.36 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:58:26 PM PST 23
Peak memory 216760 kb
Host smart-c1d04eb8-759d-4cd9-ad62-fc1b1c27d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862803938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.862803938
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.899776849
Short name T1586
Test name
Test status
Simulation time 6325027563 ps
CPU time 14.01 seconds
Started Dec 24 01:57:10 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 216932 kb
Host smart-38959179-756b-46d4-b36c-4729852a6ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899776849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.899776849
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2404975918
Short name T991
Test name
Test status
Simulation time 42893647 ps
CPU time 1.03 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 207868 kb
Host smart-bbea1bc9-8bd5-44c1-89e2-c28799862f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404975918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2404975918
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1582457791
Short name T577
Test name
Test status
Simulation time 148232915 ps
CPU time 0.86 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:19 PM PST 23
Peak memory 206840 kb
Host smart-b609555d-1fbf-4cff-a97c-3a2459a44e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582457791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1582457791
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tx_async_fifo_reset.2565881701
Short name T1043
Test name
Test status
Simulation time 72091759 ps
CPU time 0.78 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 01:57:20 PM PST 23
Peak memory 208704 kb
Host smart-e1b1d85f-e9fb-4ea9-a493-bb0d1c04ee6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565881701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tx_async_fifo_reset.2565881701
Directory /workspace/38.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/38.spi_device_txrx.560662576
Short name T696
Test name
Test status
Simulation time 25857544994 ps
CPU time 225.81 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 02:01:05 PM PST 23
Peak memory 242300 kb
Host smart-7eec059d-675e-4a60-877c-76094c8850d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560662576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_txrx.560662576
Directory /workspace/38.spi_device_txrx/latest

Test location /workspace/coverage/default/38.spi_device_upload.872704147
Short name T1498
Test name
Test status
Simulation time 358565234 ps
CPU time 2.38 seconds
Started Dec 24 01:57:07 PM PST 23
Finished Dec 24 01:57:19 PM PST 23
Peak memory 217012 kb
Host smart-fb555360-14db-42f7-90fe-de389e36a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872704147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.872704147
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_abort.2736047508
Short name T511
Test name
Test status
Simulation time 16015684 ps
CPU time 0.74 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:20 PM PST 23
Peak memory 206584 kb
Host smart-5f202e7b-8812-4a3c-a686-046c94a23b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736047508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_abort.2736047508
Directory /workspace/39.spi_device_abort/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3190092987
Short name T64
Test name
Test status
Simulation time 93082294 ps
CPU time 0.72 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 206484 kb
Host smart-caa01688-0df0-41a2-a5f6-35dc2f362a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190092987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3190092987
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_bit_transfer.2158772875
Short name T767
Test name
Test status
Simulation time 79665677 ps
CPU time 2.37 seconds
Started Dec 24 01:57:22 PM PST 23
Finished Dec 24 01:57:31 PM PST 23
Peak memory 216820 kb
Host smart-ef5c481e-c426-4fd9-9935-dedc70c44452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158772875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_bit_transfer.2158772875
Directory /workspace/39.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/39.spi_device_byte_transfer.1354451972
Short name T895
Test name
Test status
Simulation time 816041015 ps
CPU time 2.75 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:23 PM PST 23
Peak memory 216648 kb
Host smart-91fa04a5-03da-4efe-b9e2-942c9ecf15c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354451972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_byte_transfer.1354451972
Directory /workspace/39.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3057318835
Short name T1059
Test name
Test status
Simulation time 312870400 ps
CPU time 3.57 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 225140 kb
Host smart-11eb64ec-4e87-42b4-9107-97111dca8fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057318835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3057318835
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1513956460
Short name T1112
Test name
Test status
Simulation time 16259713 ps
CPU time 0.76 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 206580 kb
Host smart-c75eb3e4-3732-42cb-ad7a-46ab6cbbc3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513956460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1513956460
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_dummy_item_extra_dly.1929121803
Short name T1137
Test name
Test status
Simulation time 121337162107 ps
CPU time 255.91 seconds
Started Dec 24 01:57:12 PM PST 23
Finished Dec 24 02:01:36 PM PST 23
Peak memory 299016 kb
Host smart-1f39b7cc-954b-49b3-be0a-ba1ba7b50e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929121803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_dummy_item_extra_dly.1929121803
Directory /workspace/39.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/39.spi_device_extreme_fifo_size.2262608921
Short name T534
Test name
Test status
Simulation time 59238582286 ps
CPU time 734.57 seconds
Started Dec 24 01:57:11 PM PST 23
Finished Dec 24 02:09:33 PM PST 23
Peak memory 219040 kb
Host smart-fc7b3d94-5205-47f9-b85a-9d2860977b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262608921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_extreme_fifo_size.2262608921
Directory /workspace/39.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/39.spi_device_fifo_full.1775726712
Short name T1198
Test name
Test status
Simulation time 52225602961 ps
CPU time 1515.09 seconds
Started Dec 24 01:57:09 PM PST 23
Finished Dec 24 02:22:32 PM PST 23
Peak memory 271716 kb
Host smart-929c1114-ac8e-4e92-babd-1a1fbf422139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775726712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_full.1775726712
Directory /workspace/39.spi_device_fifo_full/latest

Test location /workspace/coverage/default/39.spi_device_fifo_underflow_overflow.2376117245
Short name T983
Test name
Test status
Simulation time 689390812362 ps
CPU time 223.97 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 02:01:04 PM PST 23
Peak memory 312500 kb
Host smart-839823fe-ce82-485f-8903-20ccec19e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376117245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_underflow_overf
low.2376117245
Directory /workspace/39.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.993356587
Short name T1404
Test name
Test status
Simulation time 22980354011 ps
CPU time 118.68 seconds
Started Dec 24 01:57:22 PM PST 23
Finished Dec 24 01:59:28 PM PST 23
Peak memory 249664 kb
Host smart-4958cd9d-22db-43ab-9204-235c4e46b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993356587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.993356587
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2593208448
Short name T1269
Test name
Test status
Simulation time 31389359077 ps
CPU time 68.33 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:58:36 PM PST 23
Peak memory 250216 kb
Host smart-a5f7032e-1c3f-4691-b698-8a25dd4edf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593208448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2593208448
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3338753338
Short name T1773
Test name
Test status
Simulation time 47689356020 ps
CPU time 90.38 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:58:58 PM PST 23
Peak memory 264064 kb
Host smart-a1d16114-a34d-451d-b641-7c2592ed0103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338753338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3338753338
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2215500003
Short name T967
Test name
Test status
Simulation time 480549246 ps
CPU time 15.21 seconds
Started Dec 24 01:57:23 PM PST 23
Finished Dec 24 01:57:45 PM PST 23
Peak memory 222620 kb
Host smart-4cd3de3a-7d68-48ca-85f7-8aa8c0765b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215500003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2215500003
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.885058212
Short name T269
Test name
Test status
Simulation time 5129294274 ps
CPU time 6.16 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:34 PM PST 23
Peak memory 220172 kb
Host smart-8c37567d-b470-4faa-8523-8987be21b3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885058212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.885058212
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intr.2805815217
Short name T691
Test name
Test status
Simulation time 16098643520 ps
CPU time 54.07 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:58:16 PM PST 23
Peak memory 232888 kb
Host smart-542e8a6f-0935-4fe7-8b2a-ecc73b217d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805815217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intr.2805815217
Directory /workspace/39.spi_device_intr/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.826795288
Short name T1775
Test name
Test status
Simulation time 10890920697 ps
CPU time 16.33 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:40 PM PST 23
Peak memory 253680 kb
Host smart-c6f532c9-853f-44d7-ad8f-e64b58b9f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826795288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.826795288
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1926397598
Short name T1205
Test name
Test status
Simulation time 802055833 ps
CPU time 9.27 seconds
Started Dec 24 01:57:19 PM PST 23
Finished Dec 24 01:57:36 PM PST 23
Peak memory 229148 kb
Host smart-81f74d84-18e1-4db8-8e3b-2a3fdfc56ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926397598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1926397598
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1704409893
Short name T1600
Test name
Test status
Simulation time 15055778869 ps
CPU time 14.86 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:39 PM PST 23
Peak memory 228336 kb
Host smart-53598921-197e-4f8c-93d1-cde99fd5d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704409893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1704409893
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_perf.3840700392
Short name T1385
Test name
Test status
Simulation time 33052835092 ps
CPU time 121.94 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:59:22 PM PST 23
Peak memory 263648 kb
Host smart-3a330b73-29b5-479a-915c-2715d8ac49f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840700392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_perf.3840700392
Directory /workspace/39.spi_device_perf/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2853662098
Short name T1293
Test name
Test status
Simulation time 1862890109 ps
CPU time 6.24 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 236076 kb
Host smart-48458f1c-2d0d-459b-af49-cfdf56492c2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2853662098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2853662098
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_rx_async_fifo_reset.3027474011
Short name T1536
Test name
Test status
Simulation time 48836734 ps
CPU time 0.95 seconds
Started Dec 24 01:57:19 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 208436 kb
Host smart-8d1ca661-68c5-4ea5-9d31-1da58d9706d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027474011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_async_fifo_reset.3027474011
Directory /workspace/39.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_rx_timeout.4224336969
Short name T1248
Test name
Test status
Simulation time 746731542 ps
CPU time 4.84 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:26 PM PST 23
Peak memory 216756 kb
Host smart-046a5e13-e65c-4963-a85e-d3af2956716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224336969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_timeout.4224336969
Directory /workspace/39.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/39.spi_device_smoke.3736643872
Short name T959
Test name
Test status
Simulation time 210768928 ps
CPU time 1.24 seconds
Started Dec 24 01:57:13 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 216816 kb
Host smart-82dd93e8-d0a7-4443-b685-54c0dd8ffa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736643872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_smoke.3736643872
Directory /workspace/39.spi_device_smoke/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4125264242
Short name T226
Test name
Test status
Simulation time 53342531161 ps
CPU time 304.57 seconds
Started Dec 24 01:57:22 PM PST 23
Finished Dec 24 02:02:33 PM PST 23
Peak memory 273536 kb
Host smart-0256ae78-b0f9-4e2d-9040-53547ef04a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125264242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4125264242
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2750561363
Short name T16
Test name
Test status
Simulation time 5566930999 ps
CPU time 43.38 seconds
Started Dec 24 01:57:23 PM PST 23
Finished Dec 24 01:58:13 PM PST 23
Peak memory 216928 kb
Host smart-fe55df73-3e5d-4685-b0b7-57d796d4eb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750561363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2750561363
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1224710702
Short name T962
Test name
Test status
Simulation time 1988612059 ps
CPU time 9.58 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 01:57:38 PM PST 23
Peak memory 216816 kb
Host smart-5b4d417f-5676-4d33-9932-dcf05c10ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224710702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1224710702
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2623086689
Short name T860
Test name
Test status
Simulation time 327182815 ps
CPU time 1.51 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 216884 kb
Host smart-6874d738-aaf0-4797-ac83-119335f1d3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623086689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2623086689
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3075169691
Short name T1060
Test name
Test status
Simulation time 46603561 ps
CPU time 0.9 seconds
Started Dec 24 01:57:19 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 206940 kb
Host smart-3ef613b4-9eca-4229-9b42-d0592fc4bd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075169691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3075169691
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tx_async_fifo_reset.1509287259
Short name T1148
Test name
Test status
Simulation time 31234325 ps
CPU time 0.8 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 208312 kb
Host smart-7022ec24-1eef-4e0b-b0c1-4f1ddf97acd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509287259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tx_async_fifo_reset.1509287259
Directory /workspace/39.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/39.spi_device_txrx.291866498
Short name T653
Test name
Test status
Simulation time 31234048366 ps
CPU time 191.33 seconds
Started Dec 24 01:57:09 PM PST 23
Finished Dec 24 02:00:29 PM PST 23
Peak memory 287944 kb
Host smart-1e1335a9-3412-4c44-95ee-0422396ade01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291866498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_txrx.291866498
Directory /workspace/39.spi_device_txrx/latest

Test location /workspace/coverage/default/39.spi_device_upload.2716991168
Short name T1053
Test name
Test status
Simulation time 6108570339 ps
CPU time 13.96 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 219964 kb
Host smart-5b7c7e71-b39e-4f68-abf8-7dfd5b946bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716991168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2716991168
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_abort.825155509
Short name T58
Test name
Test status
Simulation time 140265038 ps
CPU time 0.81 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:14 PM PST 23
Peak memory 206600 kb
Host smart-61f83ec3-b876-48fb-ba1d-4ca516b861e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825155509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_abort.825155509
Directory /workspace/4.spi_device_abort/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2412875736
Short name T1114
Test name
Test status
Simulation time 26050565 ps
CPU time 0.73 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 206480 kb
Host smart-4b338c0b-4b38-40a1-bf30-4001289ee9ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412875736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
412875736
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_bit_transfer.3875232898
Short name T903
Test name
Test status
Simulation time 2396679212 ps
CPU time 2.36 seconds
Started Dec 24 01:54:11 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 216976 kb
Host smart-7dcf1b93-15d5-4dd5-98ad-f2f3442b0c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875232898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_bit_transfer.3875232898
Directory /workspace/4.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/4.spi_device_byte_transfer.2458715894
Short name T535
Test name
Test status
Simulation time 110973937 ps
CPU time 3.11 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 01:54:13 PM PST 23
Peak memory 216868 kb
Host smart-61fd0b81-f9ff-4752-9ecb-62b351d4bb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458715894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_byte_transfer.2458715894
Directory /workspace/4.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1134401128
Short name T299
Test name
Test status
Simulation time 1307308060 ps
CPU time 6.5 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 01:54:17 PM PST 23
Peak memory 219284 kb
Host smart-7dec3aac-1ea9-411c-ad37-59f4f35edf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134401128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1134401128
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3752404949
Short name T842
Test name
Test status
Simulation time 67581282 ps
CPU time 0.77 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 207620 kb
Host smart-3321a29d-cfc9-4f18-a6ff-f1a45edfde31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752404949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3752404949
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_dummy_item_extra_dly.1784601692
Short name T59
Test name
Test status
Simulation time 87176058683 ps
CPU time 1743.48 seconds
Started Dec 24 01:54:11 PM PST 23
Finished Dec 24 02:23:22 PM PST 23
Peak memory 270516 kb
Host smart-a4e060ef-b535-4356-a448-4592862dd49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784601692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_dummy_item_extra_dly.1784601692
Directory /workspace/4.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/4.spi_device_extreme_fifo_size.4004662623
Short name T190
Test name
Test status
Simulation time 10259363624 ps
CPU time 29.38 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:51 PM PST 23
Peak memory 241516 kb
Host smart-41ba7e04-8891-40f9-964f-7d5ef5f86294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004662623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_extreme_fifo_size.4004662623
Directory /workspace/4.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/4.spi_device_fifo_full.1030108522
Short name T1306
Test name
Test status
Simulation time 18002660044 ps
CPU time 448.01 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 02:01:49 PM PST 23
Peak memory 304412 kb
Host smart-23f6b414-2bc8-43a0-9cf8-b04e48036b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030108522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_full.1030108522
Directory /workspace/4.spi_device_fifo_full/latest

Test location /workspace/coverage/default/4.spi_device_fifo_underflow_overflow.3733154608
Short name T1191
Test name
Test status
Simulation time 94637458203 ps
CPU time 438.96 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 02:01:39 PM PST 23
Peak memory 512592 kb
Host smart-e295b980-eb8f-421d-8270-9ebf6dca3764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733154608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_underflow_overfl
ow.3733154608
Directory /workspace/4.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3161169982
Short name T211
Test name
Test status
Simulation time 129893376560 ps
CPU time 340.38 seconds
Started Dec 24 01:54:05 PM PST 23
Finished Dec 24 01:59:47 PM PST 23
Peak memory 271512 kb
Host smart-e0140f0b-b5d3-433b-93d2-ef8c34f3823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161169982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3161169982
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.964458539
Short name T31
Test name
Test status
Simulation time 139712002147 ps
CPU time 289.42 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 01:58:59 PM PST 23
Peak memory 258968 kb
Host smart-33708506-d3e5-4887-97ba-d0e9d91791e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964458539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
964458539
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1194077883
Short name T1652
Test name
Test status
Simulation time 5761359616 ps
CPU time 16.92 seconds
Started Dec 24 01:54:06 PM PST 23
Finished Dec 24 01:54:25 PM PST 23
Peak memory 231936 kb
Host smart-9593c343-a466-4902-b1fa-31a2d64d08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194077883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1194077883
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2565512331
Short name T1415
Test name
Test status
Simulation time 1475424399 ps
CPU time 3.81 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 01:54:14 PM PST 23
Peak memory 224944 kb
Host smart-5263f66c-cf25-4825-90a2-cc11347cbc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565512331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2565512331
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intr.2814070166
Short name T1082
Test name
Test status
Simulation time 12151202036 ps
CPU time 46.5 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:55:00 PM PST 23
Peak memory 236448 kb
Host smart-e69775f2-e624-42fc-af73-b5d8451b2123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814070166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intr.2814070166
Directory /workspace/4.spi_device_intr/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1672547448
Short name T1189
Test name
Test status
Simulation time 1764901633 ps
CPU time 4.58 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:21 PM PST 23
Peak memory 240360 kb
Host smart-0655f754-7891-46ef-bb06-78d8b8e9fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672547448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1672547448
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.591103863
Short name T1504
Test name
Test status
Simulation time 15270035 ps
CPU time 1.04 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:13 PM PST 23
Peak memory 218848 kb
Host smart-54f39c84-a2b0-423e-86cb-e8d7a43bd95b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591103863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.591103863
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2184059107
Short name T799
Test name
Test status
Simulation time 24321152875 ps
CPU time 47.01 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:55:01 PM PST 23
Peak memory 254748 kb
Host smart-969fdd14-27eb-48dc-b54f-06af2610a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184059107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2184059107
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2981844396
Short name T1111
Test name
Test status
Simulation time 6228630737 ps
CPU time 6.13 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:18 PM PST 23
Peak memory 218680 kb
Host smart-761e8dd2-43d2-4fab-a2e4-d960ef0f528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981844396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2981844396
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_perf.862428035
Short name T508
Test name
Test status
Simulation time 24135020154 ps
CPU time 487.37 seconds
Started Dec 24 01:53:55 PM PST 23
Finished Dec 24 02:02:04 PM PST 23
Peak memory 240500 kb
Host smart-08585663-7d8d-4d84-9fc4-08cbb875134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862428035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_perf.862428035
Directory /workspace/4.spi_device_perf/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.249669942
Short name T1117
Test name
Test status
Simulation time 18254022 ps
CPU time 0.75 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 216692 kb
Host smart-f12490aa-e7ba-4d8b-a079-89d3ca928222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249669942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.249669942
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.215361694
Short name T584
Test name
Test status
Simulation time 6084433968 ps
CPU time 7.37 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 234316 kb
Host smart-ae45a975-23bd-43bb-bf52-7bf075c3d740
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=215361694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.215361694
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_rx_async_fifo_reset.3185071952
Short name T78
Test name
Test status
Simulation time 60950244 ps
CPU time 0.83 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 208376 kb
Host smart-e99f266a-5d2b-405f-941b-9b701e4b1e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185071952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_async_fifo_reset.3185071952
Directory /workspace/4.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_rx_timeout.2091510514
Short name T1665
Test name
Test status
Simulation time 2111433645 ps
CPU time 5.52 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:18 PM PST 23
Peak memory 216792 kb
Host smart-a1da5b55-ea64-4f6e-8722-ac938fc23374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091510514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_timeout.2091510514
Directory /workspace/4.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4094647468
Short name T94
Test name
Test status
Simulation time 53934428 ps
CPU time 0.96 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:14 PM PST 23
Peak memory 238124 kb
Host smart-3e014ed6-9fcc-491e-a49d-59a16d82480d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094647468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4094647468
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_smoke.468961399
Short name T1335
Test name
Test status
Simulation time 198652608 ps
CPU time 1.08 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 208080 kb
Host smart-1b0cd1ef-3581-45b9-ae06-b1644cf24bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468961399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_smoke.468961399
Directory /workspace/4.spi_device_smoke/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3780689339
Short name T1538
Test name
Test status
Simulation time 65772022805 ps
CPU time 1709.29 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 02:22:40 PM PST 23
Peak memory 362956 kb
Host smart-7f7af4df-f475-4d15-bf25-cade6b523db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780689339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3780689339
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3962259378
Short name T718
Test name
Test status
Simulation time 24029289647 ps
CPU time 39.25 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:52 PM PST 23
Peak memory 216956 kb
Host smart-8e50f2fa-901f-4186-b587-da021f783c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962259378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3962259378
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1428218506
Short name T798
Test name
Test status
Simulation time 4760934714 ps
CPU time 15.25 seconds
Started Dec 24 01:54:04 PM PST 23
Finished Dec 24 01:54:21 PM PST 23
Peak memory 216872 kb
Host smart-821db2c5-b2fd-4a56-85b6-e4900c8dec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428218506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1428218506
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2023332115
Short name T658
Test name
Test status
Simulation time 29660264 ps
CPU time 1.58 seconds
Started Dec 24 01:54:06 PM PST 23
Finished Dec 24 01:54:11 PM PST 23
Peak memory 216732 kb
Host smart-be9334fe-d9ec-4e85-ae72-18573e3e94ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023332115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2023332115
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4027304198
Short name T987
Test name
Test status
Simulation time 260605264 ps
CPU time 0.85 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 206868 kb
Host smart-41ec6afb-e52e-49d7-9c86-5b144d888c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027304198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4027304198
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tx_async_fifo_reset.1088748973
Short name T1138
Test name
Test status
Simulation time 28215323 ps
CPU time 0.84 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 208452 kb
Host smart-959f1a2d-88cc-4117-ad4e-ff16ea13a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088748973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tx_async_fifo_reset.1088748973
Directory /workspace/4.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/4.spi_device_txrx.3425990637
Short name T563
Test name
Test status
Simulation time 11001931303 ps
CPU time 114.47 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:56:19 PM PST 23
Peak memory 254224 kb
Host smart-040544b4-a9dc-4892-8b3c-883f616d0542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425990637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_txrx.3425990637
Directory /workspace/4.spi_device_txrx/latest

Test location /workspace/coverage/default/4.spi_device_upload.851512460
Short name T922
Test name
Test status
Simulation time 9327288507 ps
CPU time 12.99 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:25 PM PST 23
Peak memory 231864 kb
Host smart-2f7b8e90-f788-4e1e-95eb-881c9f753a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851512460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.851512460
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_abort.1085646891
Short name T1353
Test name
Test status
Simulation time 47948029 ps
CPU time 0.8 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 206356 kb
Host smart-85f0f8dd-c8f5-4bf7-8911-4fe70876436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085646891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_abort.1085646891
Directory /workspace/40.spi_device_abort/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4284973679
Short name T911
Test name
Test status
Simulation time 46007788 ps
CPU time 0.7 seconds
Started Dec 24 01:57:19 PM PST 23
Finished Dec 24 01:57:28 PM PST 23
Peak memory 206524 kb
Host smart-7d9e1f72-fd6d-4af7-b534-807bd4571508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284973679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4284973679
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_bit_transfer.1422867215
Short name T1145
Test name
Test status
Simulation time 288944899 ps
CPU time 2.91 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 01:57:31 PM PST 23
Peak memory 216836 kb
Host smart-81033089-29cc-4165-9b56-26ce76fd2b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422867215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_bit_transfer.1422867215
Directory /workspace/40.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/40.spi_device_byte_transfer.1422452748
Short name T520
Test name
Test status
Simulation time 334544395 ps
CPU time 2.72 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 216876 kb
Host smart-247eb633-658f-4cc7-9155-57194df848c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422452748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_byte_transfer.1422452748
Directory /workspace/40.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3465598394
Short name T267
Test name
Test status
Simulation time 374978644 ps
CPU time 3.58 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 238336 kb
Host smart-9d3dab78-8b89-49b6-9ac8-27b7506a8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465598394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3465598394
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3911581038
Short name T1024
Test name
Test status
Simulation time 18486645 ps
CPU time 0.78 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:23 PM PST 23
Peak memory 207592 kb
Host smart-6928f5cc-f7b8-445a-b3e0-e46c76edb9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911581038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3911581038
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_dummy_item_extra_dly.2515148466
Short name T1334
Test name
Test status
Simulation time 29699763730 ps
CPU time 64.14 seconds
Started Dec 24 01:57:23 PM PST 23
Finished Dec 24 01:58:33 PM PST 23
Peak memory 249580 kb
Host smart-15547d7b-3f49-493c-8d07-98083a51d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515148466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_dummy_item_extra_dly.2515148466
Directory /workspace/40.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/40.spi_device_extreme_fifo_size.2683637110
Short name T592
Test name
Test status
Simulation time 255668208062 ps
CPU time 839.23 seconds
Started Dec 24 01:57:22 PM PST 23
Finished Dec 24 02:11:28 PM PST 23
Peak memory 220232 kb
Host smart-50d47958-fb29-40cd-b88f-664f9e757312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683637110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_extreme_fifo_size.2683637110
Directory /workspace/40.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/40.spi_device_fifo_full.1396894671
Short name T1569
Test name
Test status
Simulation time 11392533859 ps
CPU time 149.18 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:59:56 PM PST 23
Peak memory 274260 kb
Host smart-10e8f46b-58bc-4cf8-92e0-8c8f662cafa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396894671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_full.1396894671
Directory /workspace/40.spi_device_fifo_full/latest

Test location /workspace/coverage/default/40.spi_device_fifo_underflow_overflow.3715269739
Short name T839
Test name
Test status
Simulation time 138444756760 ps
CPU time 299.54 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 02:02:28 PM PST 23
Peak memory 315316 kb
Host smart-3fbf9db2-096e-4029-979d-3d58c4fc6d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715269739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_underflow_overf
low.3715269739
Directory /workspace/40.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.150878409
Short name T331
Test name
Test status
Simulation time 33620585698 ps
CPU time 195.53 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 02:00:37 PM PST 23
Peak memory 257896 kb
Host smart-14c6ba32-8074-4733-a72d-52a1f1f90869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150878409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.150878409
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4099986903
Short name T246
Test name
Test status
Simulation time 15631026799 ps
CPU time 20.75 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:45 PM PST 23
Peak memory 236416 kb
Host smart-114b36d1-33bd-4d0c-b13f-7cb210fb7c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099986903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4099986903
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2717650990
Short name T1343
Test name
Test status
Simulation time 41400469 ps
CPU time 2.4 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:30 PM PST 23
Peak memory 218348 kb
Host smart-3d4c9705-ba9d-4dcd-aa06-eb4cb71f25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717650990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2717650990
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intr.2630938465
Short name T837
Test name
Test status
Simulation time 8410663846 ps
CPU time 24.05 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:51 PM PST 23
Peak memory 218292 kb
Host smart-4e4f7bcb-f724-4252-bde7-19c307c33426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630938465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intr.2630938465
Directory /workspace/40.spi_device_intr/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1454982212
Short name T931
Test name
Test status
Simulation time 3295216356 ps
CPU time 14.7 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:40 PM PST 23
Peak memory 248948 kb
Host smart-c7f4ad57-cc97-4f12-8707-618a91f82184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454982212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1454982212
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3263389534
Short name T291
Test name
Test status
Simulation time 2258566667 ps
CPU time 5.18 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 219496 kb
Host smart-b8d46f99-b33b-4fa9-9d0f-3998cdb3464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263389534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3263389534
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2209338362
Short name T1206
Test name
Test status
Simulation time 98869174 ps
CPU time 2.63 seconds
Started Dec 24 01:57:15 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 218676 kb
Host smart-3a7d9227-3d2e-450e-a359-ea53f53084f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209338362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2209338362
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_perf.3261065101
Short name T261
Test name
Test status
Simulation time 35212381911 ps
CPU time 783.97 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 02:10:32 PM PST 23
Peak memory 273876 kb
Host smart-299de292-00c7-4747-b43c-f107816f5107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261065101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_perf.3261065101
Directory /workspace/40.spi_device_perf/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1773689469
Short name T1521
Test name
Test status
Simulation time 775197886 ps
CPU time 3.93 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:25 PM PST 23
Peak memory 234752 kb
Host smart-ac1276f4-9dac-45b4-9861-cf4892683a5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1773689469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1773689469
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_rx_async_fifo_reset.3068188955
Short name T1247
Test name
Test status
Simulation time 86275980 ps
CPU time 0.9 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 208372 kb
Host smart-cd6708a6-b311-49b9-8701-65f6ea06e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068188955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_async_fifo_reset.3068188955
Directory /workspace/40.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_rx_timeout.2184093674
Short name T1456
Test name
Test status
Simulation time 1528629503 ps
CPU time 6.83 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:33 PM PST 23
Peak memory 216860 kb
Host smart-bc87dd46-07fb-44d9-8abb-4c9816c1bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184093674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_timeout.2184093674
Directory /workspace/40.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/40.spi_device_smoke.1802801705
Short name T470
Test name
Test status
Simulation time 20500469 ps
CPU time 1.22 seconds
Started Dec 24 01:57:20 PM PST 23
Finished Dec 24 01:57:29 PM PST 23
Peak memory 216712 kb
Host smart-dbffd309-ae30-47e7-b62a-4097ed21a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802801705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_smoke.1802801705
Directory /workspace/40.spi_device_smoke/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2403151048
Short name T1611
Test name
Test status
Simulation time 80545861178 ps
CPU time 903.53 seconds
Started Dec 24 01:57:18 PM PST 23
Finished Dec 24 02:12:30 PM PST 23
Peak memory 391128 kb
Host smart-b8d7d4fc-c3ff-4b2a-ba66-d13e361ae3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403151048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2403151048
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1968525617
Short name T560
Test name
Test status
Simulation time 2434991732 ps
CPU time 23.34 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:50 PM PST 23
Peak memory 216916 kb
Host smart-b6889d92-db4d-4f49-8b16-22f9b182b6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968525617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1968525617
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3776223184
Short name T1058
Test name
Test status
Simulation time 1972173648 ps
CPU time 5.67 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 216824 kb
Host smart-9626d3c2-e1a5-4731-acc6-b860f256d93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776223184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3776223184
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.859848052
Short name T1046
Test name
Test status
Simulation time 89602941 ps
CPU time 1.04 seconds
Started Dec 24 01:57:16 PM PST 23
Finished Dec 24 01:57:27 PM PST 23
Peak memory 207564 kb
Host smart-b87197a4-2c4a-4c8d-a849-db2a151d5514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859848052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.859848052
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4135424600
Short name T1734
Test name
Test status
Simulation time 151771479 ps
CPU time 0.91 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 01:57:22 PM PST 23
Peak memory 206844 kb
Host smart-332ce88a-9deb-4476-9697-17c7ab5fa806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135424600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4135424600
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tx_async_fifo_reset.1816607416
Short name T625
Test name
Test status
Simulation time 15017862 ps
CPU time 0.78 seconds
Started Dec 24 01:57:17 PM PST 23
Finished Dec 24 01:57:27 PM PST 23
Peak memory 208476 kb
Host smart-9f0c7cb6-2e84-472f-b610-c769414f2a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816607416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tx_async_fifo_reset.1816607416
Directory /workspace/40.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/40.spi_device_txrx.730421351
Short name T1080
Test name
Test status
Simulation time 28884476271 ps
CPU time 428.92 seconds
Started Dec 24 01:57:14 PM PST 23
Finished Dec 24 02:04:30 PM PST 23
Peak memory 285956 kb
Host smart-bd2b9e32-c306-4198-922f-d6491a8835b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730421351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_txrx.730421351
Directory /workspace/40.spi_device_txrx/latest

Test location /workspace/coverage/default/40.spi_device_upload.1532120083
Short name T1790
Test name
Test status
Simulation time 25878920559 ps
CPU time 14.41 seconds
Started Dec 24 01:57:21 PM PST 23
Finished Dec 24 01:57:43 PM PST 23
Peak memory 225156 kb
Host smart-6d1e9285-0a6e-4e88-9c10-5bec55adbdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532120083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1532120083
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_abort.24453637
Short name T1
Test name
Test status
Simulation time 15416415 ps
CPU time 0.75 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:39 PM PST 23
Peak memory 206580 kb
Host smart-c8a70816-881f-4db0-8972-fd9d1f36b795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24453637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_abort.24453637
Directory /workspace/41.spi_device_abort/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2464231927
Short name T1746
Test name
Test status
Simulation time 22337456 ps
CPU time 0.73 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 206484 kb
Host smart-a409459b-8dab-4cda-adcd-6dfba726417f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464231927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2464231927
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_bit_transfer.2624623504
Short name T615
Test name
Test status
Simulation time 1051089165 ps
CPU time 2.89 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 216776 kb
Host smart-3cdd0b77-5c1b-4a13-9fb1-c72c0dc89dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624623504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_bit_transfer.2624623504
Directory /workspace/41.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/41.spi_device_byte_transfer.881244716
Short name T516
Test name
Test status
Simulation time 169990036 ps
CPU time 2.85 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:43 PM PST 23
Peak memory 216892 kb
Host smart-76c28189-6773-42de-8ee8-1c318dff6046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881244716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_byte_transfer.881244716
Directory /workspace/41.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.582394463
Short name T1162
Test name
Test status
Simulation time 402362540 ps
CPU time 6.32 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 239396 kb
Host smart-a8092e4e-5c2c-4ce6-8d2a-4da02be02302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582394463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.582394463
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.561774663
Short name T1624
Test name
Test status
Simulation time 43220990 ps
CPU time 0.78 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:39 PM PST 23
Peak memory 207608 kb
Host smart-993368dd-09e6-46d3-9742-6dc1577fed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561774663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.561774663
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_dummy_item_extra_dly.3047020235
Short name T496
Test name
Test status
Simulation time 101405989936 ps
CPU time 1463.64 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 02:22:00 PM PST 23
Peak memory 241528 kb
Host smart-7a2c7329-aba6-44fa-ae47-1555a2b1c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047020235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_dummy_item_extra_dly.3047020235
Directory /workspace/41.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/41.spi_device_extreme_fifo_size.2516711263
Short name T1545
Test name
Test status
Simulation time 166549018163 ps
CPU time 782.46 seconds
Started Dec 24 01:57:34 PM PST 23
Finished Dec 24 02:10:38 PM PST 23
Peak memory 219148 kb
Host smart-9cac79d0-2b64-4929-9202-e38f5f9daf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516711263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_extreme_fifo_size.2516711263
Directory /workspace/41.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/41.spi_device_fifo_full.1679198191
Short name T1258
Test name
Test status
Simulation time 13845069218 ps
CPU time 741.86 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 02:10:05 PM PST 23
Peak memory 288340 kb
Host smart-72c52c97-e967-4a43-99e4-a8dda279b136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679198191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_full.1679198191
Directory /workspace/41.spi_device_fifo_full/latest

Test location /workspace/coverage/default/41.spi_device_fifo_underflow_overflow.513178390
Short name T1068
Test name
Test status
Simulation time 33185091574 ps
CPU time 212.25 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 02:01:16 PM PST 23
Peak memory 378124 kb
Host smart-2de11ff9-7fea-4918-991a-e46de465b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513178390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_underflow_overfl
ow.513178390
Directory /workspace/41.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1374119841
Short name T1653
Test name
Test status
Simulation time 11522644834 ps
CPU time 64.45 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:58:46 PM PST 23
Peak memory 241512 kb
Host smart-4501f9ba-2e53-45a4-9a81-65ee58534624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374119841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1374119841
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3684237230
Short name T1402
Test name
Test status
Simulation time 27283935555 ps
CPU time 183.09 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 02:00:44 PM PST 23
Peak memory 254572 kb
Host smart-e6cada2e-fcce-4264-9d66-62835404f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684237230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3684237230
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1216090506
Short name T1750
Test name
Test status
Simulation time 2786699947 ps
CPU time 23.13 seconds
Started Dec 24 01:57:33 PM PST 23
Finished Dec 24 01:57:58 PM PST 23
Peak memory 233868 kb
Host smart-aaab52e2-3dd9-4d1d-a1f7-8e3db64e96a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216090506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1216090506
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.855068915
Short name T1553
Test name
Test status
Simulation time 1831644427 ps
CPU time 7.3 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:57:50 PM PST 23
Peak memory 220252 kb
Host smart-cfc0e926-4887-45f1-90ad-4a06799ff91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855068915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.855068915
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intr.1700280930
Short name T1000
Test name
Test status
Simulation time 48235635997 ps
CPU time 49.51 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 241568 kb
Host smart-b40fb816-5936-4e13-8e36-bcde3449e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700280930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intr.1700280930
Directory /workspace/41.spi_device_intr/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3656353786
Short name T210
Test name
Test status
Simulation time 15665473312 ps
CPU time 26.93 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:58:08 PM PST 23
Peak memory 234484 kb
Host smart-1f1d4755-b288-4835-a007-6c6c107b1e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656353786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3656353786
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4175727265
Short name T288
Test name
Test status
Simulation time 7221496471 ps
CPU time 23.93 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:58:05 PM PST 23
Peak memory 229680 kb
Host smart-00971ba7-f436-4934-b3d6-6f85316fe8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175727265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4175727265
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3057616187
Short name T1239
Test name
Test status
Simulation time 1017766201 ps
CPU time 9 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 244208 kb
Host smart-138901e7-9a18-4f87-9d83-b745d1b9f5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057616187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3057616187
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_perf.2050805244
Short name T1181
Test name
Test status
Simulation time 31975028363 ps
CPU time 363.18 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 02:03:45 PM PST 23
Peak memory 270888 kb
Host smart-c15bda00-d310-48f8-870a-54a04e5f7f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050805244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_perf.2050805244
Directory /workspace/41.spi_device_perf/latest

Test location /workspace/coverage/default/41.spi_device_rx_async_fifo_reset.245475174
Short name T1155
Test name
Test status
Simulation time 35730173 ps
CPU time 0.84 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:57:43 PM PST 23
Peak memory 208480 kb
Host smart-57722589-8716-460b-85ec-50d456b18064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245475174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_async_fifo_reset.245475174
Directory /workspace/41.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_rx_timeout.1472454507
Short name T1312
Test name
Test status
Simulation time 414501578 ps
CPU time 4.44 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 216692 kb
Host smart-f3566a77-6219-4523-91a5-30bca48d8ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472454507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_timeout.1472454507
Directory /workspace/41.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/41.spi_device_smoke.1977266715
Short name T713
Test name
Test status
Simulation time 32250248 ps
CPU time 1.22 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:57:43 PM PST 23
Peak memory 216800 kb
Host smart-cebcbb51-3acd-4c89-b97f-60a8347de79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977266715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_smoke.1977266715
Directory /workspace/41.spi_device_smoke/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3683893102
Short name T1430
Test name
Test status
Simulation time 4972266674 ps
CPU time 23.43 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:58:02 PM PST 23
Peak memory 216864 kb
Host smart-ea9f4cc3-5024-4357-8f90-837fbfaf172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683893102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3683893102
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3304956016
Short name T109
Test name
Test status
Simulation time 5588553028 ps
CPU time 13.17 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:53 PM PST 23
Peak memory 216920 kb
Host smart-7433333c-4d07-47bc-9564-a8b0ea5cc042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304956016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3304956016
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1336909023
Short name T909
Test name
Test status
Simulation time 58253366 ps
CPU time 1.15 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 208556 kb
Host smart-f783e671-6bbd-4307-b143-4f7c6347b789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336909023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1336909023
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3998338523
Short name T1237
Test name
Test status
Simulation time 57126301 ps
CPU time 0.94 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 208036 kb
Host smart-5afdbb87-9769-4f16-b33a-0b6a68bfaca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998338523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3998338523
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tx_async_fifo_reset.106780472
Short name T692
Test name
Test status
Simulation time 14889398 ps
CPU time 0.79 seconds
Started Dec 24 01:57:34 PM PST 23
Finished Dec 24 01:57:37 PM PST 23
Peak memory 208448 kb
Host smart-e3e59452-44b1-4e74-9707-9316b972f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106780472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tx_async_fifo_reset.106780472
Directory /workspace/41.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/41.spi_device_txrx.436301541
Short name T523
Test name
Test status
Simulation time 10078722994 ps
CPU time 105.61 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:59:24 PM PST 23
Peak memory 255968 kb
Host smart-82d69ad0-2452-499f-aa81-e1c705caa4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436301541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_txrx.436301541
Directory /workspace/41.spi_device_txrx/latest

Test location /workspace/coverage/default/41.spi_device_upload.1552107586
Short name T1250
Test name
Test status
Simulation time 1646594988 ps
CPU time 8.17 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 233400 kb
Host smart-796dcea9-7cec-4892-98d4-e7e2aa0b728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552107586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1552107586
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_abort.1382342131
Short name T1678
Test name
Test status
Simulation time 15675670 ps
CPU time 0.79 seconds
Started Dec 24 01:57:34 PM PST 23
Finished Dec 24 01:57:36 PM PST 23
Peak memory 206640 kb
Host smart-b0d5452f-6fc6-4668-aa0b-ff7963613a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382342131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_abort.1382342131
Directory /workspace/42.spi_device_abort/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2381146933
Short name T1212
Test name
Test status
Simulation time 14218001 ps
CPU time 0.71 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:57:42 PM PST 23
Peak memory 206388 kb
Host smart-34ddd0df-2063-4e95-abca-236ab130cb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381146933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2381146933
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_bit_transfer.1240407955
Short name T481
Test name
Test status
Simulation time 1133156977 ps
CPU time 3.02 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 216908 kb
Host smart-8a127376-1fd6-40e2-8154-e1324b6664c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240407955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_bit_transfer.1240407955
Directory /workspace/42.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/42.spi_device_byte_transfer.2579596988
Short name T908
Test name
Test status
Simulation time 79808181 ps
CPU time 2.64 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:39 PM PST 23
Peak memory 216792 kb
Host smart-92c34c24-3042-4a01-9d98-530081e0c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579596988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_byte_transfer.2579596988
Directory /workspace/42.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2312352044
Short name T1174
Test name
Test status
Simulation time 5963538195 ps
CPU time 4.38 seconds
Started Dec 24 01:57:40 PM PST 23
Finished Dec 24 01:57:49 PM PST 23
Peak memory 220068 kb
Host smart-15d1f742-4e46-49a7-bcaf-494d7a546bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312352044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2312352044
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3172529280
Short name T1507
Test name
Test status
Simulation time 53039755 ps
CPU time 0.73 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:39 PM PST 23
Peak memory 207132 kb
Host smart-f73ab190-1810-48b2-af05-c96e71835414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172529280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3172529280
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_dummy_item_extra_dly.875894379
Short name T1420
Test name
Test status
Simulation time 94583413401 ps
CPU time 394.11 seconds
Started Dec 24 01:57:40 PM PST 23
Finished Dec 24 02:04:19 PM PST 23
Peak memory 309256 kb
Host smart-53cc15ec-2265-4dfd-b385-09837496fed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875894379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_dummy_item_extra_dly.875894379
Directory /workspace/42.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/42.spi_device_extreme_fifo_size.4130314931
Short name T635
Test name
Test status
Simulation time 2610531955 ps
CPU time 61.14 seconds
Started Dec 24 01:57:34 PM PST 23
Finished Dec 24 01:58:36 PM PST 23
Peak memory 234624 kb
Host smart-1f5ec4bc-790c-4908-9540-c89474ecf2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130314931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_extreme_fifo_size.4130314931
Directory /workspace/42.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/42.spi_device_fifo_full.1946714044
Short name T969
Test name
Test status
Simulation time 971198699659 ps
CPU time 1123.2 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 02:16:21 PM PST 23
Peak memory 273148 kb
Host smart-8c29c528-adf6-4d00-a77e-6a8224e75f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946714044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_full.1946714044
Directory /workspace/42.spi_device_fifo_full/latest

Test location /workspace/coverage/default/42.spi_device_fifo_underflow_overflow.1414392420
Short name T667
Test name
Test status
Simulation time 63958600500 ps
CPU time 765.1 seconds
Started Dec 24 01:57:41 PM PST 23
Finished Dec 24 02:10:30 PM PST 23
Peak memory 671356 kb
Host smart-1748c5de-a415-4283-a7c3-585b61f18c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414392420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_underflow_overf
low.1414392420
Directory /workspace/42.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1966912279
Short name T1233
Test name
Test status
Simulation time 703218445 ps
CPU time 8.5 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 229668 kb
Host smart-20fca46f-7e39-4828-81fc-1cbb45ab5731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966912279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1966912279
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4153657408
Short name T1755
Test name
Test status
Simulation time 187015137396 ps
CPU time 507.13 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 02:06:08 PM PST 23
Peak memory 266700 kb
Host smart-59840f25-baf1-483e-aad7-ec4b78577188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153657408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4153657408
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1460077370
Short name T738
Test name
Test status
Simulation time 79409066345 ps
CPU time 168.41 seconds
Started Dec 24 01:57:41 PM PST 23
Finished Dec 24 02:00:33 PM PST 23
Peak memory 250760 kb
Host smart-485dfcf6-5555-49a9-b8a8-992bbd53f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460077370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1460077370
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3833021273
Short name T1616
Test name
Test status
Simulation time 3097328841 ps
CPU time 11.76 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:55 PM PST 23
Peak memory 238784 kb
Host smart-ccfa3621-e526-4293-8094-ea2164261027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833021273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3833021273
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intr.2615583546
Short name T1088
Test name
Test status
Simulation time 4205857899 ps
CPU time 18.11 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:57 PM PST 23
Peak memory 220028 kb
Host smart-d08f7c5e-f381-4cc9-b80b-1b7edecd8a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615583546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intr.2615583546
Directory /workspace/42.spi_device_intr/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1335847721
Short name T1278
Test name
Test status
Simulation time 8076497656 ps
CPU time 23.48 seconds
Started Dec 24 01:57:40 PM PST 23
Finished Dec 24 01:58:08 PM PST 23
Peak memory 224636 kb
Host smart-533469a1-0921-496e-9bd7-40bcc1a0aa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335847721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1335847721
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.37560642
Short name T241
Test name
Test status
Simulation time 6106680240 ps
CPU time 19.49 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:58:03 PM PST 23
Peak memory 241488 kb
Host smart-83aa760c-89de-4c56-b2a4-0caaf2a0fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37560642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.37560642
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3744384051
Short name T1271
Test name
Test status
Simulation time 10243928405 ps
CPU time 10.05 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:57:53 PM PST 23
Peak memory 241648 kb
Host smart-98db44da-dd41-4d62-ad63-724265230b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744384051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3744384051
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_perf.4076274175
Short name T1470
Test name
Test status
Simulation time 37848477341 ps
CPU time 898.81 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 02:12:37 PM PST 23
Peak memory 283712 kb
Host smart-2a333f3c-b634-46cb-845c-b0626d39fd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076274175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_perf.4076274175
Directory /workspace/42.spi_device_perf/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1992923014
Short name T844
Test name
Test status
Simulation time 2141817492 ps
CPU time 4.92 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 234164 kb
Host smart-8e3c87af-d4af-4eb3-a8e3-e438dce71d07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1992923014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1992923014
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_rx_async_fifo_reset.4094896748
Short name T1096
Test name
Test status
Simulation time 265560687 ps
CPU time 0.85 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:45 PM PST 23
Peak memory 208444 kb
Host smart-ec659293-8380-4f21-8ded-a1265e088efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094896748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_async_fifo_reset.4094896748
Directory /workspace/42.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_rx_timeout.1867980451
Short name T1505
Test name
Test status
Simulation time 895106852 ps
CPU time 6.34 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:57:48 PM PST 23
Peak memory 216768 kb
Host smart-df74d81d-1254-43a6-a54f-0361af09fc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867980451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_timeout.1867980451
Directory /workspace/42.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/42.spi_device_smoke.3513175134
Short name T527
Test name
Test status
Simulation time 91065945 ps
CPU time 1.19 seconds
Started Dec 24 01:57:40 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 216468 kb
Host smart-fe7f6fa2-157b-4393-9082-72dd38dfaf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513175134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_smoke.3513175134
Directory /workspace/42.spi_device_smoke/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2866763404
Short name T315
Test name
Test status
Simulation time 853291051432 ps
CPU time 2207.39 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 02:34:25 PM PST 23
Peak memory 376884 kb
Host smart-3cc2b196-bbd6-44b0-a36e-c7918b9da270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866763404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2866763404
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2587438360
Short name T641
Test name
Test status
Simulation time 3894768766 ps
CPU time 57.41 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:58:34 PM PST 23
Peak memory 216976 kb
Host smart-489ebe45-62b3-437c-b580-9e7f3f155666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587438360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2587438360
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2680923361
Short name T1038
Test name
Test status
Simulation time 773554734 ps
CPU time 2.5 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 216576 kb
Host smart-89063795-c6fc-409e-8c1c-7c008081bbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680923361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2680923361
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2872577373
Short name T1044
Test name
Test status
Simulation time 235099171 ps
CPU time 1.08 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:42 PM PST 23
Peak memory 208356 kb
Host smart-a428c3c2-a78c-42fb-b0fb-028bc5b1c0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872577373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2872577373
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3353392400
Short name T801
Test name
Test status
Simulation time 79693278 ps
CPU time 0.78 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:42 PM PST 23
Peak memory 206912 kb
Host smart-f104c2c5-3a5a-436f-afd7-af80c0009d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353392400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3353392400
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tx_async_fifo_reset.1538834126
Short name T708
Test name
Test status
Simulation time 30227021 ps
CPU time 0.8 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:57:42 PM PST 23
Peak memory 208440 kb
Host smart-38c8d838-f5a7-4abd-b1e6-7d0595e484ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538834126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tx_async_fifo_reset.1538834126
Directory /workspace/42.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/42.spi_device_txrx.3720383145
Short name T779
Test name
Test status
Simulation time 115499127495 ps
CPU time 228.6 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 02:01:29 PM PST 23
Peak memory 266292 kb
Host smart-33e39c17-6b4b-453a-a0dd-0e620b6be99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720383145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_txrx.3720383145
Directory /workspace/42.spi_device_txrx/latest

Test location /workspace/coverage/default/42.spi_device_upload.1325953422
Short name T1466
Test name
Test status
Simulation time 13316930092 ps
CPU time 22.48 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:58:03 PM PST 23
Peak memory 233360 kb
Host smart-e942673c-3ef6-4ecc-9e6e-e8aa03e27bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325953422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1325953422
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_abort.2023839642
Short name T761
Test name
Test status
Simulation time 13016718 ps
CPU time 0.74 seconds
Started Dec 24 01:57:33 PM PST 23
Finished Dec 24 01:57:35 PM PST 23
Peak memory 206648 kb
Host smart-39483a59-79bf-4cef-b8be-3a0701e347e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023839642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_abort.2023839642
Directory /workspace/43.spi_device_abort/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.66902667
Short name T1241
Test name
Test status
Simulation time 80211689 ps
CPU time 0.71 seconds
Started Dec 24 01:57:44 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 206524 kb
Host smart-98f322fa-16d9-4bdd-8485-cc16332ed1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66902667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.66902667
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_bit_transfer.2511399292
Short name T1405
Test name
Test status
Simulation time 278818687 ps
CPU time 2.33 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:57:43 PM PST 23
Peak memory 216908 kb
Host smart-d8b904ac-e2dd-419d-8764-1b4acc3cc05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511399292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_bit_transfer.2511399292
Directory /workspace/43.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/43.spi_device_byte_transfer.1195487891
Short name T1227
Test name
Test status
Simulation time 763655511 ps
CPU time 2.97 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:41 PM PST 23
Peak memory 216816 kb
Host smart-d8b44192-3095-4632-8c08-a246572551a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195487891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_byte_transfer.1195487891
Directory /workspace/43.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2926534859
Short name T985
Test name
Test status
Simulation time 222176465 ps
CPU time 4.63 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:57:46 PM PST 23
Peak memory 238248 kb
Host smart-dd18fc79-9ba5-44e7-ae75-56295af4970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926534859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2926534859
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2904845780
Short name T1573
Test name
Test status
Simulation time 17445423 ps
CPU time 0.76 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 206504 kb
Host smart-337bfd38-440e-483f-b344-083e355892cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904845780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2904845780
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_dummy_item_extra_dly.1720417582
Short name T1557
Test name
Test status
Simulation time 11905139630 ps
CPU time 102.22 seconds
Started Dec 24 01:57:40 PM PST 23
Finished Dec 24 01:59:27 PM PST 23
Peak memory 239552 kb
Host smart-91f472f7-4b65-4e56-a66f-6f208191d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720417582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_dummy_item_extra_dly.1720417582
Directory /workspace/43.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/43.spi_device_extreme_fifo_size.2744340909
Short name T259
Test name
Test status
Simulation time 124347063066 ps
CPU time 2159.58 seconds
Started Dec 24 01:57:40 PM PST 23
Finished Dec 24 02:33:44 PM PST 23
Peak memory 220088 kb
Host smart-948a24f0-9dd1-4e84-b46c-265872918975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744340909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_extreme_fifo_size.2744340909
Directory /workspace/43.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/43.spi_device_fifo_full.3739504080
Short name T1720
Test name
Test status
Simulation time 14955775301 ps
CPU time 757.41 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 02:10:19 PM PST 23
Peak memory 301792 kb
Host smart-04281b33-46fb-484d-a45c-e761ced42866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739504080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_full.3739504080
Directory /workspace/43.spi_device_fifo_full/latest

Test location /workspace/coverage/default/43.spi_device_fifo_underflow_overflow.1499031335
Short name T1327
Test name
Test status
Simulation time 20597731741 ps
CPU time 232.42 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 02:01:34 PM PST 23
Peak memory 355864 kb
Host smart-cb1ec9d9-e12d-408c-81ec-321cdf848bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499031335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_underflow_overf
low.1499031335
Directory /workspace/43.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.200447746
Short name T751
Test name
Test status
Simulation time 1402213648 ps
CPU time 7.23 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:51 PM PST 23
Peak memory 239792 kb
Host smart-6b860585-f0be-44c4-8d88-17d3f11feff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200447746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.200447746
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3489193296
Short name T336
Test name
Test status
Simulation time 2154530276 ps
CPU time 19.02 seconds
Started Dec 24 01:57:44 PM PST 23
Finished Dec 24 01:58:05 PM PST 23
Peak memory 235692 kb
Host smart-6f5cc220-5387-4292-bfa4-d57b2b2564f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489193296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3489193296
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1565028657
Short name T1030
Test name
Test status
Simulation time 13066380891 ps
CPU time 33.23 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:58:15 PM PST 23
Peak memory 237448 kb
Host smart-441f47c8-978d-4c90-83ed-cd043c44a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565028657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1565028657
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.798494653
Short name T98
Test name
Test status
Simulation time 118562732 ps
CPU time 2.64 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 218628 kb
Host smart-d3bdb52f-fe3c-4d39-871c-65b6a6e261d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798494653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.798494653
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intr.1490141170
Short name T494
Test name
Test status
Simulation time 21385042263 ps
CPU time 38.44 seconds
Started Dec 24 01:57:36 PM PST 23
Finished Dec 24 01:58:17 PM PST 23
Peak memory 232808 kb
Host smart-451c23ff-a9ae-4c35-8ce4-fde1ccd95d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490141170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intr.1490141170
Directory /workspace/43.spi_device_intr/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3976920304
Short name T304
Test name
Test status
Simulation time 2895205197 ps
CPU time 8.04 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:52 PM PST 23
Peak memory 239780 kb
Host smart-283f67b0-e433-4116-a595-1c7f2cb3d19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976920304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3976920304
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3635042838
Short name T1214
Test name
Test status
Simulation time 2636923613 ps
CPU time 7.68 seconds
Started Dec 24 01:57:42 PM PST 23
Finished Dec 24 01:57:53 PM PST 23
Peak memory 219744 kb
Host smart-9a39fac3-b8d7-4ae4-8e34-df6730f0b315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635042838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3635042838
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2874747302
Short name T285
Test name
Test status
Simulation time 18571720050 ps
CPU time 49.52 seconds
Started Dec 24 01:57:42 PM PST 23
Finished Dec 24 01:58:35 PM PST 23
Peak memory 234856 kb
Host smart-e61bd444-1138-4c6c-ae59-b680f57ac32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874747302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2874747302
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_perf.3848202020
Short name T1771
Test name
Test status
Simulation time 38971543316 ps
CPU time 212.88 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 02:01:15 PM PST 23
Peak memory 273536 kb
Host smart-c2a5506a-0f1c-46dc-9075-09e640ff50f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848202020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_perf.3848202020
Directory /workspace/43.spi_device_perf/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2582998741
Short name T1264
Test name
Test status
Simulation time 5879063450 ps
CPU time 6.7 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:50 PM PST 23
Peak memory 218964 kb
Host smart-60801766-e76b-4367-ba2a-d200615a64a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2582998741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2582998741
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_rx_async_fifo_reset.11840669
Short name T1443
Test name
Test status
Simulation time 234966032 ps
CPU time 0.86 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:39 PM PST 23
Peak memory 208428 kb
Host smart-e7fe2764-44ac-40a3-9de4-f562fc22e4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11840669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_async_fifo_reset.11840669
Directory /workspace/43.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_rx_timeout.3369214215
Short name T614
Test name
Test status
Simulation time 3314896196 ps
CPU time 6.55 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 216828 kb
Host smart-273d95b8-04e4-4e11-a24e-153774deb913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369214215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_timeout.3369214215
Directory /workspace/43.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/43.spi_device_smoke.3319212128
Short name T1260
Test name
Test status
Simulation time 166226843 ps
CPU time 1.36 seconds
Started Dec 24 01:57:42 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 216876 kb
Host smart-0e438eba-f5e3-41b2-81d4-0d4e87db49d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319212128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_smoke.3319212128
Directory /workspace/43.spi_device_smoke/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.349545343
Short name T918
Test name
Test status
Simulation time 143048317553 ps
CPU time 1157.83 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 02:17:00 PM PST 23
Peak memory 402092 kb
Host smart-22669ebe-20b7-4024-be52-560e9d783b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349545343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.349545343
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3787094605
Short name T609
Test name
Test status
Simulation time 2327752520 ps
CPU time 11.96 seconds
Started Dec 24 01:57:37 PM PST 23
Finished Dec 24 01:57:53 PM PST 23
Peak memory 217012 kb
Host smart-f10e66e8-c621-4b20-92b0-12cbb18bcfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787094605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3787094605
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2760802328
Short name T854
Test name
Test status
Simulation time 2317143454 ps
CPU time 10.68 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 216852 kb
Host smart-c6159641-939f-4cae-993d-38d21ac348e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760802328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2760802328
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1617815654
Short name T1572
Test name
Test status
Simulation time 524393763 ps
CPU time 1.95 seconds
Started Dec 24 01:57:41 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 216564 kb
Host smart-7fb67263-6d3b-407a-b2f9-3ad2af83fbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617815654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1617815654
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3860635173
Short name T102
Test name
Test status
Simulation time 165709118 ps
CPU time 0.9 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 208116 kb
Host smart-40c3b898-8650-4663-bc96-01de7039a6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860635173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3860635173
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tx_async_fifo_reset.242248453
Short name T75
Test name
Test status
Simulation time 16035464 ps
CPU time 0.77 seconds
Started Dec 24 01:57:35 PM PST 23
Finished Dec 24 01:57:37 PM PST 23
Peak memory 208448 kb
Host smart-453469b5-ca07-4751-bb54-a4069767b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242248453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tx_async_fifo_reset.242248453
Directory /workspace/43.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/43.spi_device_txrx.3911489199
Short name T1307
Test name
Test status
Simulation time 93464000485 ps
CPU time 250.57 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 02:01:54 PM PST 23
Peak memory 301088 kb
Host smart-97841d5f-d884-4ee9-a031-9e12daeefdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911489199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_txrx.3911489199
Directory /workspace/43.spi_device_txrx/latest

Test location /workspace/coverage/default/43.spi_device_upload.2243206781
Short name T219
Test name
Test status
Simulation time 40570091947 ps
CPU time 35.82 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 01:58:18 PM PST 23
Peak memory 237080 kb
Host smart-cc110545-ed4d-4e9f-85ea-66ee43f56da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243206781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2243206781
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_abort.3393184130
Short name T734
Test name
Test status
Simulation time 41119810 ps
CPU time 0.79 seconds
Started Dec 24 01:57:53 PM PST 23
Finished Dec 24 01:57:56 PM PST 23
Peak memory 206680 kb
Host smart-48fb4e3b-6003-425e-ad6d-b6c2ff0209b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393184130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_abort.3393184130
Directory /workspace/44.spi_device_abort/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2603951655
Short name T1642
Test name
Test status
Simulation time 21769384 ps
CPU time 0.73 seconds
Started Dec 24 01:58:01 PM PST 23
Finished Dec 24 01:58:02 PM PST 23
Peak memory 206488 kb
Host smart-be4e971d-0252-49e8-87f8-482db84731ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603951655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2603951655
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_bit_transfer.1773964207
Short name T1299
Test name
Test status
Simulation time 148868253 ps
CPU time 2.34 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:23 PM PST 23
Peak memory 216832 kb
Host smart-2cbc8513-9204-4c5e-af05-e0ef45f8a8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773964207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_bit_transfer.1773964207
Directory /workspace/44.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/44.spi_device_byte_transfer.3633662682
Short name T1149
Test name
Test status
Simulation time 137497423 ps
CPU time 2.68 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 01:57:56 PM PST 23
Peak memory 216792 kb
Host smart-a560f6e4-7135-4467-b31e-7144c59d76a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633662682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_byte_transfer.3633662682
Directory /workspace/44.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2196338076
Short name T301
Test name
Test status
Simulation time 4104765221 ps
CPU time 10.3 seconds
Started Dec 24 01:58:03 PM PST 23
Finished Dec 24 01:58:14 PM PST 23
Peak memory 239316 kb
Host smart-2503c59c-d6d3-469f-a731-440ab8d57930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196338076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2196338076
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1014946770
Short name T1403
Test name
Test status
Simulation time 34722544 ps
CPU time 0.81 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:57:54 PM PST 23
Peak memory 207632 kb
Host smart-d8388f2a-62a5-455c-9878-4af665ff4d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014946770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1014946770
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_dummy_item_extra_dly.4115361404
Short name T1579
Test name
Test status
Simulation time 154101297860 ps
CPU time 1443.84 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 02:21:55 PM PST 23
Peak memory 274728 kb
Host smart-7b03e7d7-b5d4-4e7b-a580-25c831632ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115361404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_dummy_item_extra_dly.4115361404
Directory /workspace/44.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/44.spi_device_extreme_fifo_size.3666283776
Short name T1597
Test name
Test status
Simulation time 29781381301 ps
CPU time 147.48 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 02:00:21 PM PST 23
Peak memory 225204 kb
Host smart-9d95d722-bd0d-4823-8e5b-754d2c5947e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666283776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_extreme_fifo_size.3666283776
Directory /workspace/44.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/44.spi_device_fifo_full.525283495
Short name T651
Test name
Test status
Simulation time 106140442918 ps
CPU time 447.06 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 02:05:20 PM PST 23
Peak memory 273484 kb
Host smart-c918eb70-4c20-4966-a37c-9f40806cc37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525283495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_full.525283495
Directory /workspace/44.spi_device_fifo_full/latest

Test location /workspace/coverage/default/44.spi_device_fifo_underflow_overflow.4135910985
Short name T1451
Test name
Test status
Simulation time 185796299211 ps
CPU time 228.83 seconds
Started Dec 24 01:57:38 PM PST 23
Finished Dec 24 02:01:31 PM PST 23
Peak memory 316372 kb
Host smart-2a91882a-4aef-4428-9926-4a36ebc1a4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135910985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_underflow_overf
low.4135910985
Directory /workspace/44.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.439358538
Short name T329
Test name
Test status
Simulation time 47511217280 ps
CPU time 79.02 seconds
Started Dec 24 01:57:53 PM PST 23
Finished Dec 24 01:59:14 PM PST 23
Peak memory 250212 kb
Host smart-d64bd943-46d2-450e-9d75-3e8c88715645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439358538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.439358538
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1139175725
Short name T1360
Test name
Test status
Simulation time 5739088265 ps
CPU time 39.49 seconds
Started Dec 24 01:57:49 PM PST 23
Finished Dec 24 01:58:30 PM PST 23
Peak memory 225152 kb
Host smart-b55b6648-c099-4804-91bc-c17665e808fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139175725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1139175725
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4029635769
Short name T173
Test name
Test status
Simulation time 366594748 ps
CPU time 7.78 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 01:58:02 PM PST 23
Peak memory 231820 kb
Host smart-150b5d84-6296-42af-a026-f0504a7641a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029635769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4029635769
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intr.3258363203
Short name T852
Test name
Test status
Simulation time 14577194325 ps
CPU time 37.13 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 01:58:28 PM PST 23
Peak memory 233432 kb
Host smart-ac2a74cf-37e9-4d11-bfaf-baf5db7753f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258363203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intr.3258363203
Directory /workspace/44.spi_device_intr/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.112068543
Short name T1744
Test name
Test status
Simulation time 95189371 ps
CPU time 3.09 seconds
Started Dec 24 01:57:53 PM PST 23
Finished Dec 24 01:57:58 PM PST 23
Peak memory 240452 kb
Host smart-e429b62b-3b74-4b19-9dee-a5345346f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112068543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.112068543
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1092957739
Short name T1094
Test name
Test status
Simulation time 13863404711 ps
CPU time 21.6 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:58:14 PM PST 23
Peak memory 241576 kb
Host smart-da7056a7-7334-4ae0-b69f-56a6b7886e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092957739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1092957739
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1509790014
Short name T1106
Test name
Test status
Simulation time 330462011 ps
CPU time 4.06 seconds
Started Dec 24 01:57:54 PM PST 23
Finished Dec 24 01:58:00 PM PST 23
Peak memory 238420 kb
Host smart-1584db57-3cf9-484b-a910-47b63f82700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509790014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1509790014
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_perf.1309192849
Short name T980
Test name
Test status
Simulation time 146524778366 ps
CPU time 2224.33 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 02:34:58 PM PST 23
Peak memory 290496 kb
Host smart-418bc337-ebe2-4f48-8f8a-e34a67375fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309192849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_perf.1309192849
Directory /workspace/44.spi_device_perf/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3761109554
Short name T1008
Test name
Test status
Simulation time 2915821903 ps
CPU time 4.64 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:57:57 PM PST 23
Peak memory 219080 kb
Host smart-d9ffec45-1ca2-4331-841d-fe389b46967c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3761109554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3761109554
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_rx_async_fifo_reset.3956401986
Short name T1259
Test name
Test status
Simulation time 60132459 ps
CPU time 0.86 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 01:57:55 PM PST 23
Peak memory 208448 kb
Host smart-2c80e0a0-d530-4e74-b262-7641c78cb2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956401986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_async_fifo_reset.3956401986
Directory /workspace/44.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_rx_timeout.339665461
Short name T1391
Test name
Test status
Simulation time 684437393 ps
CPU time 6.06 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:57:59 PM PST 23
Peak memory 216892 kb
Host smart-cc3eee3f-f581-4fe9-a65e-9c4552e52a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339665461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_timeout.339665461
Directory /workspace/44.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/44.spi_device_smoke.3357959999
Short name T1690
Test name
Test status
Simulation time 22859842 ps
CPU time 0.91 seconds
Started Dec 24 01:57:44 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 208000 kb
Host smart-d2a39297-ff6b-4f20-9ea9-bd02c00ebe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357959999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_smoke.3357959999
Directory /workspace/44.spi_device_smoke/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.62639738
Short name T916
Test name
Test status
Simulation time 21429646530 ps
CPU time 172.2 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 02:00:44 PM PST 23
Peak memory 258076 kb
Host smart-0c69ca60-361e-4985-8474-03f0ac932b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62639738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress
_all.62639738
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2672103140
Short name T971
Test name
Test status
Simulation time 3813335142 ps
CPU time 29.6 seconds
Started Dec 24 01:58:01 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 216972 kb
Host smart-d2927895-3691-4074-b104-d44a2fc05cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672103140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2672103140
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1228810023
Short name T636
Test name
Test status
Simulation time 15077399585 ps
CPU time 24.36 seconds
Started Dec 24 01:57:53 PM PST 23
Finished Dec 24 01:58:19 PM PST 23
Peak memory 216956 kb
Host smart-27374f3a-c698-4f49-8653-fbd450b9e49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228810023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1228810023
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2808055537
Short name T965
Test name
Test status
Simulation time 166063174 ps
CPU time 0.82 seconds
Started Dec 24 01:57:53 PM PST 23
Finished Dec 24 01:57:56 PM PST 23
Peak memory 207444 kb
Host smart-a9b276e2-c03c-4a51-bdce-6e0974976a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808055537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2808055537
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1346414906
Short name T568
Test name
Test status
Simulation time 25315735 ps
CPU time 0.82 seconds
Started Dec 24 01:57:54 PM PST 23
Finished Dec 24 01:57:56 PM PST 23
Peak memory 206916 kb
Host smart-daf9e2fe-e950-45f7-a34b-ff7535c87dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346414906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1346414906
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tx_async_fifo_reset.3532371789
Short name T1484
Test name
Test status
Simulation time 14298748 ps
CPU time 0.78 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:57:54 PM PST 23
Peak memory 208440 kb
Host smart-412b6cae-1896-43e1-9fc4-74d44c6ef9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532371789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tx_async_fifo_reset.3532371789
Directory /workspace/44.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/44.spi_device_txrx.3057439363
Short name T1064
Test name
Test status
Simulation time 14118356035 ps
CPU time 257.49 seconds
Started Dec 24 01:57:39 PM PST 23
Finished Dec 24 02:02:01 PM PST 23
Peak memory 287680 kb
Host smart-479fa5a8-c03e-402b-ac91-e74721c4ca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057439363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_txrx.3057439363
Directory /workspace/44.spi_device_txrx/latest

Test location /workspace/coverage/default/44.spi_device_upload.3574720814
Short name T1187
Test name
Test status
Simulation time 661288692 ps
CPU time 7.87 seconds
Started Dec 24 01:57:58 PM PST 23
Finished Dec 24 01:58:07 PM PST 23
Peak memory 241416 kb
Host smart-fde256b4-0988-4a98-bdc9-fc212cf7cf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574720814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3574720814
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_abort.3158826663
Short name T948
Test name
Test status
Simulation time 53269387 ps
CPU time 0.77 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 01:57:55 PM PST 23
Peak memory 206628 kb
Host smart-d8a81443-f29a-491d-8b0e-026ec6a18511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158826663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_abort.3158826663
Directory /workspace/45.spi_device_abort/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3984028050
Short name T583
Test name
Test status
Simulation time 39371062 ps
CPU time 0.7 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:24 PM PST 23
Peak memory 206412 kb
Host smart-5f8df990-e2e3-494b-856a-3088b94c5741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984028050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3984028050
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_bit_transfer.3687454244
Short name T891
Test name
Test status
Simulation time 458227386 ps
CPU time 2.24 seconds
Started Dec 24 01:57:48 PM PST 23
Finished Dec 24 01:57:51 PM PST 23
Peak memory 216716 kb
Host smart-2eff199d-0333-45e9-9daf-81b7506aee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687454244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_bit_transfer.3687454244
Directory /workspace/45.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/45.spi_device_byte_transfer.554369093
Short name T1523
Test name
Test status
Simulation time 1090366547 ps
CPU time 2.83 seconds
Started Dec 24 01:57:53 PM PST 23
Finished Dec 24 01:57:57 PM PST 23
Peak memory 216828 kb
Host smart-181bc240-6d2e-45e9-9791-1a7a9104a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554369093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_byte_transfer.554369093
Directory /workspace/45.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2562921252
Short name T972
Test name
Test status
Simulation time 6622662586 ps
CPU time 7.9 seconds
Started Dec 24 01:58:07 PM PST 23
Finished Dec 24 01:58:16 PM PST 23
Peak memory 238784 kb
Host smart-6d808fb1-a655-4c1a-9b40-a82dcdbced0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562921252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2562921252
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4176216839
Short name T559
Test name
Test status
Simulation time 18183655 ps
CPU time 0.81 seconds
Started Dec 24 01:57:49 PM PST 23
Finished Dec 24 01:57:51 PM PST 23
Peak memory 207608 kb
Host smart-fd8cbeec-207d-4ad7-80f2-22c244803afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176216839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4176216839
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_dummy_item_extra_dly.892292011
Short name T1192
Test name
Test status
Simulation time 64943014640 ps
CPU time 304.61 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 02:02:58 PM PST 23
Peak memory 314720 kb
Host smart-46428d20-e395-4840-b552-0fc7644d69a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892292011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_dummy_item_extra_dly.892292011
Directory /workspace/45.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/45.spi_device_extreme_fifo_size.63678986
Short name T258
Test name
Test status
Simulation time 264919886643 ps
CPU time 952.37 seconds
Started Dec 24 01:57:54 PM PST 23
Finished Dec 24 02:13:48 PM PST 23
Peak memory 225156 kb
Host smart-eea4c9aa-a754-4102-b5f8-2247e81f1da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63678986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_extreme_fifo_size.63678986
Directory /workspace/45.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/45.spi_device_fifo_full.1707619218
Short name T573
Test name
Test status
Simulation time 36859574132 ps
CPU time 746.25 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 02:10:17 PM PST 23
Peak memory 285740 kb
Host smart-c4203912-c88e-40ef-ba9f-93838167c3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707619218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_full.1707619218
Directory /workspace/45.spi_device_fifo_full/latest

Test location /workspace/coverage/default/45.spi_device_fifo_underflow_overflow.412992913
Short name T53
Test name
Test status
Simulation time 322598540068 ps
CPU time 520.49 seconds
Started Dec 24 01:57:54 PM PST 23
Finished Dec 24 02:06:36 PM PST 23
Peak memory 495224 kb
Host smart-2084c348-0d65-49fa-9c2e-298d136bbda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412992913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_underflow_overfl
ow.412992913
Directory /workspace/45.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1857512404
Short name T1615
Test name
Test status
Simulation time 6031382524 ps
CPU time 63.62 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:59:23 PM PST 23
Peak memory 252324 kb
Host smart-52a781f0-af10-4417-95e0-cd2d047c023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857512404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1857512404
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2847895910
Short name T935
Test name
Test status
Simulation time 56975826542 ps
CPU time 27.94 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:50 PM PST 23
Peak memory 240216 kb
Host smart-8c5b12f6-c4d7-4e05-ad90-dfe536de5dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847895910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2847895910
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2560755130
Short name T116
Test name
Test status
Simulation time 7028507219 ps
CPU time 7.26 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 220516 kb
Host smart-87956891-506e-4494-a9ca-b6371479f760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560755130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2560755130
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intr.1534522196
Short name T642
Test name
Test status
Simulation time 31240750878 ps
CPU time 39.97 seconds
Started Dec 24 01:57:57 PM PST 23
Finished Dec 24 01:58:38 PM PST 23
Peak memory 238492 kb
Host smart-1a1d06a0-f563-4a63-a06b-77e645e9b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534522196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intr.1534522196
Directory /workspace/45.spi_device_intr/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.938474641
Short name T264
Test name
Test status
Simulation time 9967886152 ps
CPU time 8.04 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:30 PM PST 23
Peak memory 233168 kb
Host smart-6d719c9c-8366-4cd0-a7b6-5a5448d5102f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938474641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.938474641
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.292067362
Short name T1325
Test name
Test status
Simulation time 1768272850 ps
CPU time 7.62 seconds
Started Dec 24 01:58:06 PM PST 23
Finished Dec 24 01:58:14 PM PST 23
Peak memory 219252 kb
Host smart-2c58796e-9a4c-47e4-8699-6afcfc0dff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292067362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.292067362
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1734532618
Short name T1375
Test name
Test status
Simulation time 37030684 ps
CPU time 2.48 seconds
Started Dec 24 01:58:01 PM PST 23
Finished Dec 24 01:58:05 PM PST 23
Peak memory 218444 kb
Host smart-91f0df86-6cd4-4d21-bf67-e90bb3067d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734532618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1734532618
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_perf.3250515827
Short name T791
Test name
Test status
Simulation time 22033420995 ps
CPU time 440.86 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 02:05:12 PM PST 23
Peak memory 282584 kb
Host smart-af9dfc2a-6c5b-4d8a-a4a3-70d83bfcd679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250515827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_perf.3250515827
Directory /workspace/45.spi_device_perf/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1034869979
Short name T1541
Test name
Test status
Simulation time 4020493469 ps
CPU time 5.53 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 220836 kb
Host smart-bba36d05-e5d7-4753-9d07-1160e88a0c37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1034869979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1034869979
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_rx_async_fifo_reset.1420494815
Short name T1641
Test name
Test status
Simulation time 104440731 ps
CPU time 0.89 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 01:57:55 PM PST 23
Peak memory 208500 kb
Host smart-027d807e-0c7e-45c9-be89-b87d50e5d5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420494815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_async_fifo_reset.1420494815
Directory /workspace/45.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_rx_timeout.983676976
Short name T960
Test name
Test status
Simulation time 507200983 ps
CPU time 4.79 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:57:58 PM PST 23
Peak memory 216716 kb
Host smart-7167f795-21d0-4793-bd48-c522f5c92473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983676976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_timeout.983676976
Directory /workspace/45.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/45.spi_device_smoke.2737090211
Short name T518
Test name
Test status
Simulation time 34495062 ps
CPU time 0.96 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:57:53 PM PST 23
Peak memory 207808 kb
Host smart-8f015c1f-2362-4fb2-9304-bc2631970a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737090211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_smoke.2737090211
Directory /workspace/45.spi_device_smoke/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4139838742
Short name T867
Test name
Test status
Simulation time 212008481470 ps
CPU time 1161.37 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 02:17:49 PM PST 23
Peak memory 380148 kb
Host smart-dbf5a37f-76d3-4e41-93ce-8626f5dfa49e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139838742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4139838742
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.822860554
Short name T1016
Test name
Test status
Simulation time 2012614320 ps
CPU time 24.48 seconds
Started Dec 24 01:57:51 PM PST 23
Finished Dec 24 01:58:17 PM PST 23
Peak memory 217028 kb
Host smart-cb5478c3-3e98-4c2c-8da2-8650435cbdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822860554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.822860554
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.112256008
Short name T1153
Test name
Test status
Simulation time 1373086871 ps
CPU time 7.4 seconds
Started Dec 24 01:57:53 PM PST 23
Finished Dec 24 01:58:02 PM PST 23
Peak memory 216820 kb
Host smart-a56c4abf-f7a7-4c77-a952-bfda2eb1f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112256008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.112256008
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1627955794
Short name T1658
Test name
Test status
Simulation time 588369317 ps
CPU time 3.54 seconds
Started Dec 24 01:57:52 PM PST 23
Finished Dec 24 01:57:57 PM PST 23
Peak memory 216888 kb
Host smart-7f3211f2-f56d-4c5d-81e8-2dfa4db73515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627955794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1627955794
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.771043451
Short name T1006
Test name
Test status
Simulation time 44884728 ps
CPU time 0.84 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:58:26 PM PST 23
Peak memory 206936 kb
Host smart-6a6a4229-b122-4cf0-8d26-f2c4cb92b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771043451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.771043451
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tx_async_fifo_reset.4202610997
Short name T134
Test name
Test status
Simulation time 16916572 ps
CPU time 0.84 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 01:57:52 PM PST 23
Peak memory 208456 kb
Host smart-0987cb1f-83b5-49dd-b967-7a5061398f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202610997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tx_async_fifo_reset.4202610997
Directory /workspace/45.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/45.spi_device_txrx.946287316
Short name T486
Test name
Test status
Simulation time 64148400254 ps
CPU time 211.44 seconds
Started Dec 24 01:57:50 PM PST 23
Finished Dec 24 02:01:23 PM PST 23
Peak memory 290288 kb
Host smart-a619df48-9606-4f6b-9b83-6deeade82310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946287316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_txrx.946287316
Directory /workspace/45.spi_device_txrx/latest

Test location /workspace/coverage/default/45.spi_device_upload.34522375
Short name T843
Test name
Test status
Simulation time 367359867 ps
CPU time 2.9 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 218796 kb
Host smart-850cb1f5-ee5f-4902-841d-acf15c50e14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34522375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.34522375
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_abort.1934472764
Short name T1251
Test name
Test status
Simulation time 54931274 ps
CPU time 0.74 seconds
Started Dec 24 01:58:07 PM PST 23
Finished Dec 24 01:58:09 PM PST 23
Peak memory 206628 kb
Host smart-64d1ca75-7234-4ab7-87b8-2ecb0ea19131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934472764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_abort.1934472764
Directory /workspace/46.spi_device_abort/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1682481658
Short name T594
Test name
Test status
Simulation time 43339262 ps
CPU time 0.76 seconds
Started Dec 24 01:58:38 PM PST 23
Finished Dec 24 01:58:41 PM PST 23
Peak memory 206504 kb
Host smart-4c533896-a581-4d97-9dd4-a2b84c6bb662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682481658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1682481658
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_bit_transfer.2906960866
Short name T1222
Test name
Test status
Simulation time 402729592 ps
CPU time 2.18 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 01:58:30 PM PST 23
Peak memory 216764 kb
Host smart-aec9c79b-0ab5-4f2e-9b53-a2b50e571f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906960866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_bit_transfer.2906960866
Directory /workspace/46.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/46.spi_device_byte_transfer.2812461599
Short name T1414
Test name
Test status
Simulation time 236887671 ps
CPU time 2.62 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:24 PM PST 23
Peak memory 216700 kb
Host smart-78fa4ff5-87a2-4e56-a881-e2557da03c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812461599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_byte_transfer.2812461599
Directory /workspace/46.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1825331558
Short name T620
Test name
Test status
Simulation time 35083161 ps
CPU time 2.9 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:25 PM PST 23
Peak memory 237588 kb
Host smart-17a97ad6-fdc6-4d34-a1e9-2e8fbc765a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825331558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1825331558
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1609562607
Short name T1337
Test name
Test status
Simulation time 49158435 ps
CPU time 0.76 seconds
Started Dec 24 01:58:17 PM PST 23
Finished Dec 24 01:58:19 PM PST 23
Peak memory 206592 kb
Host smart-4549f1d4-1453-45ad-8fad-3b0409c6ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609562607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1609562607
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_dummy_item_extra_dly.723294921
Short name T1428
Test name
Test status
Simulation time 120579951200 ps
CPU time 827.87 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 02:12:11 PM PST 23
Peak memory 251840 kb
Host smart-1309c69f-2e6f-4b95-ad18-d33693d4ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723294921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_dummy_item_extra_dly.723294921
Directory /workspace/46.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/46.spi_device_extreme_fifo_size.1266100274
Short name T711
Test name
Test status
Simulation time 4704843509 ps
CPU time 27.4 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:50 PM PST 23
Peak memory 232572 kb
Host smart-123827bf-e391-4412-9b6d-311fd9fa023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266100274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_extreme_fifo_size.1266100274
Directory /workspace/46.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/46.spi_device_fifo_full.3101913161
Short name T1580
Test name
Test status
Simulation time 44855782229 ps
CPU time 624.98 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 252756 kb
Host smart-9530a572-d9de-4455-8b61-470786439d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101913161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_full.3101913161
Directory /workspace/46.spi_device_fifo_full/latest

Test location /workspace/coverage/default/46.spi_device_fifo_underflow_overflow.3869838867
Short name T195
Test name
Test status
Simulation time 474729663955 ps
CPU time 726.72 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 02:10:28 PM PST 23
Peak memory 429084 kb
Host smart-823a3d33-c1aa-470e-9d00-983195658e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869838867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_underflow_overf
low.3869838867
Directory /workspace/46.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1019333847
Short name T214
Test name
Test status
Simulation time 94772413534 ps
CPU time 139.16 seconds
Started Dec 24 01:58:31 PM PST 23
Finished Dec 24 02:00:53 PM PST 23
Peak memory 268996 kb
Host smart-f96a3f62-7536-4b86-bca6-8a8d9710298f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019333847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1019333847
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3430326106
Short name T268
Test name
Test status
Simulation time 23462510441 ps
CPU time 71.95 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:59:35 PM PST 23
Peak memory 239184 kb
Host smart-c0d2ced1-dcd3-450f-897e-d38845a3192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430326106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3430326106
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2201567485
Short name T1131
Test name
Test status
Simulation time 36673110961 ps
CPU time 273.91 seconds
Started Dec 24 01:58:31 PM PST 23
Finished Dec 24 02:03:08 PM PST 23
Peak memory 240504 kb
Host smart-7d3c3835-bf81-4dbe-829f-59bcc0156f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201567485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2201567485
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1467765464
Short name T1431
Test name
Test status
Simulation time 432219483 ps
CPU time 12.46 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:34 PM PST 23
Peak memory 233260 kb
Host smart-2b6efcb6-ba64-4564-83a1-f9e30f9558da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467765464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1467765464
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.456003852
Short name T699
Test name
Test status
Simulation time 375868942 ps
CPU time 3.33 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:25 PM PST 23
Peak memory 218208 kb
Host smart-57a3627d-25a3-405c-b076-2aaf87ed0bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456003852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.456003852
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intr.2958308659
Short name T1435
Test name
Test status
Simulation time 15450031735 ps
CPU time 32.74 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:57 PM PST 23
Peak memory 233288 kb
Host smart-13488a1f-f980-418e-9b9d-4fb3cddb84f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958308659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intr.2958308659
Directory /workspace/46.spi_device_intr/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3598591045
Short name T273
Test name
Test status
Simulation time 7102830638 ps
CPU time 9.18 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:58:28 PM PST 23
Peak memory 237160 kb
Host smart-0777eccc-3d1e-4b49-9bea-4b1d43f63bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598591045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3598591045
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2069053921
Short name T310
Test name
Test status
Simulation time 698909032 ps
CPU time 2.99 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:26 PM PST 23
Peak memory 218848 kb
Host smart-862decd7-c153-441f-8f19-3aecaf14bd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069053921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2069053921
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2393532319
Short name T1436
Test name
Test status
Simulation time 473867863 ps
CPU time 3.64 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 218532 kb
Host smart-ae863dc7-4303-49ab-afca-50463fd29ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393532319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2393532319
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_perf.2240103237
Short name T1622
Test name
Test status
Simulation time 19012977679 ps
CPU time 149.14 seconds
Started Dec 24 01:58:02 PM PST 23
Finished Dec 24 02:00:33 PM PST 23
Peak memory 249712 kb
Host smart-c5f20632-04bf-41d4-9580-606d9f141bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240103237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_perf.2240103237
Directory /workspace/46.spi_device_perf/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.587678520
Short name T712
Test name
Test status
Simulation time 711130326 ps
CPU time 5.33 seconds
Started Dec 24 01:58:24 PM PST 23
Finished Dec 24 01:58:34 PM PST 23
Peak memory 218908 kb
Host smart-b7afab75-004f-437b-87c0-9f1d458f2b0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=587678520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.587678520
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_rx_async_fifo_reset.3139150026
Short name T1687
Test name
Test status
Simulation time 23205956 ps
CPU time 0.9 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:58:21 PM PST 23
Peak memory 208412 kb
Host smart-8007a41a-d108-4b62-963c-c9b1c41088db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139150026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_async_fifo_reset.3139150026
Directory /workspace/46.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_rx_timeout.3249054004
Short name T602
Test name
Test status
Simulation time 673822158 ps
CPU time 5.39 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 216756 kb
Host smart-67a9f76c-db30-4bc1-81a4-11c1b2a7f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249054004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_timeout.3249054004
Directory /workspace/46.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/46.spi_device_smoke.2542721879
Short name T1209
Test name
Test status
Simulation time 94286432 ps
CPU time 1.11 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:23 PM PST 23
Peak memory 216564 kb
Host smart-d9b20358-188e-4def-8afd-430dc0462399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542721879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_smoke.2542721879
Directory /workspace/46.spi_device_smoke/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4207579542
Short name T1786
Test name
Test status
Simulation time 161910940497 ps
CPU time 1568.65 seconds
Started Dec 24 01:58:35 PM PST 23
Finished Dec 24 02:24:46 PM PST 23
Peak memory 355712 kb
Host smart-41ff79cb-aa18-4c61-998c-a28be374dfe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207579542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4207579542
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2422370522
Short name T679
Test name
Test status
Simulation time 2512145507 ps
CPU time 40.56 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:59:04 PM PST 23
Peak memory 220752 kb
Host smart-dc307330-66ad-4c5a-adf8-763a3bff6e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422370522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2422370522
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1403687150
Short name T631
Test name
Test status
Simulation time 7415801753 ps
CPU time 21.86 seconds
Started Dec 24 01:58:06 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 216868 kb
Host smart-4b85ae7d-b00e-4b44-8842-fddb21971953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403687150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1403687150
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2759401666
Short name T894
Test name
Test status
Simulation time 38167292 ps
CPU time 0.73 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 206908 kb
Host smart-aa73d7d9-a52d-4ed6-854b-bcf97cd813b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759401666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2759401666
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1993255590
Short name T707
Test name
Test status
Simulation time 16463079 ps
CPU time 0.74 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:58:20 PM PST 23
Peak memory 207164 kb
Host smart-c66cf892-7172-4697-ba2e-04a89ea09608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993255590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1993255590
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tx_async_fifo_reset.1515745096
Short name T945
Test name
Test status
Simulation time 15226503 ps
CPU time 0.8 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:22 PM PST 23
Peak memory 208508 kb
Host smart-ead12edc-7174-4ea8-b7ef-67603de2507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515745096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tx_async_fifo_reset.1515745096
Directory /workspace/46.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/46.spi_device_txrx.1217291026
Short name T725
Test name
Test status
Simulation time 428083080432 ps
CPU time 731.27 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 02:10:31 PM PST 23
Peak memory 257928 kb
Host smart-261e71d5-b469-49f3-b0ce-7570c8a6f14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217291026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_txrx.1217291026
Directory /workspace/46.spi_device_txrx/latest

Test location /workspace/coverage/default/46.spi_device_upload.1789111191
Short name T762
Test name
Test status
Simulation time 499422501 ps
CPU time 8.54 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 235428 kb
Host smart-04fc6a39-8932-42a8-b572-14da83b61cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789111191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1789111191
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_abort.2196439581
Short name T17
Test name
Test status
Simulation time 16461849 ps
CPU time 0.77 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:22 PM PST 23
Peak memory 206596 kb
Host smart-6da96b41-b901-4edd-9da5-3d2dd3543dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196439581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_abort.2196439581
Directory /workspace/47.spi_device_abort/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3796751649
Short name T1747
Test name
Test status
Simulation time 14882604 ps
CPU time 0.74 seconds
Started Dec 24 01:58:15 PM PST 23
Finished Dec 24 01:58:17 PM PST 23
Peak memory 206480 kb
Host smart-739cc483-20fb-4322-895e-3eeaaa94c1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796751649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3796751649
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_bit_transfer.991592369
Short name T1501
Test name
Test status
Simulation time 391645016 ps
CPU time 3.19 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 216788 kb
Host smart-d054f1d4-6e2a-40ac-bad9-bf2a262f84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991592369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_bit_transfer.991592369
Directory /workspace/47.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/47.spi_device_byte_transfer.2687281194
Short name T877
Test name
Test status
Simulation time 264607794 ps
CPU time 2.37 seconds
Started Dec 24 01:58:33 PM PST 23
Finished Dec 24 01:58:38 PM PST 23
Peak memory 216844 kb
Host smart-d74ec4cb-dc64-4d9d-993d-d19de099ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687281194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_byte_transfer.2687281194
Directory /workspace/47.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1109481408
Short name T280
Test name
Test status
Simulation time 316637222 ps
CPU time 4.77 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 225044 kb
Host smart-892d6221-0943-42b2-b978-252b577b0535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109481408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1109481408
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4202974936
Short name T638
Test name
Test status
Simulation time 50126441 ps
CPU time 0.78 seconds
Started Dec 24 01:58:31 PM PST 23
Finished Dec 24 01:58:35 PM PST 23
Peak memory 207564 kb
Host smart-ccb2abde-6a51-4e34-b3ca-4061301b0fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202974936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4202974936
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_dummy_item_extra_dly.2446685254
Short name T974
Test name
Test status
Simulation time 58307380162 ps
CPU time 916.51 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 02:13:46 PM PST 23
Peak memory 315216 kb
Host smart-5b36b88b-c9b9-4fb9-8f97-d426bce1cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446685254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_dummy_item_extra_dly.2446685254
Directory /workspace/47.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/47.spi_device_extreme_fifo_size.2798901955
Short name T541
Test name
Test status
Simulation time 312855656268 ps
CPU time 3688.87 seconds
Started Dec 24 01:58:37 PM PST 23
Finished Dec 24 03:00:09 PM PST 23
Peak memory 217992 kb
Host smart-1a76f87c-5d9f-482b-b275-f5c81f135b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798901955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_extreme_fifo_size.2798901955
Directory /workspace/47.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/47.spi_device_fifo_full.4080955593
Short name T1073
Test name
Test status
Simulation time 123876877583 ps
CPU time 585.28 seconds
Started Dec 24 01:58:37 PM PST 23
Finished Dec 24 02:08:26 PM PST 23
Peak memory 312040 kb
Host smart-0dc9ca1e-544c-4a98-9dd9-724c5dc1d134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080955593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_full.4080955593
Directory /workspace/47.spi_device_fifo_full/latest

Test location /workspace/coverage/default/47.spi_device_fifo_underflow_overflow.3810675256
Short name T753
Test name
Test status
Simulation time 187919814084 ps
CPU time 272.45 seconds
Started Dec 24 01:58:30 PM PST 23
Finished Dec 24 02:03:06 PM PST 23
Peak memory 350588 kb
Host smart-241b7360-0ef8-4cea-bc77-38b1b7cb9d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810675256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_underflow_overf
low.3810675256
Directory /workspace/47.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2451891123
Short name T247
Test name
Test status
Simulation time 14090809819 ps
CPU time 100.65 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 02:00:00 PM PST 23
Peak memory 265996 kb
Host smart-ff23301f-b81f-4df1-9283-1b6e53c24b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451891123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2451891123
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1431377015
Short name T1460
Test name
Test status
Simulation time 7219800751 ps
CPU time 32.84 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:56 PM PST 23
Peak memory 249844 kb
Host smart-5d19ce40-a216-4934-af29-9f340359ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431377015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1431377015
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.481842020
Short name T335
Test name
Test status
Simulation time 218483272595 ps
CPU time 387.26 seconds
Started Dec 24 01:58:24 PM PST 23
Finished Dec 24 02:04:56 PM PST 23
Peak memory 257952 kb
Host smart-a19d0169-7099-41ea-b082-84d5d1c74550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481842020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.481842020
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.872271765
Short name T1679
Test name
Test status
Simulation time 3791951335 ps
CPU time 22.76 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:43 PM PST 23
Peak memory 248508 kb
Host smart-2d7cb43f-5f29-4dd7-aa58-11d7eea40507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872271765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.872271765
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1599023566
Short name T656
Test name
Test status
Simulation time 3364875335 ps
CPU time 13.42 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:36 PM PST 23
Peak memory 240096 kb
Host smart-dcec4e6b-6431-41e6-a5c7-ee4622f406a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599023566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1599023566
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3107004280
Short name T137
Test name
Test status
Simulation time 23005338388 ps
CPU time 21.07 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:45 PM PST 23
Peak memory 246896 kb
Host smart-e018b1c4-1125-4508-8f8d-0f10dc8f9625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107004280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3107004280
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3963344150
Short name T612
Test name
Test status
Simulation time 1832226903 ps
CPU time 8.38 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 238904 kb
Host smart-1ed9f8cb-e650-4e9d-b3d0-0f3abb804838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963344150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3963344150
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.988224391
Short name T993
Test name
Test status
Simulation time 29943398702 ps
CPU time 39.24 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:58:58 PM PST 23
Peak memory 238556 kb
Host smart-80737a0b-11ee-47e3-a91e-dbca1a7198f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988224391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.988224391
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_perf.4038091964
Short name T1661
Test name
Test status
Simulation time 29582073104 ps
CPU time 755.21 seconds
Started Dec 24 01:58:37 PM PST 23
Finished Dec 24 02:11:14 PM PST 23
Peak memory 273800 kb
Host smart-06fa2a1d-df8b-4b28-bb5b-109b5f13bab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038091964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_perf.4038091964
Directory /workspace/47.spi_device_perf/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2310173145
Short name T1429
Test name
Test status
Simulation time 3458405132 ps
CPU time 5.73 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 234484 kb
Host smart-6cf38cd5-5314-412d-a9f3-aca34ef29711
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310173145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2310173145
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_rx_async_fifo_reset.2652031215
Short name T639
Test name
Test status
Simulation time 284522465 ps
CPU time 0.96 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:24 PM PST 23
Peak memory 208392 kb
Host smart-83a7b4a7-7c5d-4ca2-a5b9-dc4b6ff68397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652031215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_async_fifo_reset.2652031215
Directory /workspace/47.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_rx_timeout.929684285
Short name T1383
Test name
Test status
Simulation time 3000199918 ps
CPU time 4.89 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 216892 kb
Host smart-09eb9a6a-0252-404a-b88c-779cd97fd3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929684285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_timeout.929684285
Directory /workspace/47.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/47.spi_device_smoke.31424883
Short name T977
Test name
Test status
Simulation time 112295702 ps
CPU time 1.04 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 208224 kb
Host smart-6ce994ce-6e69-4674-af12-38221ad2accb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31424883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_smoke.31424883
Directory /workspace/47.spi_device_smoke/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2747533592
Short name T108
Test name
Test status
Simulation time 5015273335 ps
CPU time 18.95 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:58:44 PM PST 23
Peak memory 220220 kb
Host smart-9125ff2c-ba5f-4d0c-ae4a-eebc125a9a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747533592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2747533592
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2214896016
Short name T917
Test name
Test status
Simulation time 7578880100 ps
CPU time 10.27 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:30 PM PST 23
Peak memory 216860 kb
Host smart-a2c60b14-5baf-41f6-8caf-8b761b0d8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214896016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2214896016
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1985464484
Short name T103
Test name
Test status
Simulation time 24973462 ps
CPU time 1.49 seconds
Started Dec 24 01:58:17 PM PST 23
Finished Dec 24 01:58:20 PM PST 23
Peak memory 216824 kb
Host smart-3b5b3362-5c69-4e87-8f10-b99d9d93beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985464484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1985464484
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1149197276
Short name T531
Test name
Test status
Simulation time 32298557 ps
CPU time 0.72 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:22 PM PST 23
Peak memory 206964 kb
Host smart-15ef5e5e-7ec0-483e-8304-48d32545a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149197276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1149197276
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tx_async_fifo_reset.1731534790
Short name T1422
Test name
Test status
Simulation time 31085888 ps
CPU time 0.79 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:23 PM PST 23
Peak memory 208500 kb
Host smart-da4941ef-4ea1-44ed-bc6d-3240c668969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731534790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tx_async_fifo_reset.1731534790
Directory /workspace/47.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/47.spi_device_txrx.2311976076
Short name T926
Test name
Test status
Simulation time 105691310040 ps
CPU time 114 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 02:00:24 PM PST 23
Peak memory 247892 kb
Host smart-9911cd0c-661a-4728-9e7c-7ff8f50c453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311976076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_txrx.2311976076
Directory /workspace/47.spi_device_txrx/latest

Test location /workspace/coverage/default/47.spi_device_upload.2152925242
Short name T1040
Test name
Test status
Simulation time 3173690686 ps
CPU time 12.33 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 241764 kb
Host smart-e8b66249-8cae-46f8-99af-e840ac0a39e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152925242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2152925242
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_abort.1017517369
Short name T820
Test name
Test status
Simulation time 45172796 ps
CPU time 0.75 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 206648 kb
Host smart-d81440a0-0623-4fb3-b7cc-36dcc21b7fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017517369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_abort.1017517369
Directory /workspace/48.spi_device_abort/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.907547678
Short name T745
Test name
Test status
Simulation time 13122841 ps
CPU time 0.75 seconds
Started Dec 24 01:58:32 PM PST 23
Finished Dec 24 01:58:35 PM PST 23
Peak memory 206360 kb
Host smart-ecf4fa18-8c20-449c-b7ee-f6ff2ef53b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907547678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.907547678
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_bit_transfer.3418957163
Short name T862
Test name
Test status
Simulation time 381540888 ps
CPU time 2.59 seconds
Started Dec 24 01:58:24 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 216908 kb
Host smart-3237727a-c40a-45bf-9c0a-c7c4fa673d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418957163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_bit_transfer.3418957163
Directory /workspace/48.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/48.spi_device_byte_transfer.2643083015
Short name T1699
Test name
Test status
Simulation time 486973351 ps
CPU time 2.4 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:24 PM PST 23
Peak memory 216784 kb
Host smart-fbf35b7b-b38f-4359-90ab-fba40854218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643083015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_byte_transfer.2643083015
Directory /workspace/48.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2437028749
Short name T845
Test name
Test status
Simulation time 124240926 ps
CPU time 3.06 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:24 PM PST 23
Peak memory 233328 kb
Host smart-8661e0a0-056a-460f-bd59-3e41b2f99f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437028749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2437028749
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3673351720
Short name T816
Test name
Test status
Simulation time 27804900 ps
CPU time 0.76 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:58:20 PM PST 23
Peak memory 206512 kb
Host smart-304a95f0-53d4-4e68-a127-8d88e171274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673351720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3673351720
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_dummy_item_extra_dly.1668414625
Short name T530
Test name
Test status
Simulation time 35488741810 ps
CPU time 241.56 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 02:02:22 PM PST 23
Peak memory 271244 kb
Host smart-b5a9c52b-4668-4635-bd79-9b554176818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668414625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_dummy_item_extra_dly.1668414625
Directory /workspace/48.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/48.spi_device_extreme_fifo_size.2971298322
Short name T780
Test name
Test status
Simulation time 8958091255 ps
CPU time 37.19 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:59:01 PM PST 23
Peak memory 233332 kb
Host smart-77ada12e-964f-478f-ba99-204c9c5a4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971298322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_extreme_fifo_size.2971298322
Directory /workspace/48.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/48.spi_device_fifo_full.1260443773
Short name T1774
Test name
Test status
Simulation time 28841540787 ps
CPU time 658.09 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 02:09:26 PM PST 23
Peak memory 252092 kb
Host smart-a4ae0996-7ee0-42e4-99be-e418a8544782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260443773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_full.1260443773
Directory /workspace/48.spi_device_fifo_full/latest

Test location /workspace/coverage/default/48.spi_device_fifo_underflow_overflow.1586988268
Short name T56
Test name
Test status
Simulation time 25772880142 ps
CPU time 165.33 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 02:01:12 PM PST 23
Peak memory 359388 kb
Host smart-edaa2e42-e40b-4495-9dfb-f4dbbeed84a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586988268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_underflow_overf
low.1586988268
Directory /workspace/48.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.320826765
Short name T1253
Test name
Test status
Simulation time 45923672692 ps
CPU time 111 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 02:00:17 PM PST 23
Peak memory 256056 kb
Host smart-6fcfbf02-45bc-4000-b3c4-8a581eca56ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320826765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.320826765
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2711943287
Short name T787
Test name
Test status
Simulation time 24445538076 ps
CPU time 189.82 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 02:01:40 PM PST 23
Peak memory 249764 kb
Host smart-1d4951dd-832a-4a01-8319-b4dea7226fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711943287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2711943287
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.602567221
Short name T63
Test name
Test status
Simulation time 25209717405 ps
CPU time 189.9 seconds
Started Dec 24 01:58:32 PM PST 23
Finished Dec 24 02:01:45 PM PST 23
Peak memory 254408 kb
Host smart-876b8e74-ebfd-4b6d-bbff-7a76ad3dd3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602567221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.602567221
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3763839408
Short name T1413
Test name
Test status
Simulation time 1200445487 ps
CPU time 8.28 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 01:58:36 PM PST 23
Peak memory 232872 kb
Host smart-ed0d3504-4db1-44f2-a86b-6f8a7f29a11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763839408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3763839408
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.532044003
Short name T232
Test name
Test status
Simulation time 18385128938 ps
CPU time 12.1 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 01:58:42 PM PST 23
Peak memory 241604 kb
Host smart-8a3987d0-4c04-424e-a38f-a84eef217f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532044003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.532044003
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intr.3460882139
Short name T1389
Test name
Test status
Simulation time 12648724717 ps
CPU time 20.09 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:42 PM PST 23
Peak memory 221608 kb
Host smart-2f346bc1-90c2-435a-9018-d4cccee6dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460882139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intr.3460882139
Directory /workspace/48.spi_device_intr/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2058606849
Short name T1467
Test name
Test status
Simulation time 12418497062 ps
CPU time 18.8 seconds
Started Dec 24 01:58:26 PM PST 23
Finished Dec 24 01:58:50 PM PST 23
Peak memory 252540 kb
Host smart-1c585e2f-f97e-4cf5-884d-c318cda69583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058606849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2058606849
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4212617802
Short name T1188
Test name
Test status
Simulation time 6641479537 ps
CPU time 11.87 seconds
Started Dec 24 01:58:17 PM PST 23
Finished Dec 24 01:58:30 PM PST 23
Peak memory 221248 kb
Host smart-d8032c60-b8b6-48a2-accd-35b5787aa0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212617802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4212617802
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.251882544
Short name T906
Test name
Test status
Simulation time 101025129 ps
CPU time 3.07 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:24 PM PST 23
Peak memory 234332 kb
Host smart-5c680598-9445-4403-9a70-3aad2e6b926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251882544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.251882544
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_perf.763567569
Short name T1083
Test name
Test status
Simulation time 27295580844 ps
CPU time 199.7 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 02:01:40 PM PST 23
Peak memory 250552 kb
Host smart-724958d0-21c5-47a7-9034-e359c1f1a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763567569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_perf.763567569
Directory /workspace/48.spi_device_perf/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2507733934
Short name T859
Test name
Test status
Simulation time 1511486458 ps
CPU time 4.57 seconds
Started Dec 24 01:58:27 PM PST 23
Finished Dec 24 01:58:36 PM PST 23
Peak memory 219812 kb
Host smart-9e10091c-87d7-4c1e-bfc2-e75772fe0801
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2507733934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2507733934
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_rx_async_fifo_reset.3222373322
Short name T936
Test name
Test status
Simulation time 26576818 ps
CPU time 0.85 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:25 PM PST 23
Peak memory 208456 kb
Host smart-679f5bde-aeda-47b4-a64a-554fd5e8c479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222373322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_async_fifo_reset.3222373322
Directory /workspace/48.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_rx_timeout.2248858544
Short name T876
Test name
Test status
Simulation time 1049928363 ps
CPU time 5.02 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:26 PM PST 23
Peak memory 216796 kb
Host smart-d4fdd8a6-9eee-4b35-a49b-74aaa36f9ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248858544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_timeout.2248858544
Directory /workspace/48.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/48.spi_device_smoke.665817424
Short name T611
Test name
Test status
Simulation time 62924657 ps
CPU time 1.11 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:23 PM PST 23
Peak memory 208332 kb
Host smart-4feb68fc-571f-40b0-830c-c5c42ef6863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665817424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_smoke.665817424
Directory /workspace/48.spi_device_smoke/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3770058012
Short name T1295
Test name
Test status
Simulation time 18984020231 ps
CPU time 90.84 seconds
Started Dec 24 01:58:18 PM PST 23
Finished Dec 24 01:59:50 PM PST 23
Peak memory 216920 kb
Host smart-fc0894de-2390-4ac6-8f18-def9ba6113c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770058012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3770058012
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2543428894
Short name T1602
Test name
Test status
Simulation time 1908662965 ps
CPU time 11.54 seconds
Started Dec 24 01:58:21 PM PST 23
Finished Dec 24 01:58:34 PM PST 23
Peak memory 216912 kb
Host smart-a7029a99-146b-44cb-a32c-e5b94c77faa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543428894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2543428894
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2209640268
Short name T34
Test name
Test status
Simulation time 810820910 ps
CPU time 5.86 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:28 PM PST 23
Peak memory 216840 kb
Host smart-9943e5ce-f74b-4659-a8f9-faf48e1671b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209640268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2209640268
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3934971348
Short name T861
Test name
Test status
Simulation time 38161662 ps
CPU time 0.84 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 01:58:31 PM PST 23
Peak memory 206960 kb
Host smart-161678bf-a8cb-489b-8cfc-e32306f096e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934971348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3934971348
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tx_async_fifo_reset.2636349097
Short name T984
Test name
Test status
Simulation time 160474939 ps
CPU time 0.84 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 01:58:27 PM PST 23
Peak memory 208440 kb
Host smart-29081ee5-4b85-4a10-b51e-2557575e38e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636349097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tx_async_fifo_reset.2636349097
Directory /workspace/48.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/48.spi_device_txrx.3035873603
Short name T1728
Test name
Test status
Simulation time 43213790964 ps
CPU time 764.33 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 02:11:12 PM PST 23
Peak memory 268240 kb
Host smart-8606a9e2-380b-4f91-b56b-66ebe270d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035873603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_txrx.3035873603
Directory /workspace/48.spi_device_txrx/latest

Test location /workspace/coverage/default/48.spi_device_upload.3698232900
Short name T272
Test name
Test status
Simulation time 6798079748 ps
CPU time 22.91 seconds
Started Dec 24 01:58:26 PM PST 23
Finished Dec 24 01:58:54 PM PST 23
Peak memory 233852 kb
Host smart-9ba95012-480d-49f3-86f5-bc274df023f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698232900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3698232900
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_abort.3599492123
Short name T1756
Test name
Test status
Simulation time 42095829 ps
CPU time 0.73 seconds
Started Dec 24 01:58:20 PM PST 23
Finished Dec 24 01:58:23 PM PST 23
Peak memory 206552 kb
Host smart-7bc6e6f7-ba99-4a33-bd26-3368d70c7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599492123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_abort.3599492123
Directory /workspace/49.spi_device_abort/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3756295454
Short name T953
Test name
Test status
Simulation time 19982648 ps
CPU time 0.76 seconds
Started Dec 24 01:58:19 PM PST 23
Finished Dec 24 01:58:22 PM PST 23
Peak memory 206536 kb
Host smart-0a80c153-94dd-4b34-9a7e-23ecec2a1693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756295454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3756295454
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_bit_transfer.1120774449
Short name T1632
Test name
Test status
Simulation time 369185764 ps
CPU time 2.08 seconds
Started Dec 24 01:58:36 PM PST 23
Finished Dec 24 01:58:40 PM PST 23
Peak memory 216960 kb
Host smart-11bd57dd-d040-48b9-b5f7-65150db90eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120774449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_bit_transfer.1120774449
Directory /workspace/49.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/49.spi_device_byte_transfer.3124983980
Short name T768
Test name
Test status
Simulation time 915463288 ps
CPU time 3.17 seconds
Started Dec 24 01:58:33 PM PST 23
Finished Dec 24 01:58:39 PM PST 23
Peak memory 216876 kb
Host smart-448c0fbe-c747-4d12-b7eb-4cc49cbe016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124983980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_byte_transfer.3124983980
Directory /workspace/49.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3448214024
Short name T1283
Test name
Test status
Simulation time 137025781 ps
CPU time 0.81 seconds
Started Dec 24 01:58:33 PM PST 23
Finished Dec 24 01:58:36 PM PST 23
Peak memory 207600 kb
Host smart-c4255262-12be-42f4-aa59-0390c0893fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448214024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3448214024
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_dummy_item_extra_dly.749690991
Short name T138
Test name
Test status
Simulation time 68535255223 ps
CPU time 479.95 seconds
Started Dec 24 01:58:27 PM PST 23
Finished Dec 24 02:06:32 PM PST 23
Peak memory 303960 kb
Host smart-71926fbb-9ed9-4ee4-a232-202c4880538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749690991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_dummy_item_extra_dly.749690991
Directory /workspace/49.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/49.spi_device_extreme_fifo_size.19374696
Short name T1035
Test name
Test status
Simulation time 61433789053 ps
CPU time 355.84 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 02:04:20 PM PST 23
Peak memory 219276 kb
Host smart-3ec9d889-673a-427e-9f4c-4543a7b153dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19374696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_extreme_fifo_size.19374696
Directory /workspace/49.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/49.spi_device_fifo_full.301100148
Short name T986
Test name
Test status
Simulation time 220976416900 ps
CPU time 1168.08 seconds
Started Dec 24 01:58:24 PM PST 23
Finished Dec 24 02:17:58 PM PST 23
Peak memory 300816 kb
Host smart-b2f8d363-e4b3-4c55-8f6a-ffc2994cf57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301100148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_full.301100148
Directory /workspace/49.spi_device_fifo_full/latest

Test location /workspace/coverage/default/49.spi_device_fifo_underflow_overflow.2144552137
Short name T193
Test name
Test status
Simulation time 136904745869 ps
CPU time 306.45 seconds
Started Dec 24 01:58:34 PM PST 23
Finished Dec 24 02:03:43 PM PST 23
Peak memory 437616 kb
Host smart-f68f7d05-2a5c-4ff9-a257-092e05fcf0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144552137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_underflow_overf
low.2144552137
Directory /workspace/49.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2912035041
Short name T313
Test name
Test status
Simulation time 27852261904 ps
CPU time 206.89 seconds
Started Dec 24 01:58:34 PM PST 23
Finished Dec 24 02:02:04 PM PST 23
Peak memory 272456 kb
Host smart-8bfb785c-e2c7-47bf-bf9e-450782f27034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912035041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2912035041
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3713145201
Short name T215
Test name
Test status
Simulation time 16088344388 ps
CPU time 62.1 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 01:59:33 PM PST 23
Peak memory 250752 kb
Host smart-0d4e6943-7001-4118-bfc8-8819fada9595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713145201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3713145201
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3758311389
Short name T1121
Test name
Test status
Simulation time 38837677275 ps
CPU time 28.76 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 01:58:59 PM PST 23
Peak memory 241248 kb
Host smart-b83eb796-8c19-471a-af41-bff605688302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758311389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3758311389
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.461244897
Short name T896
Test name
Test status
Simulation time 43377601 ps
CPU time 2.79 seconds
Started Dec 24 01:58:35 PM PST 23
Finished Dec 24 01:58:40 PM PST 23
Peak memory 233324 kb
Host smart-12bce989-6d72-4fe9-9548-446215695df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461244897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.461244897
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intr.1172700154
Short name T192
Test name
Test status
Simulation time 4374194884 ps
CPU time 18.94 seconds
Started Dec 24 01:58:31 PM PST 23
Finished Dec 24 01:58:53 PM PST 23
Peak memory 218964 kb
Host smart-89112d6f-4d21-4ac9-9b95-72107627925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172700154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intr.1172700154
Directory /workspace/49.spi_device_intr/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1292241893
Short name T632
Test name
Test status
Simulation time 12982085504 ps
CPU time 18.33 seconds
Started Dec 24 01:58:31 PM PST 23
Finished Dec 24 01:58:52 PM PST 23
Peak memory 248476 kb
Host smart-e43f2dfb-be7d-4974-82d2-3621446529da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292241893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1292241893
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1711495224
Short name T1590
Test name
Test status
Simulation time 8586140392 ps
CPU time 27.55 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 01:58:55 PM PST 23
Peak memory 248512 kb
Host smart-595bb186-3049-4e09-90d4-9b1535222e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711495224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1711495224
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.275313384
Short name T1788
Test name
Test status
Simulation time 1840505920 ps
CPU time 4.22 seconds
Started Dec 24 01:58:33 PM PST 23
Finished Dec 24 01:58:40 PM PST 23
Peak memory 237796 kb
Host smart-2633a871-2821-467f-8aba-732d60ee3df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275313384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.275313384
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_perf.1629746602
Short name T683
Test name
Test status
Simulation time 13322535307 ps
CPU time 830.95 seconds
Started Dec 24 01:58:22 PM PST 23
Finished Dec 24 02:12:17 PM PST 23
Peak memory 239960 kb
Host smart-ef98ce0d-12bd-4f25-9dcd-f066864378a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629746602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_perf.1629746602
Directory /workspace/49.spi_device_perf/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2747699352
Short name T595
Test name
Test status
Simulation time 1217560550 ps
CPU time 6.32 seconds
Started Dec 24 01:58:37 PM PST 23
Finished Dec 24 01:58:46 PM PST 23
Peak memory 234444 kb
Host smart-9adb06b2-3de8-4bea-a057-6028412d0fe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2747699352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2747699352
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_rx_async_fifo_reset.2614825866
Short name T825
Test name
Test status
Simulation time 634182171 ps
CPU time 0.88 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 208368 kb
Host smart-160d4305-94c4-45aa-8566-65201c5a224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614825866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_async_fifo_reset.2614825866
Directory /workspace/49.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_rx_timeout.3932208939
Short name T1407
Test name
Test status
Simulation time 2181747561 ps
CPU time 5.2 seconds
Started Dec 24 01:58:32 PM PST 23
Finished Dec 24 01:58:40 PM PST 23
Peak memory 216880 kb
Host smart-62ad05c5-bf7c-4afd-9fc3-5996d96f2b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932208939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_timeout.3932208939
Directory /workspace/49.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/49.spi_device_smoke.2989733520
Short name T1084
Test name
Test status
Simulation time 45299912 ps
CPU time 1.22 seconds
Started Dec 24 01:58:36 PM PST 23
Finished Dec 24 01:58:39 PM PST 23
Peak memory 216752 kb
Host smart-5a17c7f7-e41c-41d0-8f0e-5b0ed72a46b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989733520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_smoke.2989733520
Directory /workspace/49.spi_device_smoke/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3675820899
Short name T963
Test name
Test status
Simulation time 44810304734 ps
CPU time 88.15 seconds
Started Dec 24 01:58:33 PM PST 23
Finished Dec 24 02:00:04 PM PST 23
Peak memory 216780 kb
Host smart-c2e0070f-39b4-45b2-be5f-a344dc47aa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675820899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3675820899
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3674453518
Short name T1365
Test name
Test status
Simulation time 1591158700 ps
CPU time 6.43 seconds
Started Dec 24 01:58:23 PM PST 23
Finished Dec 24 01:58:35 PM PST 23
Peak memory 216792 kb
Host smart-048be822-e482-4392-a434-5682b52fc408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674453518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3674453518
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2970847370
Short name T1609
Test name
Test status
Simulation time 11007643 ps
CPU time 0.78 seconds
Started Dec 24 01:58:24 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 206892 kb
Host smart-c99354ef-4a3b-4c90-aa3e-0b23255b6147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970847370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2970847370
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.615769426
Short name T1614
Test name
Test status
Simulation time 184397697 ps
CPU time 1.01 seconds
Started Dec 24 01:58:25 PM PST 23
Finished Dec 24 01:58:31 PM PST 23
Peak memory 208128 kb
Host smart-4126a0f6-52f8-4ebe-b028-74bd72bbe3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615769426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.615769426
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tx_async_fifo_reset.1941349557
Short name T1101
Test name
Test status
Simulation time 26767281 ps
CPU time 0.76 seconds
Started Dec 24 01:58:26 PM PST 23
Finished Dec 24 01:58:32 PM PST 23
Peak memory 208440 kb
Host smart-d64c6f1c-e9b8-48a6-924e-77ddc9012e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941349557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tx_async_fifo_reset.1941349557
Directory /workspace/49.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/49.spi_device_txrx.3383142902
Short name T1565
Test name
Test status
Simulation time 20030531975 ps
CPU time 193.09 seconds
Started Dec 24 01:58:24 PM PST 23
Finished Dec 24 02:01:42 PM PST 23
Peak memory 249700 kb
Host smart-0224f819-9212-43bc-8921-342ab0b1a16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383142902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_txrx.3383142902
Directory /workspace/49.spi_device_txrx/latest

Test location /workspace/coverage/default/49.spi_device_upload.198208303
Short name T807
Test name
Test status
Simulation time 14756215814 ps
CPU time 16.9 seconds
Started Dec 24 01:58:24 PM PST 23
Finished Dec 24 01:58:46 PM PST 23
Peak memory 233396 kb
Host smart-d489c88a-eb88-4449-9ce7-932011b68b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198208303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.198208303
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_abort.3403962612
Short name T1752
Test name
Test status
Simulation time 44151589 ps
CPU time 0.75 seconds
Started Dec 24 01:54:11 PM PST 23
Finished Dec 24 01:54:18 PM PST 23
Peak memory 206672 kb
Host smart-aa98ad0b-6d3b-4fd8-8e60-f520fd7c716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403962612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_abort.3403962612
Directory /workspace/5.spi_device_abort/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3607494311
Short name T941
Test name
Test status
Simulation time 12349375 ps
CPU time 0.71 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:54:21 PM PST 23
Peak memory 206540 kb
Host smart-1a37ad4b-d7d0-4232-9f1c-4ab9f4da0f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607494311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
607494311
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_bit_transfer.3971764056
Short name T731
Test name
Test status
Simulation time 97016473 ps
CPU time 2.16 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:21 PM PST 23
Peak memory 216716 kb
Host smart-8b9ac113-1c7c-486c-a81a-86126d18a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971764056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_bit_transfer.3971764056
Directory /workspace/5.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/5.spi_device_byte_transfer.3994237387
Short name T1224
Test name
Test status
Simulation time 75020935 ps
CPU time 2.67 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:19 PM PST 23
Peak memory 216648 kb
Host smart-5715e0f3-c162-4631-9485-87953780537b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994237387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_byte_transfer.3994237387
Directory /workspace/5.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3144331008
Short name T281
Test name
Test status
Simulation time 247323499 ps
CPU time 3.84 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:54:25 PM PST 23
Peak memory 219568 kb
Host smart-a1cb6699-7a6a-4d09-974f-19c639a0166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144331008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3144331008
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1878379105
Short name T589
Test name
Test status
Simulation time 65188203 ps
CPU time 0.78 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 207556 kb
Host smart-975da328-6fea-475f-a8e4-c07f30ef468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878379105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1878379105
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_dummy_item_extra_dly.1355037132
Short name T815
Test name
Test status
Simulation time 48636137489 ps
CPU time 438.38 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 02:01:34 PM PST 23
Peak memory 285080 kb
Host smart-c0c9afd8-acc6-46b2-a4d5-c3d697fc1915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355037132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_dummy_item_extra_dly.1355037132
Directory /workspace/5.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/5.spi_device_extreme_fifo_size.2288265149
Short name T1394
Test name
Test status
Simulation time 204114053427 ps
CPU time 1700.85 seconds
Started Dec 24 01:54:07 PM PST 23
Finished Dec 24 02:22:31 PM PST 23
Peak memory 218804 kb
Host smart-e9ca5cd0-32cf-46d0-9bd0-159baae94771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288265149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_extreme_fifo_size.2288265149
Directory /workspace/5.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/5.spi_device_fifo_full.4094132999
Short name T1445
Test name
Test status
Simulation time 25162053053 ps
CPU time 1440.59 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 02:18:14 PM PST 23
Peak memory 266040 kb
Host smart-17ab8867-9198-43f4-a1e9-6dc9a8098961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094132999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_full.4094132999
Directory /workspace/5.spi_device_fifo_full/latest

Test location /workspace/coverage/default/5.spi_device_fifo_underflow_overflow.1575622286
Short name T536
Test name
Test status
Simulation time 72947729391 ps
CPU time 389.38 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 02:00:41 PM PST 23
Peak memory 391056 kb
Host smart-b3797fe1-c5f6-456c-8172-f71d3a7ee6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575622286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_underflow_overfl
ow.1575622286
Directory /workspace/5.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2763266960
Short name T296
Test name
Test status
Simulation time 4320010892 ps
CPU time 90.37 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:55:50 PM PST 23
Peak memory 270828 kb
Host smart-418caf5e-f29d-4ef4-a033-748c46a2ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763266960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2763266960
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3643426674
Short name T358
Test name
Test status
Simulation time 106963978688 ps
CPU time 197.82 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:57:38 PM PST 23
Peak memory 265820 kb
Host smart-5fb6879b-06da-4282-acab-923b5ba989cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643426674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3643426674
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2990761800
Short name T1004
Test name
Test status
Simulation time 2583769662 ps
CPU time 12.14 seconds
Started Dec 24 01:54:11 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 233288 kb
Host smart-f85bbd50-ba9a-4d51-b62f-652ef2d441f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990761800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2990761800
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1561887738
Short name T1301
Test name
Test status
Simulation time 16642392906 ps
CPU time 6.87 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 219524 kb
Host smart-cae50c22-e501-4a30-b43e-284b3e0999aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561887738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1561887738
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intr.3434523902
Short name T1567
Test name
Test status
Simulation time 40335773628 ps
CPU time 39.28 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:54:59 PM PST 23
Peak memory 222400 kb
Host smart-145bde00-26be-4b5b-8b34-b9ccda931a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434523902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intr.3434523902
Directory /workspace/5.spi_device_intr/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.809460999
Short name T1396
Test name
Test status
Simulation time 3931784830 ps
CPU time 13.1 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 228136 kb
Host smart-181c5be5-b800-4fdb-990e-ad79bd062893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809460999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.809460999
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2116141309
Short name T744
Test name
Test status
Simulation time 112536868 ps
CPU time 1.09 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:17 PM PST 23
Peak memory 218832 kb
Host smart-0ae46e47-a369-421a-982f-8692ee8ee245
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116141309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2116141309
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.87581816
Short name T290
Test name
Test status
Simulation time 2333589646 ps
CPU time 16.21 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:35 PM PST 23
Peak memory 241476 kb
Host smart-6509f840-7f9f-45cc-9ee6-90a23d948ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87581816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.87581816
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3475737909
Short name T300
Test name
Test status
Simulation time 11004852306 ps
CPU time 9.48 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 224036 kb
Host smart-167beb5f-26f9-4194-a613-36853d146792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475737909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3475737909
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_perf.3679769218
Short name T528
Test name
Test status
Simulation time 122302417243 ps
CPU time 780.54 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 267636 kb
Host smart-3c55b998-e276-4ae6-b727-5272e318a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679769218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_perf.3679769218
Directory /workspace/5.spi_device_perf/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3977542149
Short name T871
Test name
Test status
Simulation time 19674310 ps
CPU time 0.72 seconds
Started Dec 24 01:54:09 PM PST 23
Finished Dec 24 01:54:16 PM PST 23
Peak memory 216612 kb
Host smart-f9e1c612-17aa-4c29-a0dd-bafc656d35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977542149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3977542149
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2083735856
Short name T1497
Test name
Test status
Simulation time 675741510 ps
CPU time 5.23 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:26 PM PST 23
Peak memory 219452 kb
Host smart-3fe99412-6257-4a5e-bc0a-6298fe0a4f1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2083735856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2083735856
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_rx_async_fifo_reset.3918071981
Short name T529
Test name
Test status
Simulation time 28210627 ps
CPU time 0.87 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:54:23 PM PST 23
Peak memory 208408 kb
Host smart-2365c0bf-2f1b-45a0-8186-9c7d3e2c806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918071981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_async_fifo_reset.3918071981
Directory /workspace/5.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_rx_timeout.374135741
Short name T1643
Test name
Test status
Simulation time 593359431 ps
CPU time 4.75 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:21 PM PST 23
Peak memory 216704 kb
Host smart-4544d359-c958-4042-8f80-6da614614484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374135741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_timeout.374135741
Directory /workspace/5.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/5.spi_device_smoke.2396563038
Short name T900
Test name
Test status
Simulation time 23630680 ps
CPU time 1.05 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:12 PM PST 23
Peak memory 216468 kb
Host smart-029900dc-27e8-4197-a4a2-44d92b4a71f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396563038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_smoke.2396563038
Directory /workspace/5.spi_device_smoke/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3035325769
Short name T169
Test name
Test status
Simulation time 1477977190851 ps
CPU time 6499.06 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 03:42:39 PM PST 23
Peak memory 457052 kb
Host smart-894a07bf-9ce6-4e46-869b-917e814cd3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035325769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3035325769
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.867391437
Short name T1601
Test name
Test status
Simulation time 46166749450 ps
CPU time 66.75 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:55:24 PM PST 23
Peak memory 216904 kb
Host smart-d7311051-25ea-412f-a392-86f6572ada4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867391437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.867391437
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4088013419
Short name T821
Test name
Test status
Simulation time 2065749577 ps
CPU time 12.09 seconds
Started Dec 24 01:54:10 PM PST 23
Finished Dec 24 01:54:28 PM PST 23
Peak memory 216780 kb
Host smart-b3342f21-abbc-4ce5-8e43-4fd3716d3404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088013419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4088013419
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1839233890
Short name T478
Test name
Test status
Simulation time 165568710 ps
CPU time 2.84 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 01:54:23 PM PST 23
Peak memory 216860 kb
Host smart-307ac884-2032-4743-8cf3-61b2d2172799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839233890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1839233890
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.645783104
Short name T525
Test name
Test status
Simulation time 82988453 ps
CPU time 0.8 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:21 PM PST 23
Peak memory 205892 kb
Host smart-ce3a3de0-2551-4c0a-8523-24717117a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645783104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.645783104
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tx_async_fifo_reset.2306335274
Short name T1204
Test name
Test status
Simulation time 53666999 ps
CPU time 0.78 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 208492 kb
Host smart-a1294011-7d86-45fd-b2a9-433539ed5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306335274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tx_async_fifo_reset.2306335274
Directory /workspace/5.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/5.spi_device_txrx.4123183393
Short name T1252
Test name
Test status
Simulation time 154193822196 ps
CPU time 234 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:58:07 PM PST 23
Peak memory 273884 kb
Host smart-6f0877b3-188b-4207-9b22-f3056bb8df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123183393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_txrx.4123183393
Directory /workspace/5.spi_device_txrx/latest

Test location /workspace/coverage/default/5.spi_device_upload.3969713209
Short name T1110
Test name
Test status
Simulation time 186397519 ps
CPU time 2.77 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 218084 kb
Host smart-8e8302c8-09f3-4fb1-a59c-7b2d4ef4ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969713209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3969713209
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_abort.2911795726
Short name T1268
Test name
Test status
Simulation time 15297656 ps
CPU time 0.75 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 206892 kb
Host smart-6c0f5a8b-235c-4ac1-9bfd-e18e6b4e8103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911795726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_abort.2911795726
Directory /workspace/6.spi_device_abort/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2026791104
Short name T1754
Test name
Test status
Simulation time 57191679 ps
CPU time 0.74 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 206508 kb
Host smart-a84b8d1a-0817-4f0f-a6ab-e7559214ec1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026791104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
026791104
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_bit_transfer.402167421
Short name T1662
Test name
Test status
Simulation time 347768680 ps
CPU time 2.51 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 216756 kb
Host smart-0179c397-2e26-402b-a43a-78e36faac322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402167421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_bit_transfer.402167421
Directory /workspace/6.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/6.spi_device_byte_transfer.3944740741
Short name T979
Test name
Test status
Simulation time 447650769 ps
CPU time 2.94 seconds
Started Dec 24 01:54:08 PM PST 23
Finished Dec 24 01:54:14 PM PST 23
Peak memory 216792 kb
Host smart-87ec6b65-6aab-4cf0-ad44-67272ef964c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944740741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_byte_transfer.3944740741
Directory /workspace/6.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.474859575
Short name T303
Test name
Test status
Simulation time 971094551 ps
CPU time 5.6 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:32 PM PST 23
Peak memory 219264 kb
Host smart-a3789c19-8dee-4bcd-bfcc-6763a3b05d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474859575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.474859575
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2710091643
Short name T647
Test name
Test status
Simulation time 24923367 ps
CPU time 0.75 seconds
Started Dec 24 01:54:06 PM PST 23
Finished Dec 24 01:54:10 PM PST 23
Peak memory 207600 kb
Host smart-70a77738-638f-4866-a540-73104878c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710091643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2710091643
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_dummy_item_extra_dly.795175973
Short name T1409
Test name
Test status
Simulation time 63612682229 ps
CPU time 486.61 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 02:02:28 PM PST 23
Peak memory 298260 kb
Host smart-51934f8c-be66-4a66-b018-adeaae539644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795175973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_dummy_item_extra_dly.795175973
Directory /workspace/6.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/6.spi_device_extreme_fifo_size.2160873372
Short name T1194
Test name
Test status
Simulation time 73907673755 ps
CPU time 1159.71 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 02:13:41 PM PST 23
Peak memory 219764 kb
Host smart-21fc5a62-e07d-4576-be86-5c0f995c6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160873372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_extreme_fifo_size.2160873372
Directory /workspace/6.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/6.spi_device_fifo_full.3282208391
Short name T260
Test name
Test status
Simulation time 55072701801 ps
CPU time 3168.87 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 02:47:08 PM PST 23
Peak memory 268256 kb
Host smart-f21f3e1b-6951-45d4-b498-3d17eb3b38f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282208391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_full.3282208391
Directory /workspace/6.spi_device_fifo_full/latest

Test location /workspace/coverage/default/6.spi_device_fifo_underflow_overflow.3750951866
Short name T1454
Test name
Test status
Simulation time 137705331292 ps
CPU time 760.71 seconds
Started Dec 24 01:54:12 PM PST 23
Finished Dec 24 02:07:00 PM PST 23
Peak memory 475520 kb
Host smart-0265f76b-5e89-443f-8c30-5ec4482a3c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750951866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_underflow_overfl
ow.3750951866
Directory /workspace/6.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.77317632
Short name T286
Test name
Test status
Simulation time 4015074834 ps
CPU time 10.14 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:54:32 PM PST 23
Peak memory 219388 kb
Host smart-f02c0579-2bdd-41d1-b8e2-d6466a592241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77317632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.77317632
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1283243910
Short name T42
Test name
Test status
Simulation time 46961076994 ps
CPU time 342.25 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 02:00:06 PM PST 23
Peak memory 255920 kb
Host smart-72dd8c12-d60d-4ceb-8f04-69b09811c8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283243910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1283243910
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3444338535
Short name T1670
Test name
Test status
Simulation time 18192677677 ps
CPU time 151.89 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:56:57 PM PST 23
Peak memory 253112 kb
Host smart-80ddd7b3-1088-40ce-bb30-8425a7e57b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444338535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3444338535
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3996459748
Short name T1014
Test name
Test status
Simulation time 706691249 ps
CPU time 3.7 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 225080 kb
Host smart-f2046812-da1a-43cc-a9b8-37839d007272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996459748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3996459748
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intr.2460867309
Short name T1537
Test name
Test status
Simulation time 4649114370 ps
CPU time 16.13 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:37 PM PST 23
Peak memory 216956 kb
Host smart-63317731-7808-47cb-be17-e77c32b92057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460867309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intr.2460867309
Directory /workspace/6.spi_device_intr/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.808998220
Short name T239
Test name
Test status
Simulation time 444423459 ps
CPU time 7.2 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 01:54:31 PM PST 23
Peak memory 233092 kb
Host smart-8381a44a-da74-4a67-9855-4ff0337fa475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808998220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.808998220
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2619524524
Short name T1695
Test name
Test status
Simulation time 243800721 ps
CPU time 1.1 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 01:54:25 PM PST 23
Peak memory 218768 kb
Host smart-8850725b-4004-4e90-8f23-7552e29ef5a8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619524524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2619524524
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1506196838
Short name T316
Test name
Test status
Simulation time 10938604970 ps
CPU time 9.78 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 01:54:34 PM PST 23
Peak memory 219588 kb
Host smart-326c0be5-6d79-4854-a146-550f9bba739b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506196838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1506196838
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1872306199
Short name T266
Test name
Test status
Simulation time 3872977758 ps
CPU time 13.16 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:38 PM PST 23
Peak memory 240436 kb
Host smart-bcb4eb6f-56ae-4baa-96b1-e874907d7bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872306199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1872306199
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_perf.3713951875
Short name T565
Test name
Test status
Simulation time 39998283395 ps
CPU time 796.57 seconds
Started Dec 24 01:54:13 PM PST 23
Finished Dec 24 02:07:36 PM PST 23
Peak memory 265556 kb
Host smart-a94e7fe8-599f-42f9-9846-25f1907ed9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713951875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_perf.3713951875
Directory /workspace/6.spi_device_perf/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.1785952734
Short name T1689
Test name
Test status
Simulation time 48252473 ps
CPU time 0.73 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 216724 kb
Host smart-0ace7552-8523-43dc-b579-025cf5457352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785952734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.1785952734
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4198363649
Short name T1203
Test name
Test status
Simulation time 6827392026 ps
CPU time 6.55 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:34 PM PST 23
Peak memory 220620 kb
Host smart-dd34f9bb-3a24-400e-b7c9-1ad06e2cd6f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4198363649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4198363649
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_rx_async_fifo_reset.2658484398
Short name T1177
Test name
Test status
Simulation time 172876592 ps
CPU time 0.81 seconds
Started Dec 24 01:54:25 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 208384 kb
Host smart-9d2e337f-08eb-45dc-a86c-7bff2158a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658484398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_async_fifo_reset.2658484398
Directory /workspace/6.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_rx_timeout.3045609266
Short name T1397
Test name
Test status
Simulation time 2678543927 ps
CPU time 6.16 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 216956 kb
Host smart-f68ae599-20ec-41f2-ac05-6e7924e5966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045609266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_timeout.3045609266
Directory /workspace/6.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/6.spi_device_smoke.2484719905
Short name T517
Test name
Test status
Simulation time 160474233 ps
CPU time 1.18 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:25 PM PST 23
Peak memory 216500 kb
Host smart-d0d3834c-4491-455a-befb-34b1ff46b308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484719905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_smoke.2484719905
Directory /workspace/6.spi_device_smoke/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.370015423
Short name T354
Test name
Test status
Simulation time 2303962809 ps
CPU time 23.08 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:48 PM PST 23
Peak memory 217240 kb
Host smart-a41e9033-5786-40d7-8eb1-c05b23dd976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370015423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.370015423
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.829476555
Short name T1186
Test name
Test status
Simulation time 25505554825 ps
CPU time 21.47 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 01:54:45 PM PST 23
Peak memory 216828 kb
Host smart-741a71c1-286a-46b3-95ab-8f3c68ae9f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829476555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.829476555
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.94827182
Short name T603
Test name
Test status
Simulation time 77000611 ps
CPU time 1.66 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 216776 kb
Host smart-5bc6d92f-3f12-41fe-abbd-3e18f03c2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94827182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.94827182
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2008643737
Short name T607
Test name
Test status
Simulation time 71293012 ps
CPU time 0.97 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:22 PM PST 23
Peak memory 207092 kb
Host smart-e1053395-09a9-41a8-ba52-3f7281e12ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008643737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2008643737
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tx_async_fifo_reset.320075389
Short name T1339
Test name
Test status
Simulation time 15762589 ps
CPU time 0.81 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:26 PM PST 23
Peak memory 208576 kb
Host smart-9f3f13f6-2d8f-48eb-bf9c-4b4add56ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320075389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tx_async_fifo_reset.320075389
Directory /workspace/6.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/6.spi_device_txrx.2381864350
Short name T1338
Test name
Test status
Simulation time 35104454827 ps
CPU time 222.7 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:58:04 PM PST 23
Peak memory 279748 kb
Host smart-5687ae72-ff45-420b-84dd-21dac69eeb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381864350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_txrx.2381864350
Directory /workspace/6.spi_device_txrx/latest

Test location /workspace/coverage/default/6.spi_device_upload.1042995459
Short name T1605
Test name
Test status
Simulation time 28147723608 ps
CPU time 44.38 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:55:10 PM PST 23
Peak memory 249700 kb
Host smart-c0b98315-5419-4e03-9812-abeba05febc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042995459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1042995459
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_abort.3817749705
Short name T682
Test name
Test status
Simulation time 144722925 ps
CPU time 0.71 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:29 PM PST 23
Peak memory 206548 kb
Host smart-b7faea35-902c-4c46-9d2b-e39abf75e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817749705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_abort.3817749705
Directory /workspace/7.spi_device_abort/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2171994988
Short name T1393
Test name
Test status
Simulation time 12488167 ps
CPU time 0.72 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 206524 kb
Host smart-7d026142-790c-4fb0-8550-a29368bd62d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171994988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
171994988
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_bit_transfer.3256686609
Short name T881
Test name
Test status
Simulation time 323884319 ps
CPU time 2.12 seconds
Started Dec 24 01:54:14 PM PST 23
Finished Dec 24 01:54:23 PM PST 23
Peak memory 216836 kb
Host smart-e89926c6-45de-4f45-8903-7ae57e65e10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256686609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_bit_transfer.3256686609
Directory /workspace/7.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/7.spi_device_byte_transfer.390205493
Short name T1555
Test name
Test status
Simulation time 454111527 ps
CPU time 3.61 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 01:54:26 PM PST 23
Peak memory 216796 kb
Host smart-d34e9cf5-de59-4bce-b7f8-5549b0c99bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390205493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_byte_transfer.390205493
Directory /workspace/7.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.130572008
Short name T1410
Test name
Test status
Simulation time 584203338 ps
CPU time 2.7 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 218920 kb
Host smart-d0433b91-ee00-4ed0-be67-0648b73af73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130572008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.130572008
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1519903837
Short name T811
Test name
Test status
Simulation time 19482964 ps
CPU time 0.77 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:28 PM PST 23
Peak memory 207588 kb
Host smart-c33e3f21-a4cc-4c13-87c3-e0adafc45167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519903837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1519903837
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_dummy_item_extra_dly.1178157463
Short name T781
Test name
Test status
Simulation time 216517927367 ps
CPU time 898.73 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 02:09:25 PM PST 23
Peak memory 268228 kb
Host smart-4531c8d3-005d-4b9b-b3a5-475e9762909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178157463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_dummy_item_extra_dly.1178157463
Directory /workspace/7.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/7.spi_device_extreme_fifo_size.522056507
Short name T1388
Test name
Test status
Simulation time 454204947426 ps
CPU time 1467.63 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 02:18:52 PM PST 23
Peak memory 220176 kb
Host smart-005c04c5-582b-47eb-bb14-e57348e877c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522056507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_extreme_fifo_size.522056507
Directory /workspace/7.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/7.spi_device_fifo_underflow_overflow.315407406
Short name T1089
Test name
Test status
Simulation time 359780278652 ps
CPU time 336.5 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 02:00:01 PM PST 23
Peak memory 446260 kb
Host smart-596a21df-a7f4-4830-9854-217316c6a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315407406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_underflow_overflo
w.315407406
Directory /workspace/7.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2751731830
Short name T339
Test name
Test status
Simulation time 209132443534 ps
CPU time 351.54 seconds
Started Dec 24 01:54:24 PM PST 23
Finished Dec 24 02:00:23 PM PST 23
Peak memory 265324 kb
Host smart-f0667a55-d4a9-4b67-b296-733b85b5ba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751731830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2751731830
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1781069232
Short name T1452
Test name
Test status
Simulation time 31867904154 ps
CPU time 128.75 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:56:37 PM PST 23
Peak memory 262360 kb
Host smart-cc76d99a-5f50-4bbb-8f07-5eb72ac8a599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781069232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1781069232
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3657928316
Short name T1091
Test name
Test status
Simulation time 2999762868 ps
CPU time 22.94 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:51 PM PST 23
Peak memory 249680 kb
Host smart-eeb5b327-4420-43c5-9770-45bd6abb4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657928316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3657928316
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.312544635
Short name T1657
Test name
Test status
Simulation time 622190620 ps
CPU time 7.09 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:34 PM PST 23
Peak memory 240492 kb
Host smart-901aa401-e095-4d2d-a2c2-b3e188fdc63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312544635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.312544635
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intr.704204040
Short name T939
Test name
Test status
Simulation time 12719145351 ps
CPU time 56.67 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:55:22 PM PST 23
Peak memory 225200 kb
Host smart-df748e05-7e63-4e32-a407-cc9b04b2bf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704204040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intr.704204040
Directory /workspace/7.spi_device_intr/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.560658312
Short name T1702
Test name
Test status
Simulation time 37758150 ps
CPU time 2.88 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:31 PM PST 23
Peak memory 226188 kb
Host smart-375b2f3b-0915-42ae-8b5f-5601179464fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560658312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.560658312
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1607916139
Short name T730
Test name
Test status
Simulation time 98412010 ps
CPU time 1 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:28 PM PST 23
Peak memory 217880 kb
Host smart-f8f89193-7ae7-478f-b87c-f678abfc5866
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607916139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1607916139
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.518333159
Short name T1037
Test name
Test status
Simulation time 572949055 ps
CPU time 5.56 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:31 PM PST 23
Peak memory 238812 kb
Host smart-4153b3a8-6de5-46ab-b1e4-581af16b3d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518333159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
518333159
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.340271366
Short name T237
Test name
Test status
Simulation time 3351148994 ps
CPU time 12.91 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:39 PM PST 23
Peak memory 229520 kb
Host smart-33f7d5b0-6093-451f-b75c-f2706c365e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340271366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.340271366
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_perf.3792604555
Short name T1627
Test name
Test status
Simulation time 37766271995 ps
CPU time 626.54 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 02:04:48 PM PST 23
Peak memory 253760 kb
Host smart-d8c85ac2-326f-4b39-bcf7-2b147dcfeb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792604555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_perf.3792604555
Directory /workspace/7.spi_device_perf/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.473890864
Short name T1351
Test name
Test status
Simulation time 49379128 ps
CPU time 0.72 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:25 PM PST 23
Peak memory 216688 kb
Host smart-9181e6a4-b36b-41ef-b8c3-60b1259e4fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473890864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.473890864
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2380109672
Short name T754
Test name
Test status
Simulation time 15730709703 ps
CPU time 6.83 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:54:38 PM PST 23
Peak memory 234592 kb
Host smart-8f254861-1ba4-411b-8674-0233c20e4399
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380109672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2380109672
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_rx_async_fifo_reset.1875050644
Short name T591
Test name
Test status
Simulation time 27804754 ps
CPU time 0.89 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:28 PM PST 23
Peak memory 208524 kb
Host smart-2185313a-3af7-484e-88dd-931bbeb9f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875050644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_async_fifo_reset.1875050644
Directory /workspace/7.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_rx_timeout.4053823333
Short name T1618
Test name
Test status
Simulation time 690439298 ps
CPU time 6.66 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 216828 kb
Host smart-ad45e58d-7b7e-4b18-b138-8c31fd7f2b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053823333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_timeout.4053823333
Directory /workspace/7.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/7.spi_device_smoke.3094904797
Short name T1423
Test name
Test status
Simulation time 45973780 ps
CPU time 0.92 seconds
Started Dec 24 01:54:16 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 207952 kb
Host smart-add96bf0-b133-42c3-a22c-43a1baee17e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094904797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_smoke.3094904797
Directory /workspace/7.spi_device_smoke/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3736967898
Short name T1146
Test name
Test status
Simulation time 2858603570 ps
CPU time 41.12 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:55:09 PM PST 23
Peak memory 217000 kb
Host smart-20973cf9-7e32-4048-b2b0-e1c62796420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736967898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3736967898
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.184768146
Short name T1221
Test name
Test status
Simulation time 12836433127 ps
CPU time 12.8 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:41 PM PST 23
Peak memory 216864 kb
Host smart-15933a26-934c-4ac3-940e-5297af68f8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184768146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.184768146
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1452020413
Short name T634
Test name
Test status
Simulation time 170714366 ps
CPU time 1.8 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 216804 kb
Host smart-72d2965e-4909-490b-9937-e0f81ba241f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452020413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1452020413
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1301378117
Short name T878
Test name
Test status
Simulation time 209033779 ps
CPU time 1.04 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:29 PM PST 23
Peak memory 207972 kb
Host smart-71897ab2-4c05-4014-9232-11b3a12b0c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301378117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1301378117
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tx_async_fifo_reset.3285612073
Short name T649
Test name
Test status
Simulation time 17997438 ps
CPU time 0.78 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:28 PM PST 23
Peak memory 208572 kb
Host smart-d5a60b8a-dbbe-417b-9cdf-b3299c69464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285612073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tx_async_fifo_reset.3285612073
Directory /workspace/7.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/7.spi_device_txrx.107997206
Short name T1617
Test name
Test status
Simulation time 233299117010 ps
CPU time 205.9 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:57:50 PM PST 23
Peak memory 241512 kb
Host smart-e6c3e470-e607-4915-83bb-096016f7fa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107997206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_txrx.107997206
Directory /workspace/7.spi_device_txrx/latest

Test location /workspace/coverage/default/7.spi_device_upload.300474565
Short name T1134
Test name
Test status
Simulation time 18938220846 ps
CPU time 17.89 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:43 PM PST 23
Peak memory 241448 kb
Host smart-6c7ba81b-3153-49ad-8e90-51a372eea261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300474565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.300474565
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_abort.61584094
Short name T576
Test name
Test status
Simulation time 144407814 ps
CPU time 0.76 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 206644 kb
Host smart-743da5e0-9bcb-44f1-be6a-89a006c1e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61584094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_abort.61584094
Directory /workspace/8.spi_device_abort/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.552380524
Short name T1018
Test name
Test status
Simulation time 15373146 ps
CPU time 0.71 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 206408 kb
Host smart-3b8ccdbf-ab57-457d-805e-6d38b62f3dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552380524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.552380524
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_bit_transfer.2788441767
Short name T669
Test name
Test status
Simulation time 670730328 ps
CPU time 2.23 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 216792 kb
Host smart-81fed655-a7bf-49fb-a569-d3431533205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788441767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_bit_transfer.2788441767
Directory /workspace/8.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/8.spi_device_byte_transfer.1957826458
Short name T1225
Test name
Test status
Simulation time 154051528 ps
CPU time 2.88 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 01:54:32 PM PST 23
Peak memory 216768 kb
Host smart-d3b1a829-148e-45e2-8ec5-da2995b85e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957826458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_byte_transfer.1957826458
Directory /workspace/8.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3210800706
Short name T1640
Test name
Test status
Simulation time 160706623 ps
CPU time 3.08 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:36 PM PST 23
Peak memory 239756 kb
Host smart-32f0947a-3b22-4066-8034-73f2b7031f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210800706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3210800706
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4102890424
Short name T1412
Test name
Test status
Simulation time 231973582 ps
CPU time 0.8 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 207552 kb
Host smart-f51047b5-b19b-47e1-ae7f-84da62eb0ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102890424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4102890424
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_dummy_item_extra_dly.607043990
Short name T1201
Test name
Test status
Simulation time 179748164983 ps
CPU time 229.79 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:58:21 PM PST 23
Peak memory 291460 kb
Host smart-c1546c99-f480-4434-82b6-f6caf1ab067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607043990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_dummy_item_extra_dly.607043990
Directory /workspace/8.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/8.spi_device_extreme_fifo_size.3539632481
Short name T1167
Test name
Test status
Simulation time 10037479959 ps
CPU time 47.94 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:55:19 PM PST 23
Peak memory 241280 kb
Host smart-b6126e66-47dd-4818-b3b6-cdef8d73b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539632481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_extreme_fifo_size.3539632481
Directory /workspace/8.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/8.spi_device_fifo_full.4070241867
Short name T538
Test name
Test status
Simulation time 16957827982 ps
CPU time 1008.62 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 02:11:17 PM PST 23
Peak memory 297624 kb
Host smart-bc0271d7-0e7f-4ef9-b472-9a9f3f323d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070241867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_full.4070241867
Directory /workspace/8.spi_device_fifo_full/latest

Test location /workspace/coverage/default/8.spi_device_fifo_underflow_overflow.1061272993
Short name T773
Test name
Test status
Simulation time 59000400990 ps
CPU time 253.78 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:58:43 PM PST 23
Peak memory 309412 kb
Host smart-755234a2-144e-4ba0-abaa-c908219c577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061272993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_underflow_overfl
ow.1061272993
Directory /workspace/8.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2893051162
Short name T1178
Test name
Test status
Simulation time 8880675114 ps
CPU time 75.29 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:55:48 PM PST 23
Peak memory 267024 kb
Host smart-f2a9b84a-5f68-4d9e-a3c0-51a3fcbee999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893051162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2893051162
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1331329121
Short name T1623
Test name
Test status
Simulation time 262140920109 ps
CPU time 227.62 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:58:16 PM PST 23
Peak memory 269584 kb
Host smart-e9ef8cec-685d-40ef-965f-a576b8121d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331329121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1331329121
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1707939069
Short name T1546
Test name
Test status
Simulation time 84039616856 ps
CPU time 377.13 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 02:00:45 PM PST 23
Peak memory 266112 kb
Host smart-0734cc2c-bf83-4fc7-a968-2bf53ec2ce18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707939069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1707939069
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3222508916
Short name T1558
Test name
Test status
Simulation time 558463950 ps
CPU time 13.43 seconds
Started Dec 24 01:54:25 PM PST 23
Finished Dec 24 01:54:45 PM PST 23
Peak memory 249144 kb
Host smart-272ce402-5c1b-4c61-a87d-3e29beebb89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222508916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3222508916
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1034460863
Short name T275
Test name
Test status
Simulation time 477521629 ps
CPU time 5.77 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:34 PM PST 23
Peak memory 220352 kb
Host smart-c04214df-8154-462d-83cc-c9218298f658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034460863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1034460863
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intr.984926729
Short name T206
Test name
Test status
Simulation time 15464568396 ps
CPU time 21.76 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:51 PM PST 23
Peak memory 220740 kb
Host smart-60e2d3c5-160f-47d8-8be5-03ab35deb3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984926729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intr.984926729
Directory /workspace/8.spi_device_intr/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.685330040
Short name T1352
Test name
Test status
Simulation time 839094820 ps
CPU time 15.58 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:46 PM PST 23
Peak memory 234192 kb
Host smart-57bd741e-581d-479c-9e25-e73f249a6f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685330040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.685330040
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3086066159
Short name T1364
Test name
Test status
Simulation time 14868345 ps
CPU time 1 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:54:32 PM PST 23
Peak memory 218904 kb
Host smart-2a09e33d-fddc-42b1-8083-ddbc6c025e90
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086066159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3086066159
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1290058551
Short name T1649
Test name
Test status
Simulation time 289250494 ps
CPU time 6.1 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:54:37 PM PST 23
Peak memory 246968 kb
Host smart-e950263c-0cf9-4e6a-9e1e-d18cae217ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290058551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1290058551
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1640305668
Short name T924
Test name
Test status
Simulation time 5133257997 ps
CPU time 14.97 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:42 PM PST 23
Peak memory 219860 kb
Host smart-deaa053a-3a4d-4eb0-937e-c744ba6210c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640305668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1640305668
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_perf.554312194
Short name T1519
Test name
Test status
Simulation time 26207729562 ps
CPU time 550.59 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 02:03:41 PM PST 23
Peak memory 272032 kb
Host smart-c62d8f04-51d0-448f-a69a-97a31f5e5f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554312194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_perf.554312194
Directory /workspace/8.spi_device_perf/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1913227747
Short name T1124
Test name
Test status
Simulation time 37248067 ps
CPU time 0.72 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 216664 kb
Host smart-b8f55e7e-4865-425e-ac32-4391aad1d000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913227747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1913227747
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3424973308
Short name T172
Test name
Test status
Simulation time 253249190 ps
CPU time 3.61 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:32 PM PST 23
Peak memory 220292 kb
Host smart-043f030d-ebd1-4010-95cb-19cf72441b71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3424973308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3424973308
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_rx_async_fifo_reset.167859695
Short name T544
Test name
Test status
Simulation time 183890518 ps
CPU time 0.95 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:31 PM PST 23
Peak memory 208416 kb
Host smart-ef14b096-0369-412e-8780-0a1da68e5207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167859695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_async_fifo_reset.167859695
Directory /workspace/8.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_rx_timeout.3913532251
Short name T671
Test name
Test status
Simulation time 2582565041 ps
CPU time 5.26 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:34 PM PST 23
Peak memory 216864 kb
Host smart-6d17c4ee-3cf4-4ed6-9467-5bc565072480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913532251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_timeout.3913532251
Directory /workspace/8.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/8.spi_device_smoke.1492452293
Short name T646
Test name
Test status
Simulation time 79193892 ps
CPU time 1.03 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:31 PM PST 23
Peak memory 207968 kb
Host smart-e3bb5ed7-cfd9-4128-b6a9-42ca9ce9f2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492452293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_smoke.1492452293
Directory /workspace/8.spi_device_smoke/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.952890185
Short name T196
Test name
Test status
Simulation time 460768827818 ps
CPU time 3291.22 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 02:49:17 PM PST 23
Peak memory 458632 kb
Host smart-1f2acb4b-0062-4030-9f50-f7dffc39ba29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952890185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.952890185
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4139532685
Short name T500
Test name
Test status
Simulation time 1221621819 ps
CPU time 3.56 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 01:54:32 PM PST 23
Peak memory 216848 kb
Host smart-8a396da0-a952-434c-97fa-73ca208c68db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139532685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4139532685
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1036574209
Short name T822
Test name
Test status
Simulation time 8960687766 ps
CPU time 10.43 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 01:54:39 PM PST 23
Peak memory 216760 kb
Host smart-8353f093-a5d1-4598-bf2e-333a36dda153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036574209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1036574209
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3280859746
Short name T1729
Test name
Test status
Simulation time 176492178 ps
CPU time 7.63 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:54:38 PM PST 23
Peak memory 216796 kb
Host smart-1ef1b2e0-0d2d-4f69-a36f-37a6bb404546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280859746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3280859746
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1784811123
Short name T106
Test name
Test status
Simulation time 73201602 ps
CPU time 0.73 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 206824 kb
Host smart-32009ba0-4656-4aaf-b4bd-5d3ececc8a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784811123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1784811123
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tx_async_fifo_reset.663412021
Short name T507
Test name
Test status
Simulation time 14282207 ps
CPU time 0.76 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 01:54:30 PM PST 23
Peak memory 208424 kb
Host smart-bbc4d891-6acc-4006-b3c2-9bb0d37cf5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663412021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tx_async_fifo_reset.663412021
Directory /workspace/8.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/8.spi_device_txrx.2782050580
Short name T831
Test name
Test status
Simulation time 56488526078 ps
CPU time 709.49 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 02:06:18 PM PST 23
Peak memory 334580 kb
Host smart-46c22e01-a23d-47fb-90fb-9c619b51425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782050580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_txrx.2782050580
Directory /workspace/8.spi_device_txrx/latest

Test location /workspace/coverage/default/8.spi_device_upload.2240193316
Short name T1673
Test name
Test status
Simulation time 4226480392 ps
CPU time 14.11 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:54:47 PM PST 23
Peak memory 219096 kb
Host smart-99c870a6-b627-4051-9d56-5d32264cc6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240193316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2240193316
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_abort.927578770
Short name T848
Test name
Test status
Simulation time 15081512 ps
CPU time 0.78 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 206628 kb
Host smart-137d0b8a-53d3-4e81-8b0a-ae02651e3bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927578770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_abort.927578770
Directory /workspace/9.spi_device_abort/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1963974958
Short name T796
Test name
Test status
Simulation time 92136549 ps
CPU time 0.7 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:34 PM PST 23
Peak memory 206548 kb
Host smart-47243dfd-42ca-45be-962b-513220aa96b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963974958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
963974958
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_bit_transfer.1577987526
Short name T1386
Test name
Test status
Simulation time 708374051 ps
CPU time 3.28 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:29 PM PST 23
Peak memory 216824 kb
Host smart-c93de5fe-b69b-40e7-b724-00b0a7708ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577987526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_bit_transfer.1577987526
Directory /workspace/9.spi_device_bit_transfer/latest

Test location /workspace/coverage/default/9.spi_device_byte_transfer.407556626
Short name T1639
Test name
Test status
Simulation time 956039739 ps
CPU time 3.21 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:29 PM PST 23
Peak memory 216832 kb
Host smart-4160a9ab-f2a0-40a3-97dc-2d34f891bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407556626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_byte_transfer.407556626
Directory /workspace/9.spi_device_byte_transfer/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.784994622
Short name T1105
Test name
Test status
Simulation time 12073162533 ps
CPU time 12.43 seconds
Started Dec 24 01:54:26 PM PST 23
Finished Dec 24 01:54:45 PM PST 23
Peak memory 241552 kb
Host smart-62fb0a08-115b-4ea6-b946-86a70292070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784994622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.784994622
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1507914614
Short name T1465
Test name
Test status
Simulation time 23139574 ps
CPU time 0.77 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 207632 kb
Host smart-c3e03849-e5fa-489d-8a89-2ae8e2213526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507914614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1507914614
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_dummy_item_extra_dly.1510283746
Short name T1619
Test name
Test status
Simulation time 125806850994 ps
CPU time 375.63 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 02:00:45 PM PST 23
Peak memory 260488 kb
Host smart-090103e3-c82d-4002-b335-3dd247e9b188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510283746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_dummy_item_extra_dly.1510283746
Directory /workspace/9.spi_device_dummy_item_extra_dly/latest

Test location /workspace/coverage/default/9.spi_device_extreme_fifo_size.3645240646
Short name T1450
Test name
Test status
Simulation time 165025009566 ps
CPU time 3889.65 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 02:59:17 PM PST 23
Peak memory 225216 kb
Host smart-30b7b242-f834-46a9-8cfa-58fd2375a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645240646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_extreme_fifo_size.3645240646
Directory /workspace/9.spi_device_extreme_fifo_size/latest

Test location /workspace/coverage/default/9.spi_device_fifo_full.2388043071
Short name T1336
Test name
Test status
Simulation time 247803161507 ps
CPU time 1067.84 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 02:12:13 PM PST 23
Peak memory 266448 kb
Host smart-b2e35aa7-e355-404d-87e0-7b38a4367397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388043071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_full.2388043071
Directory /workspace/9.spi_device_fifo_full/latest

Test location /workspace/coverage/default/9.spi_device_fifo_underflow_overflow.1226993704
Short name T794
Test name
Test status
Simulation time 201725424526 ps
CPU time 404.93 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 02:01:11 PM PST 23
Peak memory 354416 kb
Host smart-7e4fb23e-a25d-4f3f-949d-53512c282311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226993704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_underflow_overfl
ow.1226993704
Directory /workspace/9.spi_device_fifo_underflow_overflow/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3538634557
Short name T319
Test name
Test status
Simulation time 104034170471 ps
CPU time 321.56 seconds
Started Dec 24 01:54:24 PM PST 23
Finished Dec 24 01:59:53 PM PST 23
Peak memory 269736 kb
Host smart-0ebd59da-3a5b-4acc-b47c-a9843d9aa44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538634557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3538634557
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2250782957
Short name T932
Test name
Test status
Simulation time 4295118819 ps
CPU time 25.52 seconds
Started Dec 24 01:54:25 PM PST 23
Finished Dec 24 01:54:58 PM PST 23
Peak memory 250852 kb
Host smart-0e5feaa9-8037-4ce5-b46a-775c037e3a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250782957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2250782957
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.216580822
Short name T178
Test name
Test status
Simulation time 690691650 ps
CPU time 13.7 seconds
Started Dec 24 01:54:24 PM PST 23
Finished Dec 24 01:54:45 PM PST 23
Peak memory 239804 kb
Host smart-99d26e9a-f2dd-47f9-8132-bef6bfa3f3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216580822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.216580822
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2635789578
Short name T305
Test name
Test status
Simulation time 380549856 ps
CPU time 3.35 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:31 PM PST 23
Peak memory 238220 kb
Host smart-8ebe34a7-c4a9-4387-a59d-4e93d02b2885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635789578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2635789578
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intr.3606670513
Short name T1242
Test name
Test status
Simulation time 41171193366 ps
CPU time 30.68 seconds
Started Dec 24 01:54:19 PM PST 23
Finished Dec 24 01:54:57 PM PST 23
Peak memory 224440 kb
Host smart-122582f6-b34c-4f46-a161-d18a1f725a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606670513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intr.3606670513
Directory /workspace/9.spi_device_intr/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3131292403
Short name T1086
Test name
Test status
Simulation time 4073896690 ps
CPU time 9.52 seconds
Started Dec 24 01:54:23 PM PST 23
Finished Dec 24 01:54:40 PM PST 23
Peak memory 219740 kb
Host smart-a68733ab-9174-403d-853f-c1943be108b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131292403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3131292403
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.764712797
Short name T47
Test name
Test status
Simulation time 30761312 ps
CPU time 1.08 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:29 PM PST 23
Peak memory 217804 kb
Host smart-c55b6742-bfc2-4acb-9ae9-df04e8458287
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764712797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.764712797
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.28403318
Short name T1007
Test name
Test status
Simulation time 11279548395 ps
CPU time 14.15 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:40 PM PST 23
Peak memory 241476 kb
Host smart-6c53c90c-0ca8-4aef-852b-3a59298a7218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28403318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.28403318
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4286902864
Short name T1292
Test name
Test status
Simulation time 27459752107 ps
CPU time 21.31 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:51 PM PST 23
Peak memory 227356 kb
Host smart-0099946d-2342-4cfe-bc8d-93e7fca18d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286902864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4286902864
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_perf.476633105
Short name T1621
Test name
Test status
Simulation time 44504277047 ps
CPU time 753.73 seconds
Started Dec 24 01:54:24 PM PST 23
Finished Dec 24 02:07:06 PM PST 23
Peak memory 266192 kb
Host smart-aa76f651-7f89-4fd5-a37e-1a431b69c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476633105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_perf.476633105
Directory /workspace/9.spi_device_perf/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3096012979
Short name T593
Test name
Test status
Simulation time 45083386 ps
CPU time 0.72 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:29 PM PST 23
Peak memory 216820 kb
Host smart-a4d279f9-9baa-4507-af9d-27d2d0e251cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096012979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3096012979
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1122232785
Short name T938
Test name
Test status
Simulation time 209755642 ps
CPU time 4.06 seconds
Started Dec 24 01:54:29 PM PST 23
Finished Dec 24 01:54:38 PM PST 23
Peak memory 236204 kb
Host smart-ffd4a5b2-5ea2-438b-acef-398e34d51b15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1122232785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1122232785
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_rx_async_fifo_reset.3787279567
Short name T694
Test name
Test status
Simulation time 344233762 ps
CPU time 0.97 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:26 PM PST 23
Peak memory 208492 kb
Host smart-448e7643-a545-40c8-9c6b-7c4ca89812f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787279567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_async_fifo_reset.3787279567
Directory /workspace/9.spi_device_rx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_rx_timeout.1220729724
Short name T905
Test name
Test status
Simulation time 2382889762 ps
CPU time 5.4 seconds
Started Dec 24 01:54:20 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 216888 kb
Host smart-802a776e-40ce-46c1-b650-8e84fe652326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220729724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_timeout.1220729724
Directory /workspace/9.spi_device_rx_timeout/latest

Test location /workspace/coverage/default/9.spi_device_smoke.1552549549
Short name T1525
Test name
Test status
Simulation time 32737409 ps
CPU time 1.15 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:27 PM PST 23
Peak memory 208364 kb
Host smart-06275b74-cc3d-43ca-93df-54809114c351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552549549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_smoke.1552549549
Directory /workspace/9.spi_device_smoke/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3345984220
Short name T170
Test name
Test status
Simulation time 146107731537 ps
CPU time 281.71 seconds
Started Dec 24 01:54:28 PM PST 23
Finished Dec 24 01:59:16 PM PST 23
Peak memory 273976 kb
Host smart-1c7a4e5e-6b82-45d8-b8ad-2b0b4c0fa775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345984220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3345984220
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1316764272
Short name T1730
Test name
Test status
Simulation time 2775062889 ps
CPU time 23.17 seconds
Started Dec 24 01:54:21 PM PST 23
Finished Dec 24 01:54:52 PM PST 23
Peak memory 216836 kb
Host smart-1a9d9f4f-b283-435f-806b-7b9f79c782a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316764272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1316764272
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1835277570
Short name T1693
Test name
Test status
Simulation time 27714799569 ps
CPU time 16.4 seconds
Started Dec 24 01:54:17 PM PST 23
Finished Dec 24 01:54:40 PM PST 23
Peak memory 219592 kb
Host smart-edaaedb2-7712-4831-b74f-626ed044f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835277570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1835277570
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1377095638
Short name T1119
Test name
Test status
Simulation time 68075574 ps
CPU time 1.98 seconds
Started Dec 24 01:54:22 PM PST 23
Finished Dec 24 01:54:33 PM PST 23
Peak memory 216808 kb
Host smart-62ccbc12-74cb-4263-b23f-6ce487b6f0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377095638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1377095638
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.99656784
Short name T1692
Test name
Test status
Simulation time 19883638 ps
CPU time 0.76 seconds
Started Dec 24 01:54:18 PM PST 23
Finished Dec 24 01:54:26 PM PST 23
Peak memory 206932 kb
Host smart-c5a5472d-8135-4c62-8d83-f9901a42d6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99656784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.99656784
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tx_async_fifo_reset.1740106290
Short name T1107
Test name
Test status
Simulation time 16863694 ps
CPU time 0.79 seconds
Started Dec 24 01:54:24 PM PST 23
Finished Dec 24 01:54:32 PM PST 23
Peak memory 208500 kb
Host smart-5b239e73-99e3-48cb-824b-6c5bc08e1aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740106290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tx_async_fifo_reset.1740106290
Directory /workspace/9.spi_device_tx_async_fifo_reset/latest

Test location /workspace/coverage/default/9.spi_device_txrx.2792108969
Short name T1563
Test name
Test status
Simulation time 48815944366 ps
CPU time 127.36 seconds
Started Dec 24 01:54:15 PM PST 23
Finished Dec 24 01:56:29 PM PST 23
Peak memory 265504 kb
Host smart-571fde8b-9923-4b9f-98a9-05382d339290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792108969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_txrx.2792108969
Directory /workspace/9.spi_device_txrx/latest

Test location /workspace/coverage/default/9.spi_device_upload.2294365161
Short name T1031
Test name
Test status
Simulation time 2654399231 ps
CPU time 4.16 seconds
Started Dec 24 01:54:27 PM PST 23
Finished Dec 24 01:54:37 PM PST 23
Peak memory 219476 kb
Host smart-4fa18e97-adac-4ca2-b97e-a845d1152c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294365161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2294365161
Directory /workspace/9.spi_device_upload/latest
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