SPI_DEVICE Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.360s	166.227us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	50.781us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.670s	101.510us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.050s	9.080ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.910s	366.643us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.970s	69.824us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.670s	101.510us	20	20	100.00
		spi_device_csr_aliasing	24.910s	366.643us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	13.520s	3.556ms	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.890s	401.178us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	20.586m	105.016ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	52.814m	55.073ms	49	50	98.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	28.600m	1.500s	48	50	96.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	48.402m	456.221ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	48.402m	456.221ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.840s	196.021us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	1.030s	59.930us	50	50	100.00
V2	interrupts	spi_device_intr	2.070m	154.119ms	48	50	96.00
V2	abort	spi_device_abort	0.820s	15.225us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.790s	285.365us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.200s	4.968ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.480s	1.906ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.224h	83.261ms	50	50	100.00
V2	perf	spi_device_perf	56.431m	55.332ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.840s	43.917us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	243.801us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	27.427us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	21.350s	562.697us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	21.350s	562.697us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.060s	38.608ms	50	50	100.00
		spi_device_tpm_sts_read	1.170s	168.868us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.504m	41.718ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	49.520s	18.572ms	50	50	100.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	47.010s	24.321ms	50	50	100.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	47.010s	24.321ms	50	50	100.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	cmd_info_slots	spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	cmd_read_status	spi_device_intercept	13.680s	13.800ms	49	50	98.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	cmd_read_jedec	spi_device_intercept	13.680s	13.800ms	49	50	98.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	cmd_read_sfdp	spi_device_intercept	13.680s	13.800ms	49	50	98.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	cmd_fast_read	spi_device_intercept	13.680s	13.800ms	49	50	98.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	flash_cmd_upload	spi_device_upload	44.380s	28.148ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	49.730s	77.085ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	49.730s	77.085ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	49.730s	77.085ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.513m	18.871ms	47	50	94.00
		spi_device_read_buffer_direct	7.990s	6.754ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	49.730s	77.085ms	50	50	100.00
		spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	quad_spi	spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	dual_spi	spi_device_flash_all	7.439m	98.379ms	48	50	96.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.770s	3.991ms	48	50	96.00
V2	write_enable_disable	spi_device_cfg_cmd	12.770s	3.991ms	48	50	96.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.931m	236.947ms	45	50	90.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.677m	408.412ms	48	50	96.00
V2	stress_all	spi_device_stress_all	2.591h	276.335ms	41	50	82.00
V2	alert_test	spi_device_alert_test	0.800s	39.373us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	56.314us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.430s	900.429us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.430s	900.429us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	50.781us	5	5	100.00
		spi_device_csr_rw	2.670s	101.510us	20	20	100.00
		spi_device_csr_aliasing	24.910s	366.643us	5	5	100.00
		spi_device_same_csr_outstanding	4.550s	118.103us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	50.781us	5	5	100.00
		spi_device_csr_rw	2.670s	101.510us	20	20	100.00
		spi_device_csr_aliasing	24.910s	366.643us	5	5	100.00
		spi_device_same_csr_outstanding	4.550s	118.103us	20	20	100.00
V2		TOTAL			1651	1680	98.27
V2S	tl_intg_err	spi_device_sec_cm	1.190s	82.885us	5	5	100.00
		spi_device_tl_intg_err	22.660s	1.000ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.660s	1.000ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1791	1820	98.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	26	72.22
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	99.01	96.35	98.63	92.06	98.05	95.86	99.76

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 9 failures:

Test spi_device_flash_all has 1 failures.

11.spi_device_flash_all.77934289003189092616662511232545675265342200301888968071384636046087141238917
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 8906584304 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 10443531283 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/17
  UVM_INFO @ 11903822315 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/17
  UVM_INFO @ 14064159061 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/17
  UVM_INFO @ 16300394743 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/17

Test spi_device_flash_and_tpm has 3 failures.

14.spi_device_flash_and_tpm.54447150709870171613457140248569082374241169218866094769681215455452723726229
Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 13068553861 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 13196600596 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/18
  UVM_INFO @ 14105569574 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/18
  UVM_INFO @ 14423976506 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 10/18
  UVM_INFO @ 15249302941 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 11/18

36.spi_device_flash_and_tpm.31970274515303378993133657763959688351685982738212975974094431551582720397426
Line 271, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 16046385506 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 16535097749 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 14/14
  UVM_INFO @ 17268485446 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/20
  UVM_INFO @ 18539126556 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/20
  UVM_INFO @ 19492944655 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/20

... and 1 more failures.

Test spi_device_cfg_cmd has 2 failures.

22.spi_device_cfg_cmd.37568002640528471682034840537442732850160537600563590676500688550695032214420
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 202376567 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 203358702 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x6
  UVM_INFO @ 205340829 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0x6
  UVM_INFO @ 207983665 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0x6
  UVM_INFO @ 210144362 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0x4

49.spi_device_cfg_cmd.66252971162563936017493070832556749052777368107554604743884688181587355480630
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 210978026 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 213144710 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 10, test op = 0xb7
  UVM_INFO @ 217269743 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 11, test op = 0x6
  UVM_INFO @ 245394928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_stress_all has 2 failures.

23.spi_device_stress_all.99486278729963520187965978324201433768603148411020157105931982665845189525719
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 6189052668 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 6192267308 ps: (spi_monitor.sv:322) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bx (x [0xx] vs x [0xx])
  UVM_ERROR @ 6192267308 ps: (spi_monitor.sv:322) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bx (x [0xx] vs x [0xx])
  UVM_ERROR @ 6192267308 ps: (spi_monitor.sv:322) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bx (x [0xx] vs x [0xx])
  UVM_INFO @ 6202902045 ps: (uvm_comparer.svh:351) [MISCMP] Miscompare for host_item.payload_q:

32.spi_device_stress_all.54397056695306911894164786996354735153460144159134454249665435561561543022574
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/32.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 373117724 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 527704200 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/17
  UVM_INFO @ 613809676 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/18
  UVM_INFO @ 873603516 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/18
  UVM_INFO @ 1280158094 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/17

Test spi_device_flash_and_tpm_min_idle has 1 failures.

40.spi_device_flash_and_tpm_min_idle.112379405170912576183253978372689252107085522241260091491297744761410992664012
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 826519341 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 891833171 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/14
  UVM_INFO @ 936363344 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/8
  UVM_INFO @ 1058996577 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/14
  UVM_INFO @ 1302227580 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/8

UVM_ERROR (spi_device_scoreboard.sv:497) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 2 failures:

Test spi_device_stress_all has 1 failures.

3.spi_device_stress_all.98860333077352182705312800010199734623109832027712934897463559400896338918156
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 38632435924 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xfa14f4, exp: 0x91f734
  UVM_ERROR @ 38632435924 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xfa14f4, exp: 0x91f734
  UVM_INFO @ 40013726063 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/16
  UVM_INFO @ 42723637869 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/16
  UVM_INFO @ 44040416155 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 13/16

Test spi_device_flash_and_tpm has 1 failures.

37.spi_device_flash_and_tpm.18812365050047317353755826434322176114342555601185898469246650272572086203955
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 9125287307 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xfb54, exp: 0x54f470
  UVM_ERROR @ 9125287307 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xfb54, exp: 0x54f470
  UVM_INFO @ 9670438932 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/19
  UVM_INFO @ 10269218932 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/19
  UVM_INFO @ 11289063322 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/19

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed has 2 failures:

Test spi_device_stress_all has 2 failures.

6.spi_device_stress_all.80630249180779070525371203766189777372476183400697858064993036092694232530678
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 18566142138 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed
  UVM_INFO @ 18856745187 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/15
  UVM_INFO @ 21096789658 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/15
  UVM_INFO @ 21227487715 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 10/10
  UVM_INFO @ 23129392919 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/15

27.spi_device_stress_all.106301155888683273323457753309182338872555307202298708195091597142260048119029
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 520758891177 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed
  UVM_INFO @ 520920557775 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/19
  UVM_INFO @ 525377600447 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/19
  UVM_INFO @ 525607833979 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/10
  UVM_INFO @ 528641249885 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/19

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_device_fifo_underflow_overflow has 2 failures.
  - 13.spi_device_fifo_underflow_overflow.87180002481658403854083158057439392555834848176978026569479055298112385314623
    Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/13.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.spi_device_fifo_underflow_overflow.72857416392069060880499564539008825489079497873650660990279144077154450859100
    Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/32.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: * has 2 failures:

Test spi_device_intr has 2 failures.

30.spi_device_intr.109270418937643487653418988630879003226997485476108919353402617549833382511974
Line 276, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_intr/latest/run.log

  UVM_ERROR @ 20193108055 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
  UVM_INFO @ 21691217668 ps: (spi_device_intr_vseq.sv:49) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] finished run 1/2
  UVM_INFO @ 22783883242 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing RxFifoFull
  UVM_INFO @ 26182657621 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]

47.spi_device_intr.38470233066560354026618037361649926276230515722746311951213294749342590254513
Line 304, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_intr/latest/run.log

  UVM_ERROR @ 4847504141 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
  UVM_INFO @ 4859464141 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing RxFifoFull
  UVM_INFO @ 5558764141 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing TxFifoUnderflow

UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_stress_all has 1 failures.

0.spi_device_stress_all.106430144003734253425623485515310614111582609478347256578086732115993416190229
Line 338, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 187552183030 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 120 [0x78]) get_sram_filled_bytes
  UVM_ERROR @ 187552383024 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x7b
  UVM_ERROR @ 187552383024 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x7a
  UVM_ERROR @ 187552383024 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x79
  UVM_ERROR @ 187552383024 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x78

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 6.spi_device_flash_mode.35900152940512919680015203909443346591909751528088675705135520764490744021045
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 3145314206 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 6384468400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_fifo_full has 1 failures.
  - 7.spi_device_fifo_full.97314743262354157192975070367209672706885345532288868371717505041021319910278
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:85575668-7d8a-4818-a711-6b8764fc84c3
```

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

22.spi_device_flash_and_tpm.70003454178064943465914807385903773233763721602796472638540623354462601868993
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 954866867 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd7176a) != exp '{'{other_status:'hc5278, wel:'h0, busy:'h0}}
  UVM_INFO @ 1191369232 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/9
  UVM_INFO @ 1361961847 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/4
  UVM_INFO @ 2575928532 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/9
  UVM_INFO @ 2888542599 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/4

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadNotEmpty mismatch, act (*) != exp * has 1 failures:

Test spi_device_stress_all has 1 failures.

28.spi_device_stress_all.76030628676846485963537416356012580965711309271877783158610609596649013498740
Line 282, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 328722730911 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 328723189248 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 328723522584 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 328723814253 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 328724522592 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0

UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 30.spi_device_flash_mode.91697796563836977910596046487388486736544985620884794419589847991568498908317
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 63479739598 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 63479739598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_intercept has 1 failures.

36.spi_device_intercept.108954044720079958606225287322013093141919584692426798004666964181278730441015
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_intercept/latest/run.log

  UVM_ERROR @ 183440116 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2ae828) != exp '{'{other_status:'h35a657, wel:'h0, busy:'h0}, '{other_status:'h7741f, wel:'h0, busy:'h0}}
  UVM_INFO @ 205924707 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 8, test op = 0x3b
  UVM_INFO @ 217996974 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 9, test op = 0x5
  UVM_INFO @ 261721978 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 10, test op = 0xb
  UVM_INFO @ 408905565 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 11, test op = 0x3

UVM_ERROR (spi_device_pass_base_vseq.sv:641) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

40.spi_device_flash_all.99178078891697889041872408048454979165239056016214274418734476092770745194678
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 9509015153 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 10340978864 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/11
  UVM_INFO @ 11457051117 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/11
  UVM_INFO @ 12118410988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(rdata_o))' has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

41.spi_device_flash_and_tpm_min_idle.60250556188685459687217512379051532460466315452579748183238173390494881908984
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 559774076 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  "../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 193: tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A: started at 559784492ps failed at 559784492ps
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 559784492 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 42.spi_device_flash_mode.65587841291923482475226705550369366158536091409836327583342163652274504516093
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 685802635 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 798332635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.intr_state reset value: * has 1 failures:

Test spi_device_stress_all has 1 failures.

47.spi_device_stress_all.14172770769985161464567662050931496439942565416390146805537867575195862182550
Line 267, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 10184386232 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 10185180025 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 10185424745 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
  UVM_ERROR @ 10185448059 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 10185530531 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0

UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes:: has 1 failures:

Test spi_device_stress_all has 1 failures.

48.spi_device_stress_all.8859246938910794941177612370392860185155763298310795732366856063431046904660
Line 298, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 197026722768 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 552 [0x228]) get_sram_space_bytes::
  UVM_ERROR @ 197028184305 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x22b
  UVM_ERROR @ 197028184305 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x22a
  UVM_ERROR @ 197028184305 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x229
  UVM_ERROR @ 197028184305 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x228