Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
29.17 16.67 0.00 0.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo 0.00 0.00 0.00 0.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo 0.00 0.00 0.00 0.00
tb.dut.u_readcmd.u_readsram.u_fifo 0.00 0.00 0.00 0.00
tb.dut.u_upload.u_arbiter.u_req_fifo 0.00 0.00 0.00 0.00
tb.dut.u_tlul2sram.u_reqfifo 0.00 0.00 0.00 0.00
tb.dut.u_tlul2sram.u_sramreqfifo 0.00 0.00 0.00 0.00
tb.dut.u_tlul2sram.u_rspfifo 0.00 0.00 0.00 0.00
tb.dut.u_sys_sram_arbiter.u_req_fifo 0.00 0.00 0.00 0.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

SCORELINE
0.00 0.00
tb.dut.u_upload.u_arbiter.u_req_fifo

SCORELINE
0.00 0.00
tb.dut.u_sys_sram_arbiter.u_req_fifo

Line No.TotalCoveredPercent
TOTAL2200.00
ALWAYS70400.00
CONT_ASSIGN84100.00
CONT_ASSIGN85100.00
CONT_ASSIGN86100.00
CONT_ASSIGN87100.00
CONT_ASSIGN88100.00
CONT_ASSIGN92100.00
CONT_ASSIGN93100.00
CONT_ASSIGN98100.00
CONT_ASSIGN99100.00
CONT_ASSIGN100100.00
CONT_ASSIGN145100.00
CONT_ASSIGN146100.00
CONT_ASSIGN162100.00
ALWAYS165200.00
CONT_ASSIGN175100.00
CONT_ASSIGN176100.00
CONT_ASSIGN180100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 0 1
71 0 1
72 0 1
73 0 1
==> MISSING_ELSE
84 0 1
85 0 1
86 0 1
87 0 1
88 0 1
92 0 1
93 0 1
98 0 1
99 0 1
100 0 1
145 0 1
146 0 1
162 0 1
165 0 1
166 0 1
==> MISSING_ELSE
175 0 1
176 0 1
180 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo

Line No.TotalCoveredPercent
TOTAL2200.00
ALWAYS70400.00
CONT_ASSIGN84100.00
CONT_ASSIGN85100.00
CONT_ASSIGN86100.00
CONT_ASSIGN87100.00
CONT_ASSIGN88100.00
CONT_ASSIGN92100.00
CONT_ASSIGN93100.00
CONT_ASSIGN98100.00
CONT_ASSIGN99100.00
CONT_ASSIGN100100.00
CONT_ASSIGN145100.00
CONT_ASSIGN146100.00
CONT_ASSIGN154100.00
ALWAYS157200.00
CONT_ASSIGN172100.00
CONT_ASSIGN173100.00
CONT_ASSIGN182100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 0 1
71 0 1
72 0 1
73 0 1
==> MISSING_ELSE
84 0 1
85 0 1
86 0 1
87 0 1
88 0 1
92 0 1
93 0 1
98 0 1
99 0 1
100 0 1
145 0 1
146 0 1
154 0 1
157 0 1
158 0 1
==> MISSING_ELSE
172 0 1
173 0 1
182 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_readcmd.u_readsram.u_fifo

Line No.TotalCoveredPercent
TOTAL2200.00
ALWAYS70400.00
CONT_ASSIGN84100.00
CONT_ASSIGN85100.00
CONT_ASSIGN86100.00
CONT_ASSIGN87100.00
CONT_ASSIGN88100.00
CONT_ASSIGN92100.00
CONT_ASSIGN93100.00
CONT_ASSIGN98100.00
CONT_ASSIGN99100.00
CONT_ASSIGN100100.00
CONT_ASSIGN145100.00
CONT_ASSIGN146100.00
CONT_ASSIGN162100.00
ALWAYS165200.00
CONT_ASSIGN172100.00
CONT_ASSIGN173100.00
CONT_ASSIGN182100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 0 1
71 0 1
72 0 1
73 0 1
==> MISSING_ELSE
84 0 1
85 0 1
86 0 1
87 0 1
88 0 1
92 0 1
93 0 1
98 0 1
99 0 1
100 0 1
145 0 1
146 0 1
162 0 1
165 0 1
166 0 1
==> MISSING_ELSE
172 0 1
173 0 1
182 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_tlul2sram.u_reqfifo

SCORELINE
0.00 0.00
tb.dut.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL2200.00
ALWAYS70400.00
CONT_ASSIGN84100.00
CONT_ASSIGN85100.00
CONT_ASSIGN86100.00
CONT_ASSIGN87100.00
CONT_ASSIGN88100.00
CONT_ASSIGN92100.00
CONT_ASSIGN93100.00
CONT_ASSIGN98100.00
CONT_ASSIGN99100.00
CONT_ASSIGN100100.00
CONT_ASSIGN145100.00
CONT_ASSIGN146100.00
CONT_ASSIGN154100.00
ALWAYS157200.00
CONT_ASSIGN175100.00
CONT_ASSIGN176100.00
CONT_ASSIGN180100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 0 1
71 0 1
72 0 1
73 0 1
==> MISSING_ELSE
84 0 1
85 0 1
86 0 1
87 0 1
88 0 1
92 0 1
93 0 1
98 0 1
99 0 1
100 0 1
145 0 1
146 0 1
154 0 1
157 0 1
158 0 1
==> MISSING_ELSE
175 0 1
176 0 1
180 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL2200.00
ALWAYS70400.00
CONT_ASSIGN84100.00
CONT_ASSIGN85100.00
CONT_ASSIGN86100.00
CONT_ASSIGN87100.00
CONT_ASSIGN88100.00
CONT_ASSIGN92100.00
CONT_ASSIGN93100.00
CONT_ASSIGN98100.00
CONT_ASSIGN99100.00
CONT_ASSIGN100100.00
CONT_ASSIGN145100.00
CONT_ASSIGN146100.00
CONT_ASSIGN154100.00
ALWAYS157200.00
CONT_ASSIGN172100.00
CONT_ASSIGN173100.00
CONT_ASSIGN180100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 0 1
71 0 1
72 0 1
73 0 1
==> MISSING_ELSE
84 0 1
85 0 1
86 0 1
87 0 1
88 0 1
92 0 1
93 0 1
98 0 1
99 0 1
100 0 1
145 0 1
146 0 1
154 0 1
157 0 1
158 0 1
==> MISSING_ELSE
172 0 1
173 0 1
180 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Cond Coverage for Module : prim_fifo_sync ( parameter Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

TotalCoveredPercent
Conditions2600.00
Logical2600.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_upload.u_arbiter.u_req_fifo

SCORECOND
0.00 0.00
tb.dut.u_sys_sram_arbiter.u_req_fifo

TotalCoveredPercent
Conditions2600.00
Logical2600.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo

TotalCoveredPercent
Conditions3200.00
Logical3200.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_tlul2sram.u_rspfifo

TotalCoveredPercent
Conditions3400.00
Logical3400.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_tlul2sram.u_sramreqfifo

TotalCoveredPercent
Conditions2600.00
Logical2600.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_readcmd.u_readsram.u_fifo

TotalCoveredPercent
Conditions3200.00
Logical3200.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_tlul2sram.u_reqfifo

TotalCoveredPercent
Conditions2600.00
Logical2600.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Module : prim_fifo_sync ( parameter Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

SCOREBRANCH
0.00 0.00
tb.dut.u_upload.u_arbiter.u_req_fifo

SCOREBRANCH
0.00 0.00
tb.dut.u_sys_sram_arbiter.u_req_fifo

SCOREBRANCH
0.00 0.00
tb.dut.u_tlul2sram.u_reqfifo

SCOREBRANCH
0.00 0.00
tb.dut.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 10 0 0.00
TERNARY 88 3 0 0.00
TERNARY 180 2 0 0.00
IF 70 3 0 0.00
IF 165 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Branch Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo

SCOREBRANCH
0.00 0.00
tb.dut.u_readcmd.u_readsram.u_fifo

Line No.TotalCoveredPercent
Branches 10 0 0.00
TERNARY 88 3 0 0.00
TERNARY 172 2 0 0.00
IF 70 3 0 0.00
IF 157 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
Branches 12 0 0.00
TERNARY 88 3 0 0.00
TERNARY 172 2 0 0.00
TERNARY 180 2 0 0.00
IF 70 3 0 0.00
IF 157 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11752068 2786278 0 0
DepthKnown_A 11752068 11472744 0 0
RvalidKnown_A 11752068 11472744 0 0
WreadyKnown_A 11752068 11472744 0 0
gen_passthru_fifo.paramCheckPass 1050 1050 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11752068 2786278 0 0
T1 44670 12288 0 0
T2 28170 9923 0 0
T3 4746 88 0 0
T4 15846 2312 0 0
T6 0 576 0 0
T7 404736 37916 0 0
T8 23376 7824 0 0
T9 0 876 0 0
T11 147480 68178 0 0
T12 5982 160 0 0
T14 29670 11650 0 0
T15 29244 11708 0 0
T16 0 5774 0 0
T17 0 1041 0 0
T18 0 12632 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11752068 11472744 0 0
T1 44670 44106 0 0
T2 28170 27630 0 0
T3 4746 4200 0 0
T4 15846 15450 0 0
T7 404736 404142 0 0
T8 23376 22848 0 0
T11 147480 146934 0 0
T12 5982 5556 0 0
T14 29670 29076 0 0
T15 29244 28644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11752068 11472744 0 0
T1 44670 44106 0 0
T2 28170 27630 0 0
T3 4746 4200 0 0
T4 15846 15450 0 0
T7 404736 404142 0 0
T8 23376 22848 0 0
T11 147480 146934 0 0
T12 5982 5556 0 0
T14 29670 29076 0 0
T15 29244 28644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11752068 11472744 0 0
T1 44670 44106 0 0
T2 28170 27630 0 0
T3 4746 4200 0 0
T4 15846 15450 0 0
T7 404736 404142 0 0
T8 23376 22848 0 0
T11 147480 146934 0 0
T12 5982 5556 0 0
T14 29670 29076 0 0
T15 29244 28644 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T11 6 6 0 0
T12 6 6 0 0
T14 6 6 0 0
T15 6 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%