Unified Coverage Report :: Module Instance :: tb.dut.u_sys_sram_arbiter.u_req_fifo

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	0	0.00
ALWAYS	70	4	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	88	1	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	98	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	146	1	0	0.00
CONT_ASSIGN	162	1	0	0.00
ALWAYS	165	2	0	0.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	180	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	0	1
71	0	1
72	0	1
73	0	1
			==> MISSING_ELSE
84	0	1
85	0	1
86	0	1
87	0	1
88	0	1
92	0	1
93	0	1
98	0	1
99	0	1
100	0	1
145	0	1
146	0	1
162	0	1
165	0	1
166	0	1
			==> MISSING_ELSE
175	0	1
176	0	1
180	0	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	0	0.00
Logical	26	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
TERNARY	88	3	0	0.00
TERNARY	180	2	0	0.00
IF	70	3	0	0.00
IF	165	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1958678	711957	0	0
DepthKnown_A	1958678	1912124	0	0
RvalidKnown_A	1958678	1912124	0	0
WreadyKnown_A	1958678	1912124	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	711957	0	0
T1	7445	3072	0	0
T2	4695	3509	0	0
T3	791	22	0	0
T4	2641	401	0	0
T7	67456	9483	0	0
T8	3896	2606	0	0
T11	24580	22677	0	0
T12	997	40	0	0
T14	4945	3883	0	0
T15	4874	3902	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1958678	686842	0	0
DepthKnown_A	1958678	1912124	0	0
RvalidKnown_A	1958678	1912124	0	0
WreadyKnown_A	1958678	1912124	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	686842	0	0
T1	7445	3072	0	0
T2	4695	1761	0	0
T3	791	22	0	0
T4	2641	770	0	0
T7	67456	9475	0	0
T8	3896	1306	0	0
T11	24580	11412	0	0
T12	997	40	0	0
T14	4945	1942	0	0
T15	4874	1952	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1958678	53723	0	0
DepthKnown_A	1958678	1912124	0	0
RvalidKnown_A	1958678	1912124	0	0
WreadyKnown_A	1958678	1912124	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	53723	0	0
T1	7445	3071	0	0
T2	4695	411	0	0
T3	791	0	0	0
T4	2641	169	0	0
T6	0	362	0	0
T7	67456	0	0	0
T8	3896	0	0	0
T9	0	540	0	0
T11	24580	0	0	0
T12	997	0	0	0
T14	4945	3882	0	0
T15	4874	3901	0	0
T16	0	3849	0	0
T17	0	656	0	0
T18	0	3071	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1958678	58144	0	0
DepthKnown_A	1958678	1912124	0	0
RvalidKnown_A	1958678	1912124	0	0
WreadyKnown_A	1958678	1912124	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	58144	0	0
T1	7445	3071	0	0
T2	4695	363	0	0
T3	791	0	0	0
T4	2641	347	0	0
T6	0	214	0	0
T7	67456	0	0	0
T8	3896	0	0	0
T9	0	336	0	0
T11	24580	0	0	0
T12	997	0	0	0
T14	4945	1941	0	0
T15	4874	1951	0	0
T16	0	1925	0	0
T17	0	385	0	0
T18	0	9561	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1958678	646914	0	0
DepthKnown_A	1958678	1912124	0	0
RvalidKnown_A	1958678	1912124	0	0
WreadyKnown_A	1958678	1912124	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	646914	0	0
T1	7445	1	0	0
T2	4695	2481	0	0
T3	791	22	0	0
T4	2641	202	0	0
T7	67456	9483	0	0
T8	3896	2606	0	0
T11	24580	22677	0	0
T12	997	40	0	0
T14	4945	1	0	0
T15	4874	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1958678	628698	0	0
DepthKnown_A	1958678	1912124	0	0
RvalidKnown_A	1958678	1912124	0	0
WreadyKnown_A	1958678	1912124	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	628698	0	0
T1	7445	1	0	0
T2	4695	1398	0	0
T3	791	22	0	0
T4	2641	423	0	0
T7	67456	9475	0	0
T8	3896	1306	0	0
T11	24580	11412	0	0
T12	997	40	0	0
T14	4945	1	0	0
T15	4874	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1958678	1912124	0	0
T1	7445	7351	0	0
T2	4695	4605	0	0
T3	791	700	0	0
T4	2641	2575	0	0
T7	67456	67357	0	0
T8	3896	3808	0	0
T11	24580	24489	0	0
T12	997	926	0	0
T14	4945	4846	0	0
T15	4874	4774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0