Line Coverage for Module :
spid_upload
| Line No. | Total | Covered | Percent |
TOTAL | | 120 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 0 | 0.00 |
CONT_ASSIGN | 137 | 1 | 0 | 0.00 |
CONT_ASSIGN | 143 | 1 | 0 | 0.00 |
CONT_ASSIGN | 194 | 1 | 0 | 0.00 |
CONT_ASSIGN | 206 | 1 | 0 | 0.00 |
CONT_ASSIGN | 213 | 1 | 0 | 0.00 |
CONT_ASSIGN | 234 | 1 | 0 | 0.00 |
CONT_ASSIGN | 241 | 1 | 0 | 0.00 |
CONT_ASSIGN | 242 | 1 | 0 | 0.00 |
CONT_ASSIGN | 244 | 1 | 0 | 0.00 |
CONT_ASSIGN | 246 | 1 | 0 | 0.00 |
CONT_ASSIGN | 247 | 1 | 0 | 0.00 |
CONT_ASSIGN | 248 | 1 | 0 | 0.00 |
ALWAYS | 252 | 6 | 0 | 0.00 |
ALWAYS | 258 | 3 | 0 | 0.00 |
ALWAYS | 264 | 4 | 0 | 0.00 |
ALWAYS | 301 | 6 | 0 | 0.00 |
ALWAYS | 313 | 3 | 0 | 0.00 |
ALWAYS | 319 | 5 | 0 | 0.00 |
CONT_ASSIGN | 327 | 1 | 0 | 0.00 |
ALWAYS | 346 | 10 | 0 | 0.00 |
ALWAYS | 367 | 8 | 0 | 0.00 |
ALWAYS | 390 | 8 | 0 | 0.00 |
ALWAYS | 408 | 6 | 0 | 0.00 |
ALWAYS | 418 | 6 | 0 | 0.00 |
CONT_ASSIGN | 425 | 1 | 0 | 0.00 |
ALWAYS | 428 | 3 | 0 | 0.00 |
ALWAYS | 438 | 26 | 0 | 0.00 |
CONT_ASSIGN | 575 | 1 | 0 | 0.00 |
CONT_ASSIGN | 582 | 1 | 0 | 0.00 |
CONT_ASSIGN | 583 | 1 | 0 | 0.00 |
CONT_ASSIGN | 584 | 1 | 0 | 0.00 |
CONT_ASSIGN | 585 | 1 | 0 | 0.00 |
CONT_ASSIGN | 635 | 1 | 0 | 0.00 |
CONT_ASSIGN | 642 | 1 | 0 | 0.00 |
CONT_ASSIGN | 643 | 1 | 0 | 0.00 |
CONT_ASSIGN | 644 | 1 | 0 | 0.00 |
CONT_ASSIGN | 645 | 1 | 0 | 0.00 |
CONT_ASSIGN | 711 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
134 |
0 |
1 |
137 |
0 |
1 |
143 |
0 |
1 |
194 |
0 |
1 |
206 |
0 |
1 |
213 |
0 |
1 |
234 |
0 |
1 |
241 |
0 |
1 |
242 |
0 |
1 |
244 |
0 |
1 |
246 |
0 |
1 |
247 |
0 |
1 |
248 |
0 |
1 |
252 |
0 |
2 |
253 |
0 |
2 |
254 |
0 |
2 |
|
|
|
==> MISSING_ELSE |
258 |
0 |
1 |
259 |
0 |
1 |
260 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
264 |
0 |
1 |
265 |
0 |
1 |
266 |
0 |
1 |
267 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
301 |
0 |
2 |
304 |
0 |
2 |
305 |
0 |
2 |
|
|
|
==> MISSING_ELSE |
313 |
0 |
2 |
314 |
0 |
1 |
319 |
0 |
2 |
320 |
0 |
1 |
321 |
0 |
1 |
323 |
0 |
1 |
327 |
0 |
1 |
346 |
0 |
1 |
347 |
0 |
1 |
348 |
0 |
1 |
349 |
0 |
1 |
350 |
0 |
1 |
351 |
0 |
1 |
352 |
0 |
1 |
353 |
0 |
1 |
355 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
357 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
367 |
0 |
2 |
368 |
0 |
2 |
369 |
0 |
1 |
370 |
0 |
1 |
371 |
0 |
1 |
372 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
390 |
0 |
2 |
391 |
0 |
2 |
392 |
0 |
1 |
395 |
0 |
1 |
396 |
0 |
1 |
399 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
408 |
0 |
2 |
409 |
0 |
2 |
410 |
0 |
1 |
411 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
418 |
0 |
2 |
419 |
0 |
2 |
420 |
0 |
1 |
421 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
425 |
0 |
1 |
428 |
0 |
1 |
429 |
0 |
1 |
431 |
0 |
1 |
438 |
0 |
1 |
440 |
0 |
1 |
441 |
0 |
1 |
442 |
0 |
1 |
444 |
0 |
1 |
445 |
0 |
1 |
447 |
0 |
1 |
449 |
0 |
1 |
450 |
0 |
1 |
452 |
0 |
1 |
454 |
0 |
1 |
455 |
0 |
1 |
456 |
0 |
1 |
459 |
0 |
1 |
461 |
0 |
1 |
465 |
0 |
1 |
469 |
0 |
1 |
471 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
475 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
481 |
0 |
1 |
483 |
0 |
1 |
484 |
0 |
1 |
486 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
492 |
0 |
1 |
493 |
0 |
1 |
494 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
575 |
0 |
1 |
582 |
0 |
1 |
583 |
0 |
1 |
584 |
0 |
1 |
585 |
0 |
1 |
635 |
0 |
1 |
642 |
0 |
1 |
643 |
0 |
1 |
644 |
0 |
1 |
645 |
0 |
1 |
711 |
0 |
1 |
Cond Coverage for Module :
spid_upload
| Total | Covered | Percent |
Conditions | 39 | 0 | 0.00 |
Logical | 39 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 242
EXPRESSION (cmdinfo_addr_mode != AddrDisabled)
-----------------1-----------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 244
EXPRESSION (cmdinfo_addr_mode == Addr4B)
--------------1--------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 253
EXPRESSION (cmdinfo_addr_4b_en ? 5'd31 : 5'd23)
---------1--------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 266
EXPRESSION (s2p_valid_i && addr_shift)
-----1----- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 304
EXPRESSION (cmdfifo_wvalid && cmdfifo_wready)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 320
EXPRESSION (sys_csb_deasserted_pulse_i && csb_cmdfifo_set)
-------------1------------ -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 353
EXPRESSION (payloadptr == 8'((PayloadByte - 1)))
------------------1------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 369
EXPRESSION (sys_csb_deasserted_pulse_i && payload_max)
-------------1------------ -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 371
EXPRESSION (sys_csb_deasserted_pulse_i && ((!payload_max)))
-------------1------------ --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 392
EXPRESSION (sys_csb_deasserted_pulse_i && payload_max)
-------------1------------ -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 396
EXPRESSION (sys_csb_deasserted_pulse_i && ((!payload_max)))
-------------1------------ --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 410
EXPRESSION (payloadptr_inc && payload_max)
-------1------ -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 454
EXPRESSION (s2p_valid_i && (cmd_only_sel_dp_i == DpUpload))
-----1----- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 454
SUB-EXPRESSION (cmd_only_sel_dp_i == DpUpload)
---------------1---------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 483
EXPRESSION (addrcnt == '0)
-------1-------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
FSM Coverage for Module :
spid_upload
Summary for FSM :: st_q
| Total | Covered | Percent | |
States |
3 |
0 |
0.00 |
(Not included in score) |
Transitions |
3 |
0 |
0.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
states | Line No. | Covered | Tests |
StAddress |
456 |
Not Covered |
|
StIdle |
453 |
Not Covered |
|
StPayload |
461 |
Not Covered |
|
transitions | Line No. | Covered | Tests |
StAddress->StPayload |
484 |
Not Covered |
|
StIdle->StAddress |
456 |
Not Covered |
|
StIdle->StPayload |
461 |
Not Covered |
|
Branch Coverage for Module :
spid_upload
| Line No. | Total | Covered | Percent |
Branches |
|
54 |
0 |
0.00 |
IF |
252 |
5 |
0 |
0.00 |
IF |
259 |
2 |
0 |
0.00 |
IF |
264 |
3 |
0 |
0.00 |
IF |
301 |
4 |
0 |
0.00 |
IF |
313 |
2 |
0 |
0.00 |
IF |
319 |
3 |
0 |
0.00 |
IF |
346 |
5 |
0 |
0.00 |
IF |
367 |
5 |
0 |
0.00 |
IF |
390 |
5 |
0 |
0.00 |
IF |
408 |
4 |
0 |
0.00 |
IF |
418 |
4 |
0 |
0.00 |
IF |
428 |
2 |
0 |
0.00 |
CASE |
452 |
10 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 252 if ((!rst_ni))
-2-: 253 if (addr_update)
-3-: 253 (cmdinfo_addr_4b_en) ?
-4-: 254 if (addr_shift)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Not Covered |
|
0 |
1 |
1 |
- |
Not Covered |
|
0 |
1 |
0 |
- |
Not Covered |
|
0 |
0 |
- |
1 |
Not Covered |
|
0 |
0 |
- |
0 |
Not Covered |
|
LineNo. Expression
-1-: 259 if (addr_shift)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 264 if ((!rst_ni))
-2-: 266 if ((s2p_valid_i && addr_shift))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 301 if ((!sys_rst_ni))
-2-: 304 if ((cmdfifo_wvalid && cmdfifo_wready))
-3-: 305 if (sck_csb_asserted_pulse_i)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 313 if ((!sys_rst_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 319 if ((!sys_rst_ni))
-2-: 320 if ((sys_csb_deasserted_pulse_i && csb_cmdfifo_set))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 346 if ((!sys_rst_ni))
-2-: 349 if (payloadptr_clr)
-3-: 352 if (payloadptr_inc)
-4-: 353 if ((payloadptr == 8'((PayloadByte - 1))))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Not Covered |
|
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
1 |
1 |
Not Covered |
|
0 |
0 |
1 |
0 |
Not Covered |
|
0 |
0 |
0 |
- |
Not Covered |
|
LineNo. Expression
-1-: 367 if ((!sys_rst_ni))
-2-: 368 if (sys_payloadptr_clr_posedge)
-3-: 369 if ((sys_csb_deasserted_pulse_i && payload_max))
-4-: 371 if ((sys_csb_deasserted_pulse_i && (!payload_max)))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Not Covered |
|
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 390 if ((!sys_rst_ni))
-2-: 391 if (sys_payloadptr_clr_posedge)
-3-: 392 if ((sys_csb_deasserted_pulse_i && payload_max))
-4-: 396 if ((sys_csb_deasserted_pulse_i && (!payload_max)))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Not Covered |
|
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 408 if ((!sys_rst_ni))
-2-: 409 if (payloadptr_clr)
-3-: 410 if ((payloadptr_inc && payload_max))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 418 if ((!sys_rst_ni))
-2-: 419 if (sys_payloadptr_clr_posedge)
-3-: 420 if (sys_csb_deasserted_pulse_i)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Not Covered |
|
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 428 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 452 case (st_q)
-2-: 454 if ((s2p_valid_i && (cmd_only_sel_dp_i == DpUpload)))
-3-: 455 if (cmdinfo_addr_en)
-4-: 469 if (cmd_only_info_i.busy)
-5-: 483 if ((addrcnt == '0))
-6-: 492 if (s2p_valid_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
StIdle |
1 |
1 |
- |
- |
- |
Not Covered |
|
StIdle |
1 |
0 |
- |
- |
- |
Not Covered |
|
StIdle |
1 |
- |
1 |
- |
- |
Not Covered |
|
StIdle |
1 |
- |
0 |
- |
- |
Not Covered |
|
StIdle |
0 |
- |
- |
- |
- |
Not Covered |
|
StAddress |
- |
- |
- |
1 |
- |
Not Covered |
|
StAddress |
- |
- |
- |
0 |
- |
Not Covered |
|
StPayload |
- |
- |
- |
- |
1 |
Not Covered |
|
StPayload |
- |
- |
- |
- |
0 |
Not Covered |
|
default |
- |
- |
- |
- |
- |
Not Covered |
|