Unified Coverage Report :: Module :: prim_sram_arbiter

Module : prim_sram_arbiter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_fwmode.u_fwmode_arb	0.00	0.00	0.00
tb.dut.u_upload.u_arbiter	0.00	0.00	0.00
tb.dut.u_sys_sram_arbiter	0.00	0.00	0.00

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00					u_fwmode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	0.00	0.00	0.00			0.00
u_req_fifo	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_upload.u_arbiter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	0.00	0.00	0.00			0.00
u_req_fifo	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_sys_sram_arbiter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
19.21	0.00	0.00	76.82		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	0.00	0.00	0.00			0.00
u_req_fifo	0.00	0.00	0.00			0.00

Line Coverage for Module : prim_sram_arbiter ( parameter N=2,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=0 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_fwmode.u_fwmode_arb

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	67	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	69	1	0	0.00
CONT_ASSIGN	70	0	0
ALWAYS	76	4	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	2
67	0	1
68	0	1
69	0	1
70		unreachable
76	0	1
77	0	1
78	0	1
80	0	1
125	0	1
147	0	1
150	0	2
151	0	2

---

Line Coverage for Module : prim_sram_arbiter ( parameter N=3,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_upload.u_arbiter

SCORE	LINE
0.00	0.00

tb.dut.u_sys_sram_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	67	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	69	1	0	0.00
CONT_ASSIGN	70	1	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	3
67	0	1
68	0	1
69	0	1
70	0	1
125	0	1
147	0	1
150	0	3
151	0	3

---

Cond Coverage for Module : prim_sram_arbiter

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	67	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	69	1	0	0.00
CONT_ASSIGN	70	0	0
ALWAYS	76	4	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	2
67	0	1
68	0	1
69	0	1
70		unreachable
76	0	1
77	0	1
78	0	1
80	0	1
125	0	1
147	0	1
150	0	2
151	0	2

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

Line Coverage for Instance : tb.dut.u_upload.u_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	67	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	69	1	0	0.00
CONT_ASSIGN	70	1	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	3
67	0	1
68	0	1
69	0	1
70	0	1
125	0	1
147	0	1
150	0	3
151	0	3

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	67	1	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	69	1	0	0.00
CONT_ASSIGN	70	1	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	151	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	0	3
67	0	1
68	0	1
69	0	1
70	0	1
125	0	1
147	0	1
150	0	3
151	0	3

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered