Unified Coverage Report :: Module

Module : spi_fwmode

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwmode.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_fwmode	95.83	91.67	100.00

Module Instance : tb.dut.u_fwmode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.94	99.27	89.44		100.00	97.11	88.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_fwmode_arb	88.22	100.00	70.73			96.43	85.71
u_rx_fifo	99.17	100.00	96.67			100.00	100.00
u_rxf_ctrl	98.06	100.00	94.87		100.00	97.37
u_tx_fifo	99.17	100.00	96.67			100.00	100.00
u_txf_ctrl	94.88	97.56	89.66		100.00	92.31

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_fwmode

	Line No.	Total	Covered	Percent
TOTAL		12	11	91.67
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	269	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwmode.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwmode.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
124	1	1
125	1	1
128	1	1
129	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
269	0	1

Cond Coverage for Module : spi_fwmode

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (spi_mode_i == FwMode)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       124
 EXPRESSION (rx_data_valid_i && active)
             -------1-------    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T7,T12,T1
1	1	Covered	T2,T10,T11

 LINE       142
 EXPRESSION (rxf_wvalid & ((~rxf_wready)))
             -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T33
1	0	Covered	T2,T10,T11
1	1	Covered	T10,T15,T33

 LINE       143
 EXPRESSION (txf_rready & ((~txf_rvalid)))
             -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T10,T11
1	1	Covered	T33,T9,T49