Unified Coverage Report :: Module :: spi_fwm_txf_ctrl

Module : spi_fwm_txf_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	97.56	89.66		100.00	92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_fwmode.u_txf_ctrl	94.88	97.56	89.66		100.00	92.31

---

Module Instance : tb.dut.u_fwmode.u_txf_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	97.56	89.66		100.00	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	97.56	89.66		100.00	92.31

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	91.67	100.00					u_fwmode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_fwm_txf_ctrl

	Line No.	Total	Covered	Percent
TOTAL		82	80	97.56
ALWAYS	80	3	3	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	93	38	37	97.37
ALWAYS	162	6	6	100.00
ALWAYS	174	4	4	100.00
ALWAYS	182	11	10	90.91
ALWAYS	204	3	3	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
ALWAYS	223	3	3	100.00
ALWAYS	228	4	4	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	235	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	2	2
81	1	1
84	1	1
86	1	1
88	1	1
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
99	1	1
100	1	1
101	1	1
103	1	1
104	1	1
105	1	1
106	1	1
108	1	1
113	1	1
114	1	1
115	1	1
116	1	1
118	1	1
119	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
130	0	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
146	1	1
151	1	1
152	1	1
162	1	1
163	1	1
164	1	1
166	1	1
167	1	1
169	1	1
			MISSING_ELSE
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
191	1	1
192	1	1
193	1	1
197	0	1
			MISSING_ELSE
204	1	1
206	1	1
208	1	1
213	1	1
218	1	1
223	2	2
224	1	1
228	2	2
229	2	2
			MISSING_ELSE
232	1	1
235	1	1
236	1	1
237	2	2
			MISSING_ELSE

---

Cond Coverage for Module : spi_fwm_txf_ctrl

	Total	Covered	Percent
Conditions	29	26	89.66
Logical	29	26	89.66
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (spi_mode_i == FwMode)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       86
 EXPRESSION (rptr == wptr_q)
            --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       104
 EXPRESSION (active && ((!sramf_empty)) && fifo_ready)
             ---1--    --------2-------    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T72,T73,T74
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T3,T75,T76
1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (fifo_ready && ((!cnt_eq_end)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T10

 LINE       185
 EXPRESSION (pos == '0)
            -----1-----

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T10

 LINE       187
 EXPRESSION (rptr[(PtrW - 2):SDW] != sramf_limit)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T2,T11,T14
1	Covered	T2,T3,T10

 LINE       204
 EXPRESSION (wptr[(PtrW - 1)] == rptr[(PtrW - 1)])
            -------------------1------------------

-1-	Status	Tests
0	Covered	T2,T11,T14
1	Covered	T4,T5,T6

 LINE       213
 EXPRESSION ((wptr_q[(PtrW - 1):SDW] == rptr[(PtrW - 1):SDW]) ? (wptr_q[(SDW - 1):0] == pos) : (pos == '0))
             ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (wptr_q[(PtrW - 1):SDW] == rptr[(PtrW - 1):SDW])
                ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (wptr_q[(SDW - 1):0] == pos)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (pos == '0)
                -----1-----

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       232
 EXPRESSION (txf_sel ? sram_rdata_q : sram_rdata)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       237
 EXPRESSION (pos == i[(SDW - 1):0])
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Module : spi_fwm_txf_ctrl

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StIdle	108	Covered	T4,T5,T6
StLatch	114	Covered	T2,T3,T10
StPush	125	Covered	T2,T3,T10
StRead	105	Covered	T2,T3,T10
StUpdate	136	Covered	T2,T3,T10

transitions	Line No.	Covered	Tests
StIdle->StRead	105	Covered	T2,T3,T10
StLatch->StPush	125	Covered	T2,T3,T10
StPush->StUpdate	136	Covered	T2,T3,T10
StRead->StLatch	114	Covered	T2,T3,T10
StUpdate->StIdle	151	Covered	T2,T3,T10

---

Branch Coverage for Module : spi_fwm_txf_ctrl

	Line No.	Total	Covered	Percent
Branches		39	36	92.31
TERNARY	213	2	2	100.00
TERNARY	232	2	2	100.00
IF	80	2	2	100.00
CASE	101	12	10	83.33
IF	162	4	4	100.00
IF	174	3	3	100.00
IF	182	5	4	80.00
IF	204	2	2	100.00
IF	223	2	2	100.00
IF	228	3	3	100.00
IF	237	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((wptr_q[(PtrW - 1):SDW] == rptr[(PtrW - 1):SDW])) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T2,T3,T10

	LineNo.	Expression
-1-:	232	(txf_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T12,T1

	LineNo.	Expression
-1-:	101	case (st)
-2-:	104	if (((active && (!sramf_empty)) && fifo_ready))
-3-:	113	if (sram_gnt)
-4-:	124	if (sram_rvalid)
-5-:	135	if (abort)
-6-:	137	if ((!fifo_ready))
-7-:	139	if ((fifo_ready && (!cnt_eq_end)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T2,T3,T10
StIdle	0	-	-	-	-	-	Covered	T4,T5,T6
StRead	-	1	-	-	-	-	Covered	T2,T3,T10
StRead	-	0	-	-	-	-	Covered	T9,T48,T49
StLatch	-	-	1	-	-	-	Covered	T2,T3,T10
StLatch	-	-	0	-	-	-	Not Covered
StPush	-	-	-	1	-	-	Covered	T3,T75,T76
StPush	-	-	-	0	1	-	Covered	T2,T3,T10
StPush	-	-	-	0	0	1	Covered	T2,T3,T10
StPush	-	-	-	0	0	0	Covered	T2,T3,T10
StUpdate	-	-	-	-	-	-	Covered	T2,T3,T10
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	162	if ((!rst_ni))
-2-:	164	if (cnt_rst)
-3-:	167	if (cnt_incr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T7,T12,T1

	LineNo.	Expression
-1-:	174	if ((!rst_ni))
-2-:	176	if (latch_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T7,T12,T1
0	0	Covered	T2,T3,T10

	LineNo.	Expression
-1-:	182	if ((!rst_ni))
-2-:	184	if (update_rptr)
-3-:	185	if ((pos == '0))
-4-:	187	if ((rptr[(PtrW - 2):SDW] != sramf_limit))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	1	1	Covered	T2,T3,T10
0	1	1	0	Covered	T2,T11,T14
0	1	0	-	Not Covered
0	0	-	-	Covered	T7,T12,T1

	LineNo.	Expression
-1-:	204	if ((wptr[(PtrW - 1)] == rptr[(PtrW - 1)]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T2,T11,T14

	LineNo.	Expression
-1-:	223	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T12,T1

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	229	if (sram_rvalid)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T3,T10
0	0	Covered	T7,T12,T1

	LineNo.	Expression
-1-:	237	if ((pos == i[(SDW - 1):0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6