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Module Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.85 100.00 65.38 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.96 100.00 65.38 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_fwmode_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00


Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.25 100.00 75.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.33 95.00 75.00 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.15 98.25 100.00 100.00 87.50 100.00 u_readsram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.15 98.25 100.00 100.00 87.50 100.00 u_readsram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00


Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.30 90.91 42.31 60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.72 85.00 42.31 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 100.00 33.33 u_arbiter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.89 77.78 50.00


Module Instance : tb.dut.u_tlul2sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.77 100.00 73.08 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.85 95.00 73.08 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.29 96.97 80.53 91.67 100.00 u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_tlul2sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.81 100.00 69.23 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.89 95.00 69.23 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.29 96.97 80.53 91.67 100.00 u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_tlul2sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.03 100.00 76.47 91.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.12 95.00 76.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.29 96.97 80.53 91.67 100.00 u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00

Go back
Module Instances:
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo
tb.dut.u_readcmd.u_readsram.u_sram_fifo
tb.dut.u_readcmd.u_readsram.u_fifo
tb.dut.u_upload.u_arbiter.u_req_fifo
tb.dut.u_tlul2sram.u_reqfifo
tb.dut.u_tlul2sram.u_sramreqfifo
tb.dut.u_tlul2sram.u_rspfifo
Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo
TotalCoveredPercent
Conditions261765.38
Logical261765.38
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT2,T10,T11
1CoveredT4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT2,T10,T11
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT7,T12,T1
101Not Covered
110Not Covered
111CoveredT2,T3,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT2,T3,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT7,T12,T1

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T12,T1
10Not Covered
11CoveredT2,T3,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T10
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T5,T6
0 0 Covered T2,T10,T11


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T2,T3,T10


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T7,T12,T1
0 0 Covered T7,T12,T1


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T10
0 Covered T4,T6,T7


Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1682880266 4502916 0 0
DepthKnown_A 1682880266 1645751674 0 0
RvalidKnown_A 1682880266 1645751674 0 0
WreadyKnown_A 1682880266 1645751674 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1682880266 4502916 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1682880266 4502916 0 0
T2 348480 11802 0 0
T3 1115 2 0 0
T8 836914 0 0 0
T10 1631 12 0 0
T11 324980 3165 0 0
T13 65808 0 0 0
T14 175518 17659 0 0
T15 1215 12 0 0
T31 268674 0 0 0
T32 0 15968 0 0
T33 0 9645 0 0
T34 0 12482 0 0
T36 113230 0 0 0
T46 0 2 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1682880266 1645751674 0 0
T1 884449 834882 0 0
T2 348480 348480 0 0
T3 1115 1115 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 1631 1631 0 0
T11 324980 324980 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 175518 175518 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1682880266 1645751674 0 0
T1 884449 834882 0 0
T2 348480 348480 0 0
T3 1115 1115 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 1631 1631 0 0
T11 324980 324980 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 175518 175518 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1682880266 1645751674 0 0
T1 884449 834882 0 0
T2 348480 348480 0 0
T3 1115 1115 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 1631 1631 0 0
T11 324980 324980 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 175518 175518 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1682880266 4502916 0 0
T2 348480 11802 0 0
T3 1115 2 0 0
T8 836914 0 0 0
T10 1631 12 0 0
T11 324980 3165 0 0
T13 65808 0 0 0
T14 175518 17659 0 0
T15 1215 12 0 0
T31 268674 0 0 0
T32 0 15968 0 0
T33 0 9645 0 0
T34 0 12482 0 0
T36 113230 0 0 0
T46 0 2 0 0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
182 1 1


Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
TotalCoveredPercent
Conditions322475.00
Logical322475.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT7,T12,T1
101Not Covered
110Not Covered
111CoveredT7,T12,T1

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T12,T1
110Not Covered
111CoveredT7,T12,T1

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T12,T1
10CoveredT4,T5,T6
11CoveredT7,T12,T1

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T12,T1
10Not Covered
11CoveredT7,T12,T1

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT7,T12,T1

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT7,T12,T1
10CoveredT7,T12,T1
11CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 172 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T12,T1
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T7,T12,T1
0 Covered T4,T5,T6


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T7,T12,T1
0 0 Covered T7,T12,T1


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T7,T12,T1
0 Covered T4,T6,T7


Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 394100318 24777377 0 0
DepthKnown_A 394100318 342026219 0 0
RvalidKnown_A 394100318 342026219 0 0
WreadyKnown_A 394100318 342026219 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 394100318 24777377 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 24777377 0 0
T1 884449 118183 0 0
T2 377666 0 0 0
T3 1 0 0 0
T7 21468 20281 0 0
T8 836914 106772 0 0
T9 0 195251 0 0
T10 385 0 0 0
T11 101282 0 0 0
T12 52863 35608 0 0
T13 65808 35536 0 0
T14 565090 0 0 0
T16 0 56 0 0
T17 0 18004 0 0
T38 0 8880 0 0
T41 0 32754 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 24777377 0 0
T1 884449 118183 0 0
T2 377666 0 0 0
T3 1 0 0 0
T7 21468 20281 0 0
T8 836914 106772 0 0
T9 0 195251 0 0
T10 385 0 0 0
T11 101282 0 0 0
T12 52863 35608 0 0
T13 65808 35536 0 0
T14 565090 0 0 0
T16 0 56 0 0
T17 0 18004 0 0
T38 0 8880 0 0
T41 0 32754 0 0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
172 1 1
173 1 1
182 1 1


Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
TotalCoveredPercent
Conditions322887.50
Logical322887.50
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT7,T12,T1
1CoveredT4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT7,T12,T1
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT7,T12,T1
101CoveredT7,T12,T1
110Not Covered
111CoveredT7,T12,T1

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T12,T1
110Not Covered
111CoveredT7,T12,T1

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T12,T1
10CoveredT4,T5,T6
11CoveredT7,T12,T1

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T12,T1
10Not Covered
11CoveredT7,T12,T1

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT7,T12,T1
10CoveredT4,T5,T6
11CoveredT7,T12,T1

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT7,T12,T1
10CoveredT7,T12,T1
11CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 172 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T12,T1
0 1 Covered T4,T5,T6
0 0 Covered T7,T12,T1


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T7,T12,T1
0 Covered T4,T5,T6


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T7,T12,T1
0 0 Covered T7,T12,T1


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T7,T12,T1
0 Covered T4,T6,T7


Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 394100318 26061483 0 0
DepthKnown_A 394100318 342026219 0 0
RvalidKnown_A 394100318 342026219 0 0
WreadyKnown_A 394100318 342026219 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 394100318 26061483 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 26061483 0 0
T1 884449 125071 0 0
T2 377666 0 0 0
T3 1 0 0 0
T7 21468 21118 0 0
T8 836914 111131 0 0
T9 0 205790 0 0
T10 385 0 0 0
T11 101282 0 0 0
T12 52863 37696 0 0
T13 65808 38808 0 0
T14 565090 0 0 0
T16 0 56 0 0
T17 0 19184 0 0
T38 0 9832 0 0
T41 0 34185 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 26061483 0 0
T1 884449 125071 0 0
T2 377666 0 0 0
T3 1 0 0 0
T7 21468 21118 0 0
T8 836914 111131 0 0
T9 0 205790 0 0
T10 385 0 0 0
T11 101282 0 0 0
T12 52863 37696 0 0
T13 65808 38808 0 0
T14 565090 0 0 0
T16 0 56 0 0
T17 0 19184 0 0
T38 0 9832 0 0
T41 0 34185 0 0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS1652150.00
CONT_ASSIGN175100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 0 1
MISSING_ELSE
175 0 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
TotalCoveredPercent
Conditions261142.31
Logical261142.31
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT7,T12,T1
101Not Covered
110Not Covered
111Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT7,T12,T1

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T12,T1
10Not Covered
11Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
Branches 10 6 60.00
TERNARY 88 3 1 33.33
TERNARY 180 2 1 50.00
IF 70 3 3 100.00
IF 165 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Not Covered


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T7,T12,T1
0 0 Covered T7,T12,T1


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T6,T7


Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 394100318 0 0 0
DepthKnown_A 394100318 342026219 0 0
RvalidKnown_A 394100318 342026219 0 0
WreadyKnown_A 394100318 342026219 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 394100318 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 342026219 0 0
T1 884449 834882 0 0
T2 377666 377664 0 0
T3 1 0 0 0
T7 21468 21422 0 0
T8 836914 818621 0 0
T10 385 384 0 0
T11 101282 101280 0 0
T12 52863 52744 0 0
T13 65808 65390 0 0
T14 565090 565088 0 0
T15 0 384 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 394100318 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Not Covered
110Not Covered
111CoveredT7,T12,T1

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T12,T3
110Not Covered
111CoveredT7,T12,T1

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T12,T1
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT7,T12,T1

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT7,T12,T1

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT7,T12,T1
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T12,T1
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T7,T12,T1


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T7,T12,T1
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2049979927 23047058 0 0
DepthKnown_A 2049979927 2049845846 0 0
RvalidKnown_A 2049979927 2049845846 0 0
WreadyKnown_A 2049979927 2049845846 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2049979927 23047058 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 23047058 0 0
T1 270361 14665 0 0
T2 348489 23604 0 0
T3 1222 4 0 0
T7 15995 1024 0 0
T8 517454 20908 0 0
T10 1745 12 0 0
T11 325051 6330 0 0
T12 56701 1025 0 0
T13 396572 1024 0 0
T14 0 35318 0 0
T37 1428 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 23047058 0 0
T1 270361 14665 0 0
T2 348489 23604 0 0
T3 1222 4 0 0
T7 15995 1024 0 0
T8 517454 20908 0 0
T10 1745 12 0 0
T11 325051 6330 0 0
T12 56701 1025 0 0
T13 396572 1024 0 0
T14 0 35318 0 0
T37 1428 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo
TotalCoveredPercent
Conditions261869.23
Logical261869.23
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T8

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Not Covered
110Not Covered
111CoveredT1,T2,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T2,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T8
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT1,T2,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T8

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T8
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T8
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T8


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T8
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2049979927 4819250 0 0
DepthKnown_A 2049979927 2049845846 0 0
RvalidKnown_A 2049979927 2049845846 0 0
WreadyKnown_A 2049979927 2049845846 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2049979927 4819250 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 4819250 0 0
T1 270361 329 0 0
T2 348489 11802 0 0
T3 1222 0 0 0
T8 517454 428 0 0
T10 1745 0 0 0
T11 325051 3165 0 0
T13 396572 0 0 0
T14 175528 17659 0 0
T31 105784 0 0 0
T32 0 15968 0 0
T33 0 11233 0 0
T34 0 12482 0 0
T35 0 8760 0 0
T37 1428 0 0 0
T45 0 7 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 4819250 0 0
T1 270361 329 0 0
T2 348489 11802 0 0
T3 1222 0 0 0
T8 517454 428 0 0
T10 1745 0 0 0
T11 325051 3165 0 0
T13 396572 0 0 0
T14 175528 17659 0 0
T31 105784 0 0 0
T32 0 15968 0 0
T33 0 11233 0 0
T34 0 12482 0 0
T35 0 8760 0 0
T37 1428 0 0 0
T45 0 7 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo
TotalCoveredPercent
Conditions342676.47
Logical342676.47
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT34,T58,T60

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Not Covered
110Not Covered
111CoveredT1,T2,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT32,T34,T57
110Not Covered
111CoveredT1,T2,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT34,T58,T60
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT1,T2,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT34,T58,T60

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T8

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT1,T2,T8

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT34,T58,T60
10CoveredT1,T2,T8
11CoveredT4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T8
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 12 11 91.67
TERNARY 88 3 2 66.67
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T34,T58,T60
0 1 Covered T4,T5,T6
0 0 Not Covered


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T8
0 Covered T4,T5,T6


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T8


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T8
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2049979927 9920659 0 0
DepthKnown_A 2049979927 2049845846 0 0
RvalidKnown_A 2049979927 2049845846 0 0
WreadyKnown_A 2049979927 2049845846 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2049979927 9920659 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 9920659 0 0
T1 270361 329 0 0
T2 348489 11802 0 0
T3 1222 0 0 0
T8 517454 428 0 0
T10 1745 0 0 0
T11 325051 3165 0 0
T13 396572 0 0 0
T14 175528 17659 0 0
T31 105784 0 0 0
T32 0 15968 0 0
T33 0 11233 0 0
T34 0 60054 0 0
T35 0 8760 0 0
T37 1428 0 0 0
T45 0 7 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 2049845846 0 0
T1 270361 270354 0 0
T2 348489 348481 0 0
T3 1222 1127 0 0
T4 3172 3108 0 0
T5 1149 1078 0 0
T6 15012 14961 0 0
T7 15995 15915 0 0
T8 517454 517446 0 0
T10 1745 1646 0 0
T12 56701 56638 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2049979927 9920659 0 0
T1 270361 329 0 0
T2 348489 11802 0 0
T3 1222 0 0 0
T8 517454 428 0 0
T10 1745 0 0 0
T11 325051 3165 0 0
T13 396572 0 0 0
T14 175528 17659 0 0
T31 105784 0 0 0
T32 0 15968 0 0
T33 0 11233 0 0
T34 0 60054 0 0
T35 0 8760 0 0
T37 1428 0 0 0
T45 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%