Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.29	96.97	80.53			91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul2sram	92.29	96.97	80.53			91.67	100.00

---

Module Instance : tb.dut.u_tlul2sram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.29	96.97	80.53			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.21	88.70	77.78			86.36	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	91.88	100.00	80.00			87.50	100.00
u_reqfifo	87.85	95.00	73.08			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	89.12	95.00	76.47			85.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	86.89	95.00	69.23			83.33	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		66	64	96.97
ALWAYS	93	3	3	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	7	87.50
ALWAYS	249	6	6	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	433	3	3	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96		unreachable
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	1	1
239	1	1
242	1	1
249	1	1
251	1	1
252	1	1
253	1	1
255	1	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
381	1	1
382	1	1
383	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
433	1	1
434	1	1
435	1	1
439	1	1
442	1	1
447	1	1
452	0	1

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	113	91	80.53
Logical	113	91	80.53
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T6,T7,T3
1	0	Covered	T4,T5,T6

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T7,T12,T1
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T4,T5,T6
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T12,T1
1	1	Covered	T7,T12,T1

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T12,T3
1	1	Covered	T7,T12,T1

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T7,T12,T1

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T12,T1
1	Covered	T1,T2,T8

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T12,T1
1	Covered	T1,T2,T8

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Not Covered
1	0	Covered	T42,T43,T44

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T8

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T1,T2,T8

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T1

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T8
1	1	Covered	T7,T12,T1

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T1

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T1

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T12,T1
1	1	Covered	T42,T43,T44

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T12,T1
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T1
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T12,T1

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T12,T1
1	1	0	Not Covered
1	1	1	Covered	T7,T12,T1

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T8
1	1	Covered	T7,T12,T1

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T1

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T7,T12,T1

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T8
1	1	Covered	T7,T12,T1

 LINE       383
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T12,T1
1	1	Covered	T7,T12,T1

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T12,T1
1	1	Covered	T1,T2,T8

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	107	2	2	100.00
TERNARY	291	2	2	100.00
TERNARY	297	3	2	66.67
TERNARY	324	2	2	100.00
TERNARY	447	2	2	100.00
IF	93	2	2	100.00
IF	231	4	3	75.00
IF	251	3	3	100.00
IF	357	2	2	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Unreachable
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Covered	T1,T2,T8
1	0	0	Covered	T7,T12,T1
0	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T8
1	0	Covered	T7,T12,T1
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T1
0	Covered	T4,T5,T6

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	2049979927	2049845846	0	0
DataIntgOptions_A	1601	1601	0	0
ReqOutKnown_A	2049979927	2049845846	0	0
SramDwHasByteGranularity_A	1601	1601	0	0
SramDwIsMultipleOfTlulWidth_A	1601	1601	0	0
TlOutKnown_A	2049979927	2049845846	0	0
TlOutPayloadKnown_A	2049979927	23047058	0	0
TlOutPayloadKnown_AKnownEnable	2049979927	2049845846	0	0
WdataOutKnown_A	2049979927	2049845846	0	0
WeOutKnown_A	2049979927	2049845846	0	0
WmaskOutKnown_A	2049979927	2049845846	0	0
adapterNoReadOrWrite	1601	1601	0	0
rvalidHighReqFifoEmpty	2049979927	4819250	0	0
rvalidHighWhenRspFifoFull	2049979927	4819250	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	23047058	0	0
T1	270361	14665	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20908	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1025	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	4819250	0	0
T1	270361	329	0	0
T2	348489	11802	0	0
T3	1222	0	0	0
T8	517454	428	0	0
T10	1745	0	0	0
T11	325051	3165	0	0
T13	396572	0	0	0
T14	175528	17659	0	0
T31	105784	0	0	0
T32	0	15968	0	0
T33	0	11233	0	0
T34	0	12482	0	0
T35	0	8760	0	0
T37	1428	0	0	0
T45	0	7	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	4819250	0	0
T1	270361	329	0	0
T2	348489	11802	0	0
T3	1222	0	0	0
T8	517454	428	0	0
T10	1745	0	0	0
T11	325051	3165	0	0
T13	396572	0	0	0
T14	175528	17659	0	0
T31	105784	0	0	0
T32	0	15968	0	0
T33	0	11233	0	0
T34	0	12482	0	0
T35	0	8760	0	0
T37	1428	0	0	0
T45	0	7	0	0