Group : spi_device_env_pkg::tpm_read_hw_reg_cg_wrap::tpm_read_hw_reg_cg
Group Instance : tpm_access_0
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_0
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_1
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_1
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_2
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_2
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_3
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_3
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_3
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_4
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_4
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_4
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_did_vid
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_did_vid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_did_vid
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_hash_start
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_hash_start
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_hash_start
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_enable
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_enable
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_status
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_status
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_status
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_vector
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_vector
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_vector
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_intf_capability
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_intf_capability
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_intf_capability
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_rid
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_rid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_rid
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_sts
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_sts
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
782 |
1 |
|
|
T50 |
6 |
|
T52 |
2 |
|
T121 |
10 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
820 |
1 |
|
|
T50 |
10 |
|
T121 |
2 |
|
T123 |
14 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
720 |
1 |
|
|
T50 |
8 |
|
T52 |
2 |
|
T121 |
2 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
790 |
1 |
|
|
T50 |
14 |
|
T52 |
6 |
|
T123 |
20 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
760 |
1 |
|
|
T50 |
4 |
|
T52 |
2 |
|
T121 |
6 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
3730 |
1 |
|
|
T50 |
40 |
|
T52 |
8 |
|
T121 |
8 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
3788 |
1 |
|
|
T50 |
52 |
|
T52 |
10 |
|
T121 |
8 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
3888 |
1 |
|
|
T50 |
46 |
|
T52 |
10 |
|
T121 |
20 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
3716 |
1 |
|
|
T50 |
42 |
|
T52 |
10 |
|
T121 |
16 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
3898 |
1 |
|
|
T50 |
48 |
|
T52 |
12 |
|
T121 |
10 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
done |
6 |
1 |
|
|
T121 |
4 |
|
T128 |
2 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
3926 |
1 |
|
|
T50 |
42 |
|
T52 |
4 |
|
T121 |
18 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
3311 |
1 |
|
|
T50 |
32 |
|
T52 |
10 |
|
T121 |
13 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |