Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153370727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19913262

1

T4

1

T1

391

T2

104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	160591318	1			T4	1		T1	173		T2	101
values[0x0]	6346503	1			T1	166		T2	49		T9	570
values[0x1]	6346168	1			T1	153		T2	51		T9	527

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78642293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

94641696

1

T4

1

T1

434

T2

156

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	734410	1			T3	3		T8	2		T12	93
valid_sources[0x01]	630696	1			T3	3		T12	3118		T82	3
valid_sources[0x02]	726726	1			T3	2		T8	1		T12	3574
valid_sources[0x03]	651677	1			T3	2		T8	1		T12	1576
valid_sources[0x04]	729275	1			T3	2		T8	1		T12	1205
valid_sources[0x05]	641118	1			T12	1605		T82	4		T83	2
valid_sources[0x06]	649855	1			T3	1		T12	2145		T83	1
valid_sources[0x07]	695941	1			T3	1		T8	2		T12	3347
valid_sources[0x08]	663991	1			T3	4		T12	2425		T81	8
valid_sources[0x09]	698960	1			T3	3		T12	1689		T81	3
valid_sources[0x0a]	681999	1			T3	1		T8	2		T12	2906
valid_sources[0x0b]	654901	1			T3	5		T12	1372		T82	1
valid_sources[0x0c]	664600	1			T2	9		T3	2		T8	1
valid_sources[0x0d]	690545	1			T3	1		T12	2786		T78	5
valid_sources[0x0e]	713555	1			T3	4		T12	2555		T82	7
valid_sources[0x0f]	709647	1			T12	2902		T78	1		T81	14
valid_sources[0x10]	723803	1			T3	3		T12	693		T82	6
valid_sources[0x11]	685038	1			T8	1		T12	4717		T81	1
valid_sources[0x12]	692986	1			T3	2		T8	1		T12	1751
valid_sources[0x13]	678601	1			T9	547		T3	1		T12	2935
valid_sources[0x14]	759516	1			T3	2		T8	1		T12	1121
valid_sources[0x15]	663624	1			T12	3508		T82	9		T83	5
valid_sources[0x16]	699817	1			T3	1		T8	1		T12	1889
valid_sources[0x17]	666618	1			T3	1		T8	1		T12	697
valid_sources[0x18]	684474	1			T3	4		T8	1		T12	1383
valid_sources[0x19]	651904	1			T3	1		T12	142		T87	2
valid_sources[0x1a]	653750	1			T3	1		T12	3118		T82	5
valid_sources[0x1b]	665897	1			T2	14		T8	1		T12	2972
valid_sources[0x1c]	699449	1			T8	1		T12	3347		T85	1
valid_sources[0x1d]	712469	1			T3	1		T12	2455		T82	1
valid_sources[0x1e]	680011	1			T8	1		T12	3711		T82	1
valid_sources[0x1f]	708532	1			T2	26		T3	1		T8	2
valid_sources[0x20]	701258	1			T3	1		T12	1090		T85	6
valid_sources[0x21]	696345	1			T8	1		T12	1038		T85	5
valid_sources[0x22]	664153	1			T3	5		T12	2342		T85	4
valid_sources[0x23]	650366	1			T3	3		T12	2810		T87	1
valid_sources[0x24]	692835	1			T3	6		T12	3282		T82	6
valid_sources[0x25]	674570	1			T12	1777		T78	3		T82	4
valid_sources[0x26]	692753	1			T3	6		T12	900		T85	3
valid_sources[0x27]	625949	1			T3	1		T8	1		T12	1060
valid_sources[0x28]	660608	1			T3	3		T8	2		T12	2881
valid_sources[0x29]	695693	1			T3	4		T12	1240		T85	3
valid_sources[0x2a]	650542	1			T2	10		T3	3		T12	2192
valid_sources[0x2b]	695519	1			T3	1		T8	1		T12	4704
valid_sources[0x2c]	657749	1			T3	1		T12	3043		T80	5
valid_sources[0x2d]	680133	1			T3	1		T12	1757		T78	6
valid_sources[0x2e]	725314	1			T3	4		T12	1110		T78	2
valid_sources[0x2f]	734379	1			T12	499		T78	3		T85	1
valid_sources[0x30]	639697	1			T3	4		T8	1		T12	858
valid_sources[0x31]	650783	1			T12	3564		T78	11		T81	4
valid_sources[0x32]	654487	1			T3	2		T12	499		T80	8
valid_sources[0x33]	678836	1			T3	3		T8	1		T12	2848
valid_sources[0x34]	614597	1			T3	1		T8	1		T12	545
valid_sources[0x35]	710092	1			T3	1		T8	2		T12	5772
valid_sources[0x36]	667276	1			T8	2		T12	4752		T78	1
valid_sources[0x37]	640570	1			T3	3		T12	2379		T82	1
valid_sources[0x38]	661531	1			T3	8		T12	5652		T82	2
valid_sources[0x39]	686208	1			T3	1		T12	6146		T87	1
valid_sources[0x3a]	647358	1			T3	2		T12	2152		T82	3
valid_sources[0x3b]	684683	1			T3	1		T12	612		T82	3
valid_sources[0x3c]	655003	1			T3	2		T12	2627		T78	2
valid_sources[0x3d]	666251	1			T3	1		T12	2627		T79	1
valid_sources[0x3e]	695547	1			T3	1		T8	1		T12	2506
valid_sources[0x3f]	883864	1			T3	1		T8	3		T12	2275
valid_sources[0x40]	635228	1			T12	2581		T87	1		T82	2
valid_sources[0x41]	668712	1			T3	5		T12	3826		T85	7
valid_sources[0x42]	673598	1			T2	12		T8	1		T12	213
valid_sources[0x43]	654994	1			T3	2		T12	817		T82	3
valid_sources[0x44]	664727	1			T3	1		T8	3		T12	2798
valid_sources[0x45]	678145	1			T3	1		T8	1		T12	1936
valid_sources[0x46]	663709	1			T3	1		T12	910		T82	4
valid_sources[0x47]	695980	1			T3	3		T8	2		T12	1287
valid_sources[0x48]	671964	1			T3	1		T12	2846		T87	1
valid_sources[0x49]	697837	1			T8	1		T12	1467		T85	11
valid_sources[0x4a]	681295	1			T3	1		T8	2		T12	2894
valid_sources[0x4b]	641401	1			T3	1		T12	3780		T82	2
valid_sources[0x4c]	693679	1			T3	6		T12	402		T78	2
valid_sources[0x4d]	687963	1			T12	552		T78	5		T85	7
valid_sources[0x4e]	665778	1			T3	10		T12	1634		T82	6
valid_sources[0x4f]	647474	1			T8	1		T12	132		T85	3
valid_sources[0x50]	678591	1			T12	2128		T79	6		T85	9
valid_sources[0x51]	694747	1			T3	3		T8	1		T12	411
valid_sources[0x52]	634078	1			T3	1		T8	2		T12	4018
valid_sources[0x53]	671367	1			T12	2079		T82	3		T83	5
valid_sources[0x54]	678317	1			T12	2646		T78	1		T85	2
valid_sources[0x55]	667145	1			T3	4		T8	4		T12	2034
valid_sources[0x56]	670810	1			T3	2		T8	1		T12	798
valid_sources[0x57]	663669	1			T3	4		T12	772		T81	2
valid_sources[0x58]	716929	1			T3	2		T12	1956		T78	4
valid_sources[0x59]	709062	1			T3	2		T12	2387		T87	1
valid_sources[0x5a]	667176	1			T3	5		T12	1307		T78	1
valid_sources[0x5b]	643252	1			T3	6		T8	1		T12	1638
valid_sources[0x5c]	650981	1			T3	5		T12	3389		T81	3
valid_sources[0x5d]	694871	1			T3	1		T8	2		T12	1033
valid_sources[0x5e]	657164	1			T2	22		T3	1		T12	2013
valid_sources[0x5f]	676640	1			T12	1396		T78	2		T82	8
valid_sources[0x60]	669972	1			T2	29		T12	4576		T78	2
valid_sources[0x61]	686105	1			T8	1		T12	2533		T78	13
valid_sources[0x62]	666750	1			T3	4		T12	39		T79	3
valid_sources[0x63]	689511	1			T2	13		T3	3		T8	2
valid_sources[0x64]	678570	1			T3	1		T8	1		T12	3512
valid_sources[0x65]	678119	1			T3	1		T8	1		T12	2618
valid_sources[0x66]	670851	1			T3	1		T8	2		T12	1678
valid_sources[0x67]	673612	1			T3	3		T12	1521		T78	4
valid_sources[0x68]	639998	1			T3	1		T12	2636		T78	3
valid_sources[0x69]	616826	1			T3	4		T8	1		T12	1846
valid_sources[0x6a]	716444	1			T3	4		T8	5		T12	2161
valid_sources[0x6b]	677260	1			T3	5		T8	1		T12	966
valid_sources[0x6c]	659439	1			T3	4		T12	1518		T78	2
valid_sources[0x6d]	696015	1			T3	4		T8	1		T12	2474
valid_sources[0x6e]	693466	1			T3	3		T8	1		T12	3109
valid_sources[0x6f]	686425	1			T2	5		T3	1		T8	1
valid_sources[0x70]	707452	1			T3	7		T12	3611		T82	2
valid_sources[0x71]	701801	1			T3	3		T12	2015		T79	7
valid_sources[0x72]	676233	1			T3	2		T12	4401		T78	1
valid_sources[0x73]	711121	1			T3	3		T8	1		T12	1240
valid_sources[0x74]	647679	1			T3	2		T8	2		T12	676
valid_sources[0x75]	692625	1			T3	1		T12	3402		T85	12
valid_sources[0x76]	682411	1			T3	1		T8	1		T12	2294
valid_sources[0x77]	652043	1			T3	3		T12	2821		T85	7
valid_sources[0x78]	647990	1			T3	3		T8	1		T12	1317
valid_sources[0x79]	648603	1			T3	3		T8	2		T12	2442
valid_sources[0x7a]	667428	1			T3	4		T8	1		T12	2477
valid_sources[0x7b]	665052	1			T3	3		T8	1		T12	3422
valid_sources[0x7c]	685580	1			T8	2		T12	568		T82	3
valid_sources[0x7d]	667612	1			T2	1		T3	3		T8	1
valid_sources[0x7e]	659196	1			T3	1		T12	3184		T78	3
valid_sources[0x7f]	680866	1			T3	3		T12	7497		T78	3
valid_sources[0x80]	672804	1			T3	1		T12	4544		T85	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7636225

1

T4

1

T1

85

T2

4

values[0x0]

all_enables

biggest_size

6151490

1

T1

161

T2

49

T9

570

values[0x1]

all_enables

biggest_size

6125547

1

T1

145

T2

51

T9

520