Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

153394208

1

T1

101

T9

21

T3

168

full_word

19912525

1

T4

1

T1

391

T9

1101

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	173306383	1			T4	1		T1	492		T9	1122
auto[TlIntgErrCmd]	105	1			T135	5		T136	7		T138	3
auto[TlIntgErrData]	119	1			T135	4		T136	7		T138	8
auto[TlIntgErrBoth]	126	1			T135	1		T136	6		T138	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160591901

1

T4

1

T1

173

T9

25

auto[1]

12714832

1

T1

319

T9

1097

T3

340

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152955432	1			T1	88		T9	14		T3	156
auto[TlIntgErrNone]	partial	auto[1]	438446	1			T1	13		T9	7		T3	12
auto[TlIntgErrNone]	full_word	auto[0]	7636302	1			T4	1		T1	85		T9	11
auto[TlIntgErrNone]	full_word	auto[1]	12276203	1			T1	306		T9	1090		T3	328
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T135	4		T136	4		T138	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T135	1		T136	2		T138	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T136	1		T169	1		T241	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T240	1		T242	1		T243	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T135	1		T136	5		T138	5
auto[TlIntgErrData]	partial	auto[1]	50	1			T135	3		T136	2		T138	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T138	1		T178	1		T244	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T169	1		T170	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T138	3		T169	2		T245	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T135	1		T136	5		T138	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T177	1		T243	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T136	1		T178	1		T242	1