Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	144	144	100.00
Total Bits 0->1	72	72	100.00
Total Bits 1->0	72	72	100.00

Ports	5	5	100.00
Port Bits	144	144	100.00
Port Bits 0->1	72	72	100.00
Port Bits 1->0	72	72	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	INPUT
rst_ni	Yes	Yes	T28,T150,T153	Yes	T4,T1,T2	INPUT
oh_i[6:0]	Yes	Yes	*T1,*T3,*T8	Yes	T1,T3,T8	INPUT
oh_i[8:7]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[13:9]	Yes	Yes	*T1,*T3,*T8	Yes	T1,T3,T8	INPUT
oh_i[14]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[19:15]	Yes	Yes	T9,*T15,T10	Yes	T9,T15,T10	INPUT
oh_i[23:20]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[63:24]	Yes	Yes	*T9,T15,*T10	Yes	T9,T15,T10	INPUT
oh_i[64]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[65]	Yes	Yes	*T5,*T50,*T52	Yes	T5,T50,T52	INPUT
oh_i[66]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[75:67]	Yes	Yes	T5,T50,T52	Yes	T5,T50,T52	INPUT
oh_i[76]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[77]	Yes	Yes	*T5,*T52,*T6	Yes	T5,T52,T6	INPUT
oh_i[78]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[6:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	INPUT
err_o	Yes	Yes	T108,T109,T110	Yes	T108,T109,T110	OUTPUT

*Tests covering at least one bit in the range