Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.53	100.00

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T3
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T2

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	4821	4821	0	0
GntImpliesReady_A	2147483647	21200096	0	0
GntImpliesValid_A	2147483647	21200096	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	21200096	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	0	0	0
ReadyAndValidImplyGrant_A	2147483647	21200096	0	0
ReqAndReadyImplyGrant_A	2147483647	21200096	0	0
ReqImpliesValid_A	2147483647	21200096	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	583	0	2314
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	21200096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	58948	58883	0	0
T2	2039	1967	0	0
T3	18789	18707	0	0
T4	1093	1024	0	0
T8	5708	5650	0	0
T9	462889	462340	0	0
T10	45506	44616	0	0
T12	1263678	1263668	0	0
T13	614221	572958	0	0
T14	952099	952088	0	0
T15	32777	31321	0	0
T16	3099	3098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4821	4821	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T12	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21200096	0	0
T1	55889	340	0	0
T2	2039	200	0	0
T3	15517	368	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T8	5323	48	0	0
T9	291545	1024	0	0
T10	22753	1024	0	0
T11	101926	0	0	0
T12	1181181	10312	0	0
T13	247142	40728	0	0
T14	478145	59244	0	0
T15	22450	1024	0	0
T16	2682	26	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T40	0	445	0	0
T41	0	19	0	0
T42	1644	0	0	0
T44	0	7373	0	0
T49	75745	4734	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21200096	0	0
T1	55889	340	0	0
T2	2039	200	0	0
T3	15517	368	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T8	5323	48	0	0
T9	291545	1024	0	0
T10	22753	1024	0	0
T11	101926	0	0	0
T12	1181181	10312	0	0
T13	247142	40728	0	0
T14	478145	59244	0	0
T15	22450	1024	0	0
T16	2682	26	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T40	0	445	0	0
T41	0	19	0	0
T42	1644	0	0	0
T44	0	7373	0	0
T49	75745	4734	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	58948	58883	0	0
T2	2039	1967	0	0
T3	18789	18707	0	0
T4	1093	1024	0	0
T8	5708	5650	0	0
T9	462889	462340	0	0
T10	45506	44616	0	0
T12	1263678	1263668	0	0
T13	614221	572958	0	0
T14	952099	952088	0	0
T15	32777	31321	0	0
T16	3099	3098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	58948	58883	0	0
T2	2039	1967	0	0
T3	18789	18707	0	0
T4	1093	1024	0	0
T8	5708	5650	0	0
T9	462889	462340	0	0
T10	45506	44616	0	0
T12	1263678	1263668	0	0
T13	614221	572958	0	0
T14	952099	952088	0	0
T15	32777	31321	0	0
T16	3099	3098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21200096	0	0
T1	55889	340	0	0
T2	2039	200	0	0
T3	15517	368	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T8	5323	48	0	0
T9	291545	1024	0	0
T10	22753	1024	0	0
T11	101926	0	0	0
T12	1181181	10312	0	0
T13	247142	40728	0	0
T14	478145	59244	0	0
T15	22450	1024	0	0
T16	2682	26	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T40	0	445	0	0
T41	0	19	0	0
T42	1644	0	0	0
T44	0	7373	0	0
T49	75745	4734	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21200096	0	0
T1	55889	340	0	0
T2	2039	200	0	0
T3	15517	368	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T8	5323	48	0	0
T9	291545	1024	0	0
T10	22753	1024	0	0
T11	101926	0	0	0
T12	1181181	10312	0	0
T13	247142	40728	0	0
T14	478145	59244	0	0
T15	22450	1024	0	0
T16	2682	26	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T40	0	445	0	0
T41	0	19	0	0
T42	1644	0	0	0
T44	0	7373	0	0
T49	75745	4734	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21200096	0	0
T1	55889	340	0	0
T2	2039	200	0	0
T3	15517	368	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T8	5323	48	0	0
T9	291545	1024	0	0
T10	22753	1024	0	0
T11	101926	0	0	0
T12	1181181	10312	0	0
T13	247142	40728	0	0
T14	478145	59244	0	0
T15	22450	1024	0	0
T16	2682	26	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T40	0	445	0	0
T41	0	19	0	0
T42	1644	0	0	0
T44	0	7373	0	0
T49	75745	4734	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21200096	0	0
T1	55889	340	0	0
T2	2039	200	0	0
T3	15517	368	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T8	5323	48	0	0
T9	291545	1024	0	0
T10	22753	1024	0	0
T11	101926	0	0	0
T12	1181181	10312	0	0
T13	247142	40728	0	0
T14	478145	59244	0	0
T15	22450	1024	0	0
T16	2682	26	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T40	0	445	0	0
T41	0	19	0	0
T42	1644	0	0	0
T44	0	7373	0	0
T49	75745	4734	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	583	0	2314
T27	702596	0	0	0
T54	348021	13	0	1
T55	110724	9	0	1
T56	0	1	0	1
T57	0	115	0	1
T58	0	37	0	0
T59	0	5	0	0
T60	0	3	0	0
T61	0	2	0	0
T62	0	3	0	0
T63	0	3	0	0
T64	8258	0	0	0
T65	966785	0	0	1
T66	19676	0	0	1
T67	180557	0	0	0
T68	60941	0	0	1
T69	63966	0	0	1
T70	1184	0	0	0
T71	0	0	0	0
T72	0	0	0	0
T73	0	0	0	0
T74	0	0	0	0
T75	0	0	0	0
T76	0	0	0	1
T77	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	58948	58883	0	0
T2	2039	1967	0	0
T3	18789	18707	0	0
T4	1093	1024	0	0
T8	5708	5650	0	0
T9	462889	462340	0	0
T10	45506	44616	0	0
T12	1263678	1263668	0	0
T13	614221	572958	0	0
T14	952099	952088	0	0
T15	32777	31321	0	0
T16	3099	3098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21200096	0	0
T1	55889	340	0	0
T2	2039	200	0	0
T3	15517	368	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T8	5323	48	0	0
T9	291545	1024	0	0
T10	22753	1024	0	0
T11	101926	0	0	0
T12	1181181	10312	0	0
T13	247142	40728	0	0
T14	478145	59244	0	0
T15	22450	1024	0	0
T16	2682	26	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T40	0	445	0	0
T41	0	19	0	0
T42	1644	0	0	0
T44	0	7373	0	0
T49	75745	4734	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T5,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386536807	335033634	0	0
CheckNGreaterZero_A	1607	1607	0	0
GntImpliesReady_A	386536807	712707	0	0
GntImpliesValid_A	386536807	712707	0	0
GrantKnown_A	386536807	335033634	0	0
IdxKnown_A	386536807	335033634	0	0
IndexIsCorrect_A	386536807	712707	0	0
LockArbDecision_A	386536807	0	0	0
NoReadyValidNoGrant_A	386536807	0	0	0
ReadyAndValidImplyGrant_A	386536807	712707	0	0
ReqAndReadyImplyGrant_A	386536807	712707	0	0
ReqImpliesValid_A	386536807	712707	0	0
ReqStaysHighUntilGranted0_M	386536807	0	0	0
RoundRobin_A	386536807	0	0	0
ValidKnown_A	386536807	335033634	0	0
gen_data_port_assertion.DataFlow_A	386536807	712707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	335033634	0	0
T1	3059	3051	0	0
T3	3272	3263	0	0
T8	385	384	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	82497	82496	0	0
T13	367079	325824	0	0
T14	473954	473952	0	0
T15	10327	9632	0	0
T16	417	416	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	712707	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T11	101926	0	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T27	0	6497	0	0
T28	0	2063	0	0
T33	20673	0	0	0
T44	0	7373	0	0
T45	0	1747	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	712707	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T11	101926	0	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T27	0	6497	0	0
T28	0	2063	0	0
T33	20673	0	0	0
T44	0	7373	0	0
T45	0	1747	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	335033634	0	0
T1	3059	3051	0	0
T3	3272	3263	0	0
T8	385	384	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	82497	82496	0	0
T13	367079	325824	0	0
T14	473954	473952	0	0
T15	10327	9632	0	0
T16	417	416	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	335033634	0	0
T1	3059	3051	0	0
T3	3272	3263	0	0
T8	385	384	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	82497	82496	0	0
T13	367079	325824	0	0
T14	473954	473952	0	0
T15	10327	9632	0	0
T16	417	416	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	712707	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T11	101926	0	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T27	0	6497	0	0
T28	0	2063	0	0
T33	20673	0	0	0
T44	0	7373	0	0
T45	0	1747	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	712707	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T11	101926	0	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T27	0	6497	0	0
T28	0	2063	0	0
T33	20673	0	0	0
T44	0	7373	0	0
T45	0	1747	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	712707	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T11	101926	0	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T27	0	6497	0	0
T28	0	2063	0	0
T33	20673	0	0	0
T44	0	7373	0	0
T45	0	1747	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	712707	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T11	101926	0	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T27	0	6497	0	0
T28	0	2063	0	0
T33	20673	0	0	0
T44	0	7373	0	0
T45	0	1747	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	335033634	0	0
T1	3059	3051	0	0
T3	3272	3263	0	0
T8	385	384	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	82497	82496	0	0
T13	367079	325824	0	0
T14	473954	473952	0	0
T15	10327	9632	0	0
T16	417	416	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	712707	0	0
T5	144411	774	0	0
T6	624216	7147	0	0
T7	0	1729	0	0
T11	101926	0	0	0
T18	0	264	0	0
T19	78353	0	0	0
T20	0	3329	0	0
T22	0	11	0	0
T27	0	6497	0	0
T28	0	2063	0	0
T33	20673	0	0	0
T44	0	7373	0	0
T45	0	1747	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T9
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1929928785	1929792554	0	0
CheckNGreaterZero_A	1607	1607	0	0
GntImpliesReady_A	1929928785	11640682	0	0
GntImpliesValid_A	1929928785	11640682	0	0
GrantKnown_A	1929928785	1929792554	0	0
IdxKnown_A	1929928785	1929792554	0	0
IndexIsCorrect_A	1929928785	11640682	0	0
LockArbDecision_A	1929928785	0	0	0
NoReadyValidNoGrant_A	1929928785	0	0	0
ReadyAndValidImplyGrant_A	1929928785	11640682	0	0
ReqAndReadyImplyGrant_A	1929928785	11640682	0	0
ReqImpliesValid_A	1929928785	11640682	0	0
ReqStaysHighUntilGranted0_M	1929928785	0	0	0
RoundRobin_A	1929928785	0	0	1607
ValidKnown_A	1929928785	1929792554	0	0
gen_data_port_assertion.DataFlow_A	1929928785	11640682	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11640682	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11640682	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11640682	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11640682	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11640682	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11640682	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	0	0	1607

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11640682	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T3
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1477438707	1438501198	0	0
CheckNGreaterZero_A	1607	1607	0	0
GntImpliesReady_A	1477438707	8846707	0	0
GntImpliesValid_A	1477438707	8846707	0	0
GrantKnown_A	1477438707	1438501198	0	0
IdxKnown_A	1477438707	1438501198	0	0
IndexIsCorrect_A	1477438707	8846707	0	0
LockArbDecision_A	1477438707	0	0	0
NoReadyValidNoGrant_A	1477438707	0	0	0
ReadyAndValidImplyGrant_A	1477438707	8846707	0	0
ReqAndReadyImplyGrant_A	1477438707	8846707	0	0
ReqImpliesValid_A	1477438707	8846707	0	0
ReqStaysHighUntilGranted0_M	1477438707	0	0	0
RoundRobin_A	1477438707	583	0	707
ValidKnown_A	1477438707	1438501198	0	0
gen_data_port_assertion.DataFlow_A	1477438707	8846707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	1438501198	0	0
T1	27908	27908	0	0
T3	7701	7701	0	0
T8	2625	2625	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	590585	590585	0	0
T13	123566	123566	0	0
T14	239067	239067	0	0
T15	10327	9632	0	0
T16	2682	2682	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	8846707	0	0
T1	27908	170	0	0
T3	7701	184	0	0
T8	2625	24	0	0
T9	171344	0	0	0
T10	22753	0	0	0
T12	590585	5156	0	0
T13	123566	20364	0	0
T14	239067	29622	0	0
T15	10327	0	0	0
T16	2682	26	0	0
T40	0	445	0	0
T41	0	19	0	0
T49	0	4734	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	8846707	0	0
T1	27908	170	0	0
T3	7701	184	0	0
T8	2625	24	0	0
T9	171344	0	0	0
T10	22753	0	0	0
T12	590585	5156	0	0
T13	123566	20364	0	0
T14	239067	29622	0	0
T15	10327	0	0	0
T16	2682	26	0	0
T40	0	445	0	0
T41	0	19	0	0
T49	0	4734	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	1438501198	0	0
T1	27908	27908	0	0
T3	7701	7701	0	0
T8	2625	2625	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	590585	590585	0	0
T13	123566	123566	0	0
T14	239067	239067	0	0
T15	10327	9632	0	0
T16	2682	2682	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	1438501198	0	0
T1	27908	27908	0	0
T3	7701	7701	0	0
T8	2625	2625	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	590585	590585	0	0
T13	123566	123566	0	0
T14	239067	239067	0	0
T15	10327	9632	0	0
T16	2682	2682	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	8846707	0	0
T1	27908	170	0	0
T3	7701	184	0	0
T8	2625	24	0	0
T9	171344	0	0	0
T10	22753	0	0	0
T12	590585	5156	0	0
T13	123566	20364	0	0
T14	239067	29622	0	0
T15	10327	0	0	0
T16	2682	26	0	0
T40	0	445	0	0
T41	0	19	0	0
T49	0	4734	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	8846707	0	0
T1	27908	170	0	0
T3	7701	184	0	0
T8	2625	24	0	0
T9	171344	0	0	0
T10	22753	0	0	0
T12	590585	5156	0	0
T13	123566	20364	0	0
T14	239067	29622	0	0
T15	10327	0	0	0
T16	2682	26	0	0
T40	0	445	0	0
T41	0	19	0	0
T49	0	4734	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	8846707	0	0
T1	27908	170	0	0
T3	7701	184	0	0
T8	2625	24	0	0
T9	171344	0	0	0
T10	22753	0	0	0
T12	590585	5156	0	0
T13	123566	20364	0	0
T14	239067	29622	0	0
T15	10327	0	0	0
T16	2682	26	0	0
T40	0	445	0	0
T41	0	19	0	0
T49	0	4734	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	8846707	0	0
T1	27908	170	0	0
T3	7701	184	0	0
T8	2625	24	0	0
T9	171344	0	0	0
T10	22753	0	0	0
T12	590585	5156	0	0
T13	123566	20364	0	0
T14	239067	29622	0	0
T15	10327	0	0	0
T16	2682	26	0	0
T40	0	445	0	0
T41	0	19	0	0
T49	0	4734	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	583	0	707
T27	702596	0	0	0
T54	348021	13	0	1
T55	110724	9	0	1
T56	0	1	0	1
T57	0	115	0	1
T58	0	37	0	0
T59	0	5	0	0
T60	0	3	0	0
T61	0	2	0	0
T62	0	3	0	0
T63	0	3	0	0
T64	8258	0	0	0
T65	966785	0	0	1
T66	19676	0	0	1
T67	180557	0	0	0
T68	60941	0	0	1
T69	63966	0	0	1
T70	1184	0	0	0
T71	0	0	0	0
T72	0	0	0	0
T73	0	0	0	0
T74	0	0	0	0
T75	0	0	0	0
T76	0	0	0	1
T77	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	1438501198	0	0
T1	27908	27908	0	0
T3	7701	7701	0	0
T8	2625	2625	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	590585	590585	0	0
T13	123566	123566	0	0
T14	239067	239067	0	0
T15	10327	9632	0	0
T16	2682	2682	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1477438707	8846707	0	0
T1	27908	170	0	0
T3	7701	184	0	0
T8	2625	24	0	0
T9	171344	0	0	0
T10	22753	0	0	0
T12	590585	5156	0	0
T13	123566	20364	0	0
T14	239067	29622	0	0
T15	10327	0	0	0
T16	2682	26	0	0
T40	0	445	0	0
T41	0	19	0	0
T49	0	4734	0	0