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Module Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.81 100.00 69.23 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.89 95.00 69.23 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.66 94.03 73.28 83.33 100.00 u_tlul2sram_ingress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.03 100.00 76.47 91.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.12 95.00 76.47 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.66 94.03 73.28 83.33 100.00 u_tlul2sram_ingress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.94 88.89 75.00


Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.85 100.00 65.38 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.96 100.00 65.38 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_sys_sram_arbiter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_tlul2sram_ingress.u_sramreqfifo
tb.dut.u_tlul2sram_ingress.u_rspfifo
tb.dut.u_sys_sram_arbiter.u_req_fifo
tb.dut.u_reg.u_socket.fifo_h.reqfifo
tb.dut.u_reg.u_socket.fifo_h.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
TotalCoveredPercent
Conditions261869.23
Logical261869.23
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T23 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T5,T23 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT4,T5,T23 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T23
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T23 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T23 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T23
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T23
0 1 Covered T1,T2,T3
0 0 Not Covered 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T23 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T5,T23
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 576134620 56689 0 0
DepthKnown_A 576134620 576051877 0 0
RvalidKnown_A 576134620 576051877 0 0
WreadyKnown_A 576134620 576051877 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 576134620 56689 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 56689 0 0
T4 314426 641 0 0
T5 591984 64 0 0
T6 63231 0 0 0
T14 177435 0 0 0
T15 7937 0 0 0
T18 66879 0 0 0
T19 5782 0 0 0
T22 1292 0 0 0
T23 0 326 0 0
T24 0 100 0 0
T25 0 100 0 0
T27 0 129 0 0
T28 0 321 0 0
T29 0 544 0 0
T30 0 424 0 0
T31 0 175 0 0
T32 1270 0 0 0
T33 990 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 56689 0 0
T4 314426 641 0 0
T5 591984 64 0 0
T6 63231 0 0 0
T14 177435 0 0 0
T15 7937 0 0 0
T18 66879 0 0 0
T19 5782 0 0 0
T22 1292 0 0 0
T23 0 326 0 0
T24 0 100 0 0
T25 0 100 0 0
T27 0 129 0 0
T28 0 321 0 0
T29 0 544 0 0
T30 0 424 0 0
T31 0 175 0 0
T32 1270 0 0 0
T33 990 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
TotalCoveredPercent
Conditions342676.47
Logical342676.47
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T23 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T5,T23 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T23
110Not Covered
111CoveredT4,T5,T23 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T23
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T23 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T23 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T23 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T5,T23 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT4,T5,T23
10CoveredT4,T5,T23
11CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T23
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
Line No.TotalCoveredPercent
Branches 12 11 91.67
TERNARY 88 3 2 66.67
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T23
0 1 Covered T1,T2,T3
0 0 Not Covered 



	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T23
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T23 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T5,T23
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 576134620 144105 0 0
DepthKnown_A 576134620 576051877 0 0
RvalidKnown_A 576134620 576051877 0 0
WreadyKnown_A 576134620 576051877 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 576134620 144105 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 144105 0 0
T4 314426 2950 0 0
T5 591984 331 0 0
T6 63231 0 0 0
T14 177435 0 0 0
T15 7937 0 0 0
T18 66879 0 0 0
T19 5782 0 0 0
T22 1292 0 0 0
T23 0 1034 0 0
T24 0 100 0 0
T25 0 100 0 0
T27 0 545 0 0
T28 0 321 0 0
T29 0 544 0 0
T30 0 1090 0 0
T31 0 175 0 0
T32 1270 0 0 0
T33 990 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 144105 0 0
T4 314426 2950 0 0
T5 591984 331 0 0
T6 63231 0 0 0
T14 177435 0 0 0
T15 7937 0 0 0
T18 66879 0 0 0
T19 5782 0 0 0
T22 1292 0 0 0
T23 0 1034 0 0
T24 0 100 0 0
T25 0 100 0 0
T27 0 545 0 0
T28 0 321 0 0
T29 0 544 0 0
T30 0 1090 0 0
T31 0 175 0 0
T32 1270 0 0 0
T33 990 0 0 0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
TotalCoveredPercent
Conditions261765.38
Logical261765.38
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T5,T6 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT4,T5,T6 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T6 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 576134620 61014 0 0
DepthKnown_A 576134620 576051877 0 0
RvalidKnown_A 576134620 576051877 0 0
WreadyKnown_A 576134620 576051877 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 576134620 61014 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 61014 0 0
T4 314426 698 0 0
T5 591984 66 0 0
T6 63231 4 0 0
T14 177435 0 0 0
T15 7937 0 0 0
T18 66879 0 0 0
T19 5782 0 0 0
T22 1292 0 0 0
T23 0 343 0 0
T27 0 138 0 0
T28 0 367 0 0
T29 0 585 0 0
T30 0 451 0 0
T31 0 183 0 0
T32 1270 0 0 0
T33 990 0 0 0
T42 0 4 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 576051877 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 576134620 61014 0 0
T4 314426 698 0 0
T5 591984 66 0 0
T6 63231 4 0 0
T14 177435 0 0 0
T15 7937 0 0 0
T18 66879 0 0 0
T19 5782 0 0 0
T22 1292 0 0 0
T23 0 343 0 0
T27 0 138 0 0
T28 0 367 0 0
T29 0 585 0 0
T30 0 451 0 0
T31 0 183 0 0
T32 1270 0 0 0
T33 990 0 0 0
T42 0 4 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 577947680 16634923 0 0
DepthKnown_A 577947680 577824082 0 0
RvalidKnown_A 577947680 577824082 0 0
WreadyKnown_A 577947680 577824082 0 0
gen_passthru_fifo.paramCheckPass 1095 1095 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 16634923 0 0
T1 2048 61 0 0
T2 11842 429 0 0
T3 380270 12454 0 0
T7 55033 911 0 0
T8 152980 1990 0 0
T9 68355 881 0 0
T10 1520 45 0 0
T11 19483 914 0 0
T12 566282 2623 0 0
T16 950 21 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1095 1095 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 577947680 31297796 0 0
DepthKnown_A 577947680 577824082 0 0
RvalidKnown_A 577947680 577824082 0 0
WreadyKnown_A 577947680 577824082 0 0
gen_passthru_fifo.paramCheckPass 1095 1095 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 31297796 0 0
T1 2048 182 0 0
T2 11842 429 0 0
T3 380270 54640 0 0
T7 55033 911 0 0
T8 152980 1158 0 0
T9 68355 881 0 0
T10 1520 45 0 0
T11 19483 914 0 0
T12 566282 4819 0 0
T16 950 100 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1095 1095 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 577947680 3325833 0 0
DepthKnown_A 577947680 577824082 0 0
RvalidKnown_A 577947680 577824082 0 0
WreadyKnown_A 577947680 577824082 0 0
gen_passthru_fifo.paramCheckPass 1095 1095 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 3325833 0 0
T4 314426 16665 0 0
T5 0 3327 0 0
T7 55033 832 0 0
T8 152980 1663 0 0
T9 68355 832 0 0
T11 19483 832 0 0
T12 566282 1663 0 0
T13 11131 1666 0 0
T14 0 1663 0 0
T15 0 1663 0 0
T16 950 0 0 0
T17 26571 0 0 0
T18 66879 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1095 1095 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 577947680 3874135 0 0
DepthKnown_A 577947680 577824082 0 0
RvalidKnown_A 577947680 577824082 0 0
WreadyKnown_A 577947680 577824082 0 0
gen_passthru_fifo.paramCheckPass 1095 1095 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 3874135 0 0
T4 314426 35582 0 0
T5 0 8651 0 0
T7 55033 832 0 0
T8 152980 832 0 0
T9 68355 832 0 0
T11 19483 832 0 0
T12 566282 832 0 0
T13 11131 836 0 0
T14 0 832 0 0
T15 0 832 0 0
T16 950 0 0 0
T17 26571 0 0 0
T18 66879 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577947680 577824082 0 0
T1 2048 1980 0 0
T2 11842 11786 0 0
T3 380270 380176 0 0
T7 55033 54955 0 0
T8 152980 152899 0 0
T9 68355 68305 0 0
T10 1520 1449 0 0
T11 19483 19404 0 0
T12 566282 566207 0 0
T16 950 860 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1095 1095 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%