Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=4,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T7,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	763132514	721916079	0	0
CheckNGreaterZero_A	1844	1844	0	0
GntImpliesReady_A	763132514	2982210	0	0
GntImpliesValid_A	763132514	2982210	0	0
GrantKnown_A	763132514	721916079	0	0
IdxKnown_A	763132514	721916079	0	0
IndexIsCorrect_A	763132514	2982210	0	0
LockArbDecision_A	763132514	0	0	0
NoReadyValidNoGrant_A	763132514	0	0	0
ReadyAndValidImplyGrant_A	763132514	2982210	0	0
ReqAndReadyImplyGrant_A	763132514	2982210	0	0
ReqImpliesValid_A	763132514	2982210	0	0
ReqStaysHighUntilGranted0_M	763132514	0	0	0
RoundRobin_A	763132514	0	0	922
ValidKnown_A	763132514	721916079	0	0
gen_data_port_assertion.DataFlow_A	763132514	2982210	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	721916079	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	230890	229987	0	0
T8	227506	227425	0	0
T9	88783	88733	0	0
T10	1520	1449	0	0
T11	31232	31153	0	0
T12	706460	706385	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T16	950	860	0	0
T17	4250	0	0	0
T18	101454	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1844	1844	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T12	2	2	0	0
T16	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	2982210	0	0
T4	415159	23241	0	0
T5	518621	2820	0	0
T6	44222	4	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	221150	832	0	0
T15	13543	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	168333	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	2982210	0	0
T4	415159	23241	0	0
T5	518621	2820	0	0
T6	44222	4	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	221150	832	0	0
T15	13543	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	168333	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	721916079	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	230890	229987	0	0
T8	227506	227425	0	0
T9	88783	88733	0	0
T10	1520	1449	0	0
T11	31232	31153	0	0
T12	706460	706385	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T16	950	860	0	0
T17	4250	0	0	0
T18	101454	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	721916079	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	230890	229987	0	0
T8	227506	227425	0	0
T9	88783	88733	0	0
T10	1520	1449	0	0
T11	31232	31153	0	0
T12	706460	706385	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T16	950	860	0	0
T17	4250	0	0	0
T18	101454	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	2982210	0	0
T4	415159	23241	0	0
T5	518621	2820	0	0
T6	44222	4	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	221150	832	0	0
T15	13543	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	168333	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	2982210	0	0
T4	415159	23241	0	0
T5	518621	2820	0	0
T6	44222	4	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	221150	832	0	0
T15	13543	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	168333	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	2982210	0	0
T4	415159	23241	0	0
T5	518621	2820	0	0
T6	44222	4	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	221150	832	0	0
T15	13543	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	168333	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	2982210	0	0
T4	415159	23241	0	0
T5	518621	2820	0	0
T6	44222	4	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	221150	832	0	0
T15	13543	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	168333	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	0	0	922

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	721916079	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	230890	229987	0	0
T8	227506	227425	0	0
T9	88783	88733	0	0
T10	1520	1449	0	0
T11	31232	31153	0	0
T12	706460	706385	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T16	950	860	0	0
T17	4250	0	0	0
T18	101454	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763132514	2982210	0	0
T4	415159	23241	0	0
T5	518621	2820	0	0
T6	44222	4	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	221150	832	0	0
T15	13543	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	168333	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	186997894	145864202	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	186997894	710300	0	0
GntImpliesValid_A	186997894	710300	0	0
GrantKnown_A	186997894	145864202	0	0
IdxKnown_A	186997894	145864202	0	0
IndexIsCorrect_A	186997894	710300	0	0
LockArbDecision_A	186997894	0	0	0
NoReadyValidNoGrant_A	186997894	0	0	0
ReadyAndValidImplyGrant_A	186997894	710300	0	0
ReqAndReadyImplyGrant_A	186997894	710300	0	0
ReqImpliesValid_A	186997894	710300	0	0
ReqStaysHighUntilGranted0_M	186997894	0	0	0
RoundRobin_A	186997894	0	0	0
ValidKnown_A	186997894	145864202	0	0
gen_data_port_assertion.DataFlow_A	186997894	710300	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	145864202	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	175857	175032	0	0
T8	74526	74526	0	0
T9	20428	20428	0	0
T11	11749	11749	0	0
T12	140178	140178	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T17	4250	0	0	0
T18	101454	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	710300	0	0
T4	100733	10895	0	0
T5	518621	258	0	0
T6	44222	4	0	0
T14	221150	0	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	710300	0	0
T4	100733	10895	0	0
T5	518621	258	0	0
T6	44222	4	0	0
T14	221150	0	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	145864202	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	175857	175032	0	0
T8	74526	74526	0	0
T9	20428	20428	0	0
T11	11749	11749	0	0
T12	140178	140178	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T17	4250	0	0	0
T18	101454	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	145864202	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	175857	175032	0	0
T8	74526	74526	0	0
T9	20428	20428	0	0
T11	11749	11749	0	0
T12	140178	140178	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T17	4250	0	0	0
T18	101454	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	710300	0	0
T4	100733	10895	0	0
T5	518621	258	0	0
T6	44222	4	0	0
T14	221150	0	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	710300	0	0
T4	100733	10895	0	0
T5	518621	258	0	0
T6	44222	4	0	0
T14	221150	0	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	710300	0	0
T4	100733	10895	0	0
T5	518621	258	0	0
T6	44222	4	0	0
T14	221150	0	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	710300	0	0
T4	100733	10895	0	0
T5	518621	258	0	0
T6	44222	4	0	0
T14	221150	0	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	145864202	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	175857	175032	0	0
T8	74526	74526	0	0
T9	20428	20428	0	0
T11	11749	11749	0	0
T12	140178	140178	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T17	4250	0	0	0
T18	101454	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	710300	0	0
T4	100733	10895	0	0
T5	518621	258	0	0
T6	44222	4	0	0
T14	221150	0	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	6152	0	0
T27	0	3161	0	0
T28	0	1339	0	0
T29	0	3374	0	0
T30	0	1986	0	0
T31	0	967	0	0
T34	62877	0	0	0
T42	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T7,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	576134620	576051877	0	0
CheckNGreaterZero_A	922	922	0	0
GntImpliesReady_A	576134620	2271910	0	0
GntImpliesValid_A	576134620	2271910	0	0
GrantKnown_A	576134620	576051877	0	0
IdxKnown_A	576134620	576051877	0	0
IndexIsCorrect_A	576134620	2271910	0	0
LockArbDecision_A	576134620	0	0	0
NoReadyValidNoGrant_A	576134620	0	0	0
ReadyAndValidImplyGrant_A	576134620	2271910	0	0
ReqAndReadyImplyGrant_A	576134620	2271910	0	0
ReqImpliesValid_A	576134620	2271910	0	0
ReqStaysHighUntilGranted0_M	576134620	0	0	0
RoundRobin_A	576134620	0	0	922
ValidKnown_A	576134620	576051877	0	0
gen_data_port_assertion.DataFlow_A	576134620	2271910	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2271910	0	0
T4	314426	12346	0	0
T5	0	2562	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2271910	0	0
T4	314426	12346	0	0
T5	0	2562	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2271910	0	0
T4	314426	12346	0	0
T5	0	2562	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2271910	0	0
T4	314426	12346	0	0
T5	0	2562	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2271910	0	0
T4	314426	12346	0	0
T5	0	2562	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2271910	0	0
T4	314426	12346	0	0
T5	0	2562	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	0	0	922

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2271910	0	0
T4	314426	12346	0	0
T5	0	2562	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0