Module Definition
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Module : spid_readbuffer
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.23 97.30 97.14 90.48 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_readcmd.u_readbuffer 96.23 97.30 97.14 90.48 100.00



Module Instance : tb.dut.u_readcmd.u_readbuffer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.23 97.30 97.14 90.48 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.23 97.30 97.14 90.48 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.19 96.32 100.00 80.00 84.62 100.00 u_readcmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spid_readbuffer
Line No.TotalCoveredPercent
TOTAL373697.30
ALWAYS10344100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11211100.00
ALWAYS11844100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN13111100.00
ALWAYS13566100.00
ALWAYS1476583.33
ALWAYS16655100.00
ALWAYS17588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
103 1 1
104 1 1
105 1 1
106 1 1
MISSING_ELSE
111 1 1
112 1 1
118 2 2
119 2 2
MISSING_ELSE
122 1 1
131 1 1
135 1 1
136 1 1
137 1 1
140 1 1
141 1 1
142 1 1
MISSING_ELSE
147 1 1
149 1 1
150 1 1
151 1 1
152 1 1
157 0 1
MISSING_ELSE
MISSING_ELSE
166 2 2
167 1 1
168 1 1
170 1 1
175 1 1
177 1 1
179 1 1
181 1 1
183 1 1
185 1 1
MISSING_ELSE
191 1 1
193 1 1


Cond Coverage for Module : spid_readbuffer
TotalCoveredPercent
Conditions353497.14
Logical353497.14
Non-Logical00
Event00

 LINE       105
 EXPRESSION (active && flip)
             ---1--    --2-
-1--2-StatusTests
01CoveredT4,T39,T67
10CoveredT11,T15,T43
11CoveredT11,T15,T43

 LINE       112
 EXPRESSION (current_buffer_idx == next_buffer_addr)
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T4,T15

 LINE       122
 EXPRESSION (active && flip && ((!flip_q)))
             ---1--    --2-    -----3-----
-1--2--3-StatusTests
011CoveredT4,T39,T67
101CoveredT11,T15,T43
110Not Covered
111CoveredT11,T15,T43

 LINE       131
 EXPRESSION ((current_address_i[(spi_device_pkg::SramBufferAw - 1):0] >= threshold_i) && ((|threshold_i)))
             ------------------------------------1-----------------------------------    --------2-------
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT1,T2,T3
11CoveredT7,T9,T11

 LINE       137
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------
-1--2-StatusTests
01CoveredT7,T9,T11
10CoveredT11,T15,T43
11CoveredT11,T15,T43

 LINE       141
 EXPRESSION (active && flip)
             ---1--    --2-
-1--2-StatusTests
01CoveredT4,T39,T67
10CoveredT11,T15,T43
11CoveredT11,T15,T43

 LINE       149
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------
-1--2-StatusTests
01CoveredT7,T9,T11
10CoveredT11,T15,T43
11CoveredT11,T15,T43

 LINE       167
 EXPRESSION (spi_mode_i != FlashMode)
            ------------1------------
-1-StatusTests
0CoveredT11,T15,T6
1CoveredT7,T8,T9

 LINE       181
 EXPRESSION (start_i && (spi_mode_i == FlashMode) && ((!sfdp_hit_i)) && ( ! (mailbox_en_i && mailbox_hit_i) ))
             ---1---    ------------2------------    -------3-------    ------------------4------------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT7,T8,T9
1101CoveredT6,T28,T29
1110CoveredT6,T28,T29
1111CoveredT11,T15,T43

 LINE       181
 SUB-EXPRESSION (spi_mode_i == FlashMode)
                ------------1------------
-1-StatusTests
0CoveredT7,T8,T9
1CoveredT1,T2,T3

 LINE       181
 SUB-EXPRESSION ( ! (mailbox_en_i && mailbox_hit_i) )
                    ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T9,T12

 LINE       181
 SUB-EXPRESSION (mailbox_en_i && mailbox_hit_i)
                 ------1-----    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T9,T12
11CoveredT7,T9,T12

Branch Coverage for Module : spid_readbuffer
Line No.TotalCoveredPercent
Branches 21 19 90.48
IF 103 3 3 100.00
IF 118 3 3 100.00
IF 135 4 4 100.00
IF 149 4 3 75.00
IF 166 3 3 100.00
CASE 179 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 103 if ((!sys_rst_ni)) -2-: 105 if ((active && flip))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T15,T43
0 0 Covered T2,T3,T7


LineNo. Expression -1-: 118 if ((!sys_rst_ni)) -2-: 119 if (active)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T15,T43
0 0 Covered T2,T3,T7


LineNo. Expression -1-: 135 if ((!sys_rst_ni)) -2-: 137 if ((active && watermark_cross)) -3-: 141 if ((active && flip))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T11,T15,T43
0 0 1 Covered T11,T15,T43
0 0 0 Covered T2,T3,T7


LineNo. Expression -1-: 149 if ((active && watermark_cross)) -2-: 150 if ((!watermark_crossed)) -3-: 152 if (flip)

Branches:
-1--2--3-StatusTests
1 1 - Covered T11,T15,T43
1 0 1 Not Covered
1 0 0 Covered T11,T15,T68
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 166 if ((!rst_ni)) -2-: 167 if ((spi_mode_i != FlashMode))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T7,T8,T9
0 0 Covered T11,T15,T6


LineNo. Expression -1-: 179 case (st_q) -2-: 181 if ((((start_i && (spi_mode_i == FlashMode)) && (!sfdp_hit_i)) && (!(mailbox_en_i && mailbox_hit_i))))

Branches:
-1--2-StatusTests
StIdle 1 Covered T11,T15,T43
StIdle 0 Covered T1,T2,T3
StActive - Covered T11,T15,T43
default - Not Covered


Assert Coverage for Module : spid_readbuffer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
StartWithAddressUpdate_A 186997894 9806 0 0


StartWithAddressUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 186997894 9806 0 0
T4 100733 68 0 0
T5 0 16 0 0
T7 175857 10 0 0
T8 74526 2 0 0
T9 20428 4 0 0
T11 11749 8 0 0
T12 140178 8 0 0
T13 15516 12 0 0
T14 221150 6 0 0
T15 0 8 0 0
T17 4250 0 0 0
T18 101454 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%