Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13050263	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13577803

1

T1

897

T2

1851

T3

44

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17435213	1			T1	29		T2	1933		T3	1
values[0x0]	4593985	1			T1	455		T2	456		T3	27
values[0x1]	4598868	1			T1	434		T2	433		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9465533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17162533

1

T1

902

T2

2064

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	100979	1			T1	4		T2	9		T5	275
valid_sources[0x01]	104868	1			T2	16		T3	1		T5	270
valid_sources[0x02]	108979	1			T2	7		T4	5		T5	247
valid_sources[0x03]	102096	1			T5	258		T7	225		T8	6
valid_sources[0x04]	104180	1			T1	2		T2	7		T4	2
valid_sources[0x05]	105681	1			T1	3		T2	9		T3	1
valid_sources[0x06]	105842	1			T1	4		T2	21		T5	250
valid_sources[0x07]	101779	1			T1	1		T2	19		T5	274
valid_sources[0x08]	104181	1			T1	3		T2	13		T5	282
valid_sources[0x09]	100608	1			T1	1		T2	5		T5	253
valid_sources[0x0a]	101430	1			T1	2		T2	7		T5	274
valid_sources[0x0b]	104139	1			T2	10		T5	249		T7	198
valid_sources[0x0c]	102305	1			T1	7		T2	14		T5	254
valid_sources[0x0d]	106070	1			T1	10		T2	10		T5	289
valid_sources[0x0e]	102435	1			T1	1		T2	13		T4	1
valid_sources[0x0f]	108335	1			T1	3		T2	8		T5	261
valid_sources[0x10]	104769	1			T1	2		T2	11		T5	251
valid_sources[0x11]	101616	1			T1	8		T2	10		T5	250
valid_sources[0x12]	101707	1			T1	2		T2	15		T3	1
valid_sources[0x13]	108910	1			T2	18		T5	270		T7	217
valid_sources[0x14]	98602	1			T1	5		T2	29		T5	235
valid_sources[0x15]	104873	1			T1	1		T2	6		T5	243
valid_sources[0x16]	102645	1			T1	9		T2	3		T5	280
valid_sources[0x17]	100191	1			T1	2		T2	7		T5	231
valid_sources[0x18]	107642	1			T2	19		T5	225		T7	217
valid_sources[0x19]	113015	1			T2	19		T5	246		T7	173
valid_sources[0x1a]	101822	1			T1	3		T2	5		T5	269
valid_sources[0x1b]	102774	1			T1	4		T2	23		T5	235
valid_sources[0x1c]	101555	1			T1	4		T2	7		T5	237
valid_sources[0x1d]	102123	1			T1	6		T2	5		T5	240
valid_sources[0x1e]	102774	1			T2	13		T5	237		T7	217
valid_sources[0x1f]	99985	1			T1	2		T2	13		T5	226
valid_sources[0x20]	110635	1			T2	14		T5	264		T7	198
valid_sources[0x21]	98802	1			T1	9		T2	9		T5	251
valid_sources[0x22]	100887	1			T1	12		T2	11		T3	3
valid_sources[0x23]	105951	1			T2	15		T5	254		T7	255
valid_sources[0x24]	99749	1			T1	1		T2	2		T5	251
valid_sources[0x25]	103577	1			T1	3		T2	14		T5	242
valid_sources[0x26]	104064	1			T1	5		T2	9		T5	246
valid_sources[0x27]	104230	1			T1	3		T2	9		T5	247
valid_sources[0x28]	107562	1			T1	2		T2	10		T5	224
valid_sources[0x29]	102681	1			T1	3		T2	27		T5	223
valid_sources[0x2a]	106099	1			T1	8		T2	9		T5	242
valid_sources[0x2b]	105094	1			T1	5		T2	8		T5	238
valid_sources[0x2c]	106627	1			T1	4		T2	11		T3	2
valid_sources[0x2d]	102057	1			T2	27		T5	197		T7	170
valid_sources[0x2e]	103071	1			T1	1		T2	10		T5	276
valid_sources[0x2f]	108777	1			T1	3		T2	22		T5	208
valid_sources[0x30]	105783	1			T1	5		T2	16		T5	246
valid_sources[0x31]	103073	1			T1	4		T2	11		T5	233
valid_sources[0x32]	104823	1			T1	5		T2	10		T5	249
valid_sources[0x33]	110596	1			T2	4		T5	246		T7	205
valid_sources[0x34]	98552	1			T1	8		T2	12		T5	228
valid_sources[0x35]	103902	1			T2	13		T3	3		T5	232
valid_sources[0x36]	104455	1			T2	11		T5	241		T7	201
valid_sources[0x37]	107124	1			T1	3		T2	14		T3	2
valid_sources[0x38]	103588	1			T2	19		T3	1		T5	209
valid_sources[0x39]	103281	1			T1	14		T2	1		T5	277
valid_sources[0x3a]	102348	1			T2	7		T5	216		T7	186
valid_sources[0x3b]	100824	1			T1	2		T2	18		T5	258
valid_sources[0x3c]	104468	1			T2	1		T5	217		T7	170
valid_sources[0x3d]	104023	1			T1	3		T2	12		T5	232
valid_sources[0x3e]	100448	1			T1	2		T2	11		T5	252
valid_sources[0x3f]	106586	1			T1	7		T2	18		T5	242
valid_sources[0x40]	111672	1			T2	3		T5	295		T7	212
valid_sources[0x41]	109261	1			T2	11		T3	1		T5	274
valid_sources[0x42]	98239	1			T1	1		T2	16		T3	2
valid_sources[0x43]	102822	1			T2	16		T5	295		T7	225
valid_sources[0x44]	101064	1			T1	3		T2	11		T5	281
valid_sources[0x45]	101542	1			T2	14		T5	256		T7	214
valid_sources[0x46]	106809	1			T1	11		T2	15		T3	1
valid_sources[0x47]	102891	1			T1	12		T2	7		T5	216
valid_sources[0x48]	99835	1			T2	21		T3	1		T5	240
valid_sources[0x49]	109393	1			T1	3		T2	5		T5	201
valid_sources[0x4a]	106035	1			T2	7		T5	271		T7	220
valid_sources[0x4b]	109104	1			T2	26		T5	243		T7	244
valid_sources[0x4c]	104886	1			T1	3		T2	4		T5	258
valid_sources[0x4d]	103955	1			T1	1		T2	9		T3	1
valid_sources[0x4e]	99799	1			T1	11		T2	20		T5	243
valid_sources[0x4f]	101707	1			T1	1		T2	5		T5	243
valid_sources[0x50]	101918	1			T1	2		T2	10		T5	232
valid_sources[0x51]	105801	1			T1	8		T2	6		T5	238
valid_sources[0x52]	100934	1			T1	2		T2	8		T5	245
valid_sources[0x53]	98550	1			T1	1		T2	16		T3	1
valid_sources[0x54]	99555	1			T2	18		T5	228		T7	189
valid_sources[0x55]	102989	1			T1	12		T2	5		T5	249
valid_sources[0x56]	102259	1			T1	3		T2	17		T4	4
valid_sources[0x57]	104313	1			T1	2		T2	4		T5	230
valid_sources[0x58]	110935	1			T1	3		T2	5		T5	254
valid_sources[0x59]	102870	1			T2	6		T5	261		T7	201
valid_sources[0x5a]	101277	1			T1	5		T2	18		T5	267
valid_sources[0x5b]	99596	1			T2	10		T5	218		T7	202
valid_sources[0x5c]	105768	1			T2	8		T3	1		T5	269
valid_sources[0x5d]	99613	1			T1	3		T2	16		T3	1
valid_sources[0x5e]	105978	1			T2	24		T5	263		T7	250
valid_sources[0x5f]	100370	1			T1	6		T2	14		T3	2
valid_sources[0x60]	108473	1			T2	7		T5	274		T7	215
valid_sources[0x61]	110713	1			T1	3		T2	33		T5	294
valid_sources[0x62]	107056	1			T1	1		T2	8		T5	268
valid_sources[0x63]	109646	1			T1	7		T2	2		T5	284
valid_sources[0x64]	109606	1			T1	10		T2	11		T5	252
valid_sources[0x65]	103510	1			T1	8		T2	2		T5	252
valid_sources[0x66]	107521	1			T1	6		T2	24		T5	272
valid_sources[0x67]	99584	1			T1	3		T2	23		T5	274
valid_sources[0x68]	105918	1			T1	6		T2	8		T3	1
valid_sources[0x69]	106794	1			T1	1		T2	5		T4	1
valid_sources[0x6a]	101579	1			T1	6		T2	4		T5	253
valid_sources[0x6b]	103916	1			T2	10		T5	260		T7	170
valid_sources[0x6c]	108835	1			T1	3		T5	265		T7	213
valid_sources[0x6d]	105210	1			T2	2		T5	287		T7	196
valid_sources[0x6e]	105212	1			T1	6		T2	5		T5	255
valid_sources[0x6f]	106639	1			T1	1		T2	14		T5	249
valid_sources[0x70]	112021	1			T1	1		T2	11		T5	239
valid_sources[0x71]	102507	1			T1	4		T2	5		T5	248
valid_sources[0x72]	97930	1			T1	4		T2	20		T5	281
valid_sources[0x73]	103137	1			T1	2		T2	16		T5	246
valid_sources[0x74]	103558	1			T1	3		T2	16		T5	243
valid_sources[0x75]	108524	1			T1	12		T2	11		T5	237
valid_sources[0x76]	101965	1			T1	2		T2	4		T5	233
valid_sources[0x77]	99349	1			T2	2		T3	1		T5	253
valid_sources[0x78]	102399	1			T1	7		T2	10		T3	8
valid_sources[0x79]	107782	1			T1	5		T2	18		T5	249
valid_sources[0x7a]	107956	1			T1	4		T2	14		T5	252
valid_sources[0x7b]	105707	1			T1	12		T2	16		T5	248
valid_sources[0x7c]	97144	1			T1	1		T2	7		T5	222
valid_sources[0x7d]	106549	1			T1	1		T2	11		T5	230
valid_sources[0x7e]	106423	1			T1	2		T2	8		T3	1
valid_sources[0x7f]	106467	1			T1	11		T2	18		T3	1
valid_sources[0x80]	102335	1			T2	9		T5	235		T7	179

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5368532

1

T1

18

T2

965

T3

1

values[0x0]

all_enables

biggest_size

4135982

1

T1

450

T2

456

T3

19

values[0x1]

all_enables

biggest_size

4073289

1

T1

429

T2

430

T3

24