SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[spi_device_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21824898 | 1 | T1 | 86 | T2 | 1990 | T3 | 56 | ||||
auto[1] | 4843149 | 1 | T1 | 832 | T2 | 832 | T5 | 11611 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 26667485 | 1 | T1 | 918 | T2 | 2822 | T3 | 56 | ||||
values[1] | 55 | 1 | T86 | 2 | T88 | 4 | T89 | 1 | ||||
values[2] | 13 | 1 | T104 | 1 | T157 | 1 | T158 | 1 | ||||
values[3] | 281 | 1 | T86 | 15 | T88 | 9 | T89 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 26667493 | 1 | T1 | 918 | T2 | 2822 | T3 | 56 | ||||
values[1] | 55 | 1 | T86 | 2 | T88 | 2 | T89 | 1 | ||||
values[2] | 13 | 1 | T89 | 1 | T159 | 1 | T160 | 1 | ||||
values[3] | 280 | 1 | T86 | 7 | T88 | 8 | T89 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 26667197 | 1 | T1 | 918 | T2 | 2822 | T3 | 56 | ||||
auto[TlIntgErrCmd] | 296 | 1 | T86 | 16 | T88 | 12 | T89 | 3 | ||||
auto[TlIntgErrData] | 288 | 1 | T86 | 7 | T88 | 7 | T89 | 3 | ||||
auto[TlIntgErrBoth] | 266 | 1 | T86 | 7 | T88 | 11 | T89 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |