Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13090056

1

T1

21

T2

971

T3

12

full_word

13577991

1

T1

897

T2

1851

T3

44

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	26667197	1			T1	918		T2	2822		T3	56
auto[TlIntgErrCmd]	296	1			T86	16		T88	12		T89	3
auto[TlIntgErrData]	288	1			T86	7		T88	7		T89	3
auto[TlIntgErrBoth]	266	1			T86	7		T88	11		T89	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17440298

1

T1

29

T2

1933

T3

1

auto[1]

9227749

1

T1

889

T2

889

T3

55

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	12071021	1			T1	11		T2	968		T4	63
auto[TlIntgErrNone]	partial	auto[1]	1018260	1			T1	10		T2	3		T3	12
auto[TlIntgErrNone]	full_word	auto[0]	5368896	1			T1	18		T2	965		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	8209020	1			T1	879		T2	886		T3	43
auto[TlIntgErrCmd]	partial	auto[0]	120	1			T86	7		T88	3		T89	1
auto[TlIntgErrCmd]	partial	auto[1]	154	1			T86	9		T88	7		T89	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T161	1		T162	1		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	17	1			T88	2		T164	1		T104	1
auto[TlIntgErrData]	partial	auto[0]	133	1			T86	3		T88	6		T89	1
auto[TlIntgErrData]	partial	auto[1]	129	1			T86	4		T88	1		T89	2
auto[TlIntgErrData]	full_word	auto[0]	12	1			T165	1		T159	1		T150	1
auto[TlIntgErrData]	full_word	auto[1]	14	1			T164	1		T104	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	101	1			T86	4		T88	3		T89	1
auto[TlIntgErrBoth]	partial	auto[1]	138	1			T86	3		T88	6		T89	2
auto[TlIntgErrBoth]	full_word	auto[0]	10	1			T150	1		T166	1		T167	1
auto[TlIntgErrBoth]	full_word	auto[1]	17	1			T88	2		T89	1		T157	1